KR100749618B1 - Plasma Display Panel - Google Patents

Abstract

The present invention relates to a plasma display panel, and more particularly, to a partition structure having a delta partition wall in which two address electrodes are assigned to one pixel instead of a conventional delta partition wall in which three address electrodes are assigned to one pixel. The present invention relates to a plasma display panel including an intermediate electrode, and increasing the dielectric constant of the dielectric layer covering the intermediate electrode as compared to the other side, or by using an electron-emitting material instead of the dielectric layer, thereby improving the light emission efficiency by reducing the discharge voltage.

Plasma Display Panels, Delta Bulkheads, Intermediate Electrodes, Emission Materials

Description

Plasma Display Panel

1 is an exploded perspective view of a PDP according to an embodiment of the present invention;

2 is a layout view of a discharge cell and electrodes according to an embodiment of the present invention;

Figure 3a is a vertical cross-sectional view of the PDP according to an embodiment of the present invention (K-K cross-sectional view of Figure 2)

3B is a vertical cross sectional view of a PDP according to another embodiment of the present invention;

4 is a driving waveform diagram of a PDP according to an embodiment of the present invention;

5A to 5E are schematic diagrams schematically illustrating wall charge distribution according to a driving waveform shown in FIG. 4.

<Description of Symbols for Main Parts of Drawings>

100, 200-PDP 110, 220-Front panel

120, 220-display electrode 122, 222-X electrode

124, 224-Y electrode 126, 226-M electrode

130, 230-second upper dielectric layer 132, 232-electron-emitting material layer (first upper dielectric layer)

135, 235-Protective layer 140, 240-Back board

150, 250-A electrode 160, 260-Lower dielectric layer

170, 270-Bulkhead 180, 280-Phosphor layer

190-pixels

The present invention relates to a plasma display panel, and more particularly, to a partition structure having a delta partition wall in which two address electrodes are assigned to one pixel instead of a conventional delta partition wall in which three address electrodes are assigned to one pixel. The present invention relates to a plasma display panel including an intermediate electrode, and increasing the dielectric constant of the dielectric layer covering the intermediate electrode as compared to the other side, or by using an electron-emitting material instead of the dielectric layer, thereby improving the light emission efficiency by reducing the discharge voltage.

In general, a plasma display panel (hereinafter referred to as a PDP) is a display device that realizes an image by using visible light generated by excitation of a phosphor by vacuum ultraviolet rays (VUV) emitted from a plasma obtained through gas discharge. to be. Such a PDP can realize an ultra-large screen of 60 inches or more with a thickness of only 10 cm or less, and is a self-luminous display device such as a CRT. In addition, since the manufacturing method is simpler than LCD, it has advantages in terms of productivity and cost, and thus, it is being spotlighted as the next-generation industrial flat panel display and home TV display.

Such a conventional PDP generally includes a front substrate having a plurality of display electrodes and a back substrate having a plurality of address electrodes to intersect the display electrodes. In addition, a plurality of partition walls are formed between the front substrate and the rear substrate so as to partition the plurality of discharge regions. There are various structures of such a partition, such as stripe type, matrix type, and delta type.

Among these, in the case of a PDP having a delta partition, three discharge cells are normally adjacent to each other to form one pixel. Each of the discharge cells has a red (R) fluorescent layer, a green (G) fluorescent layer, and a blue (R) fluorescent layer. Three address electrodes are normally assigned to one pixel.

On the other hand, in recent years, as the resolution of the PDP is increased, that is, as the resolution is increased, the number of address electrodes gradually increases and the pitch between the address electrodes is also reduced. However, as is well known, as the pitch between address electrodes decreases, the capacitance value between address electrodes increases, and energy calculated as approximately CV ² f is consumed between the address electrodes. In other words, it is necessary to increase the power consumption of the address electrode to make a high resolution PDP. Since a discharge voltage much larger than that of the display electrode can be applied to the address electrode, an increase in power consumption of the address electrode is directly related to an increase in power consumption of the entire PDP. Here, C is a capacitance value generated between address electrodes, V is a voltage applied to the address electrode, and f is a frequency applied to the address electrode.

As the size of the cell becomes smaller, the amount of phosphor decreases due to the high resolution, which is a major trend of PDP technology. Therefore, since the luminance is reduced, there is a problem that an increase in the discharge voltage is inevitable in order to have an appropriate luminance. In addition, when the resolution is high, the wall charges are not sufficiently formed on the electrodes because there are not enough charged particles in the discharge space. Therefore, there is a problem that the discharge voltage is increased. For high efficiency, another main trend of PDP technology, high discharge voltage is required to use high Xe partial pressure gas. Accordingly, there is a need to propose a barrier rib structure and an electrode structure capable of reducing capacitance between address electrodes due to high resolution and suppressing an increase in discharge voltage due to high resolution.

The present invention has been made to solve the above problems, and in particular, a partition structure having a delta partition wall in which two address electrodes are allocated per pixel instead of a conventional delta partition wall in which three address electrodes are allocated in one pixel. By providing one more intermediate electrode, and increasing the dielectric constant of the dielectric layer covering the intermediate electrode than the other side or by using an electron-emitting material in place of the dielectric layer, to provide a plasma display panel with high definition and low discharge voltage to improve the luminous efficiency Its purpose is to.

Plasma display panel according to an embodiment of the present invention devised to solve the above problems is a front substrate and a rear substrate facing each other; A partition wall formed between the front substrate and the rear substrate and partitioning the discharge cells so that three discharge cells emitting different colors of visible light are adjacent to each other to form one pixel; First and second display electrodes formed between the front substrate and the rear substrate; Address electrodes allocated to each one of the discharge cells divided by the barrier ribs; An intermediate electrode disposed between the first display electrode and the second display electrode to correspond to each of the discharge cells; And an electron-emitting material layer coated on the intermediate electrode.

In this case, one address electrode may be commonly assigned to two selected discharge cells among the three discharge cells constituting the one pixel, and another address electrode may be allocated to the other discharge cell. In addition, the first display electrode, the second display electrode and the intermediate electrode may be formed in parallel with each other on the rear surface of the front substrate, and the intermediate electrode may be formed between the first display electrode and the second display electrode. have. In addition, the first display electrode and the second display electrode may be formed in parallel with each other in the partition wall, and the first display electrode and the second display electrode may be formed of a metal electrode.

In addition, the electron emission material layer may be formed between the intermediate electrode and the back substrate, and a dielectric layer may be formed at a portion adjacent to the side of the electron emission material layer. In this case, the electron-emitting material layer may be made of carbon nanotubes (CNT) or carbonates.

In addition, the plasma display panel according to another embodiment of the present invention includes a front substrate and a rear substrate facing each other; A partition wall formed between the front substrate and the rear substrate and partitioning the discharge cells so that three discharge cells emitting different colors of visible light are adjacent to each other to form one pixel; First and second display electrodes formed between the front substrate and the rear substrate; Two address electrodes each allocated to one pixel including discharge cells separated by the barrier ribs; An intermediate electrode disposed between the first display electrode and the second display electrode to correspond to each of the discharge cells; And a dielectric layer formed between the intermediate electrode and the back substrate, wherein the dielectric layer includes a first upper dielectric layer adjacent to the intermediate electrode and a second upper dielectric layer formed on a side of the first upper dielectric layer. The dielectric layer and the second upper dielectric layer are characterized in that the dielectric constant is different from each other.

In this case, one address electrode may be commonly assigned to two selected discharge cells among the three discharge cells constituting the one pixel, and another address electrode may be allocated to the other discharge cell. In addition, the first display electrode, the second display electrode and the intermediate electrode may be formed in parallel with each other on the rear surface of the front substrate, and the intermediate electrode may be formed between the first display electrode and the second display electrode. have. In addition, the first display electrode and the second display electrode may be formed in parallel with each other in the partition wall, and the first display electrode and the second display electrode may be formed of a metal electrode.

In addition, the first upper dielectric layer is preferably formed to have a higher dielectric constant than the second upper dielectric layer. In this case, the dielectric constant of the first upper dielectric layer may be formed to be at least 15, and the dielectric constant of the second upper dielectric layer may be formed to be 10 to 14.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a PDP according to an embodiment of the present invention will be described.

1 is an exploded perspective view of a PDP according to an embodiment of the present invention, FIG. 2 is a layout view of the discharge cells and electrodes of FIG. 1, and FIG. 3A is a cross-sectional view of the PDP according to an embodiment of the present invention (FIG. 2). KK cross-sectional view). In the embodiment of FIG. 3A, the intermediate electrode is covered with the first upper dielectric layer having a relatively higher dielectric constant than the electron emitting material layer or the second upper dielectric layer. Hereinafter, reference numerals of the electron emission material layer and the first upper dielectric layer will be referred to. The same code is used. In addition, the first display electrode 122 and the second display electrode 124 are referred to as a display electrode 120.

1 to 3A, the PDP 100 according to an embodiment of the present invention, the front substrate 110, the rear substrate 140 and the first display electrode 122 (hereinafter referred to as X electrode) And second display electrodes 124 (hereinafter referred to as Y electrodes) and intermediate electrodes 126 (hereinafter referred to as M electrodes). In addition, the X electrodes 122 and the Y electrodes 124 are covered by the second upper dielectric layer 130, and the second upper dielectric layer 130 is protected by the protective layer 135. In addition, the M electrodes 126 are covered with the electron emission material layer 132 or the first upper dielectric layer 132, and the electron emission material layer 132 has no protective layer 135 formed thereon. In addition, the address electrodes 150 (hereinafter referred to as “A electrodes”) are covered by the lower dielectric layer 160 and absorb vacuum vacuum inside the discharge cells 191, 192, and 193 partitioned by the partition wall 170. A phosphor layer 180 for emitting visible light is provided and filled with a discharge gas for generating vacuum ultraviolet rays by plasma discharge. In the PDP 100, the X electrode 122, the Y electrode 124, and the M electrode 126 are formed parallel to each other on the rear surface of the front substrate 110, and the M electrode 126 is the X electrode 122. And between Y electrode 124.

The back substrate 140 is formed of a material such as glass having a predetermined thickness to form the plasma display panel 100 together with the front substrate 110. The rear substrate 140 is formed with the A electrodes 150 disposed in one direction on the upper surface facing the front substrate 110 and the lower dielectric layer 160 applied to cover the A electrodes 150. The partition wall 170 is formed on the dielectric layer 160. The phosphor layer 180 is formed on the lower dielectric layer 160 and the partition wall 170. Hereinafter, the front substrate 110 direction (the + z direction in FIG. 1) will be divided into the upper direction, and the back substrate 140 direction (the -z direction in FIG. 1) will be described in the lower direction.

The front substrate 110 is formed of a transparent material such as soda glass, and is formed to face the rear substrate 140. The X electrode 122, the Y electrode 124, and the M electrode 126 are arranged side by side under the front substrate 110, and the X electrode 122 and the Y electrode 124 are formed on the upper dielectric layer ( 130, the upper dielectric layer 130 is protected by a protective layer 135. Meanwhile, when the M electrodes 122 are covered by the electron emission material layer 132, a separate protective layer is not formed for smooth emission of electrons.

The partition wall 170 may be formed to a predetermined thickness on the surface of the lower dielectric layer 160 formed on the rear substrate 140 as shown in FIG. 1, or may be formed separately from the rear substrate 140. The partition wall 170 may be formed of a triangle, a square, a rhombus, a pentagon, a hexagon, and the like. Although the partition wall 170 of the hexagonal shape is shown in the figure, it does not limit the present invention in this form. That is, this invention is applicable to all the partitions of a closed type. The partition wall 170 maintains a gap between the front substrate 110 and the rear substrate 140 and partitions the discharge cells 191, 192, and 193.

The barrier rib 170 is formed such that three discharge cells 191, 192, and 193 emitting visible light having different colors are adjacent to each other in a substantially triangular form to form one pixel 190. Here, two A electrodes 150 are allocated to one pixel 190 divided by the partition wall 170. That is, one A electrode 150 is commonly allocated to two selected discharge cells 192 and 193 among three discharge cells 191, 192 and 193, and the other A electrode is assigned to the other discharge cell 191. 150 may be assigned.

The barrier rib 170 may be formed by screen printing, sand blasting, lift-off, etching, or the like, but the method of forming the barrier rib 170 is not limited thereto. In addition, the partition wall 170 is formed of a glass component containing elements such as Pb, B, Si, Al and O, preferably zirconium oxide (ZrO 2), titanium oxide (TiO 2), aluminum oxide (Al 2 O 3) and It is formed of a dielectric including the same filler and pigments such as chromium (Cr), copper (Cu), cobalt (Co), iron (Fe) and the like. However, the components of the barrier rib 170 are not limited thereto, but may be formed of various dielectric materials.

The second upper dielectric layer 130 covers the bottom surface of the front substrate 110 including the X electrode 122 and the Y electrode 124 except for the M electrode 126. The upper dielectric layer 130 may be formed by uniformly screen printing a paste including a low melting point glass powder on the entire lower surface of the front substrate 110. The upper dielectric layer 130, as is well known, is a transparent body, acts as a capacitor during discharge, limits the current and performs a memory function. In addition, a protective layer 135 may be further formed on the surface of the upper dielectric layer 130 to reinforce durability and to emit many secondary electrons during discharge. The protective layer 135 may be formed by an electron beam method or sputtering using any one selected from magnesium oxide (MgO) or equivalents thereof, but the material of the protective layer and the method of forming the protective layer 135 are not limited thereto.

The electron emission material layer 132 is formed to have a thickness reaching the surface of the protective layer 135 surrounding the lower portion of the M electrode 126. The left and right sides of the electron-emitting material layer 132 contact the second upper dielectric layer 130 and may be formed by screen printing or the like. The electron emission material layer 132 is made of a material capable of emitting electrons in an electric field, such as carbon nanotubes (CNT) or carbonates. The carbon nanotubes are new materials in which hexagons made of six carbons are connected to each other to form a tubular shape, and may be conductors or semiconductors according to a molecular arrangement. In addition, the carbon nanotubes emit a large amount of electrons when an electric field of a predetermined size or more is applied. Therefore, when carbon nanotubes are used as the electron emission material layer 132, a large amount of electrons are emitted as the voltage is applied, thereby increasing the number of charged particles. Therefore, even though the PDP is fixed, a large amount of charged particles can be generated in a small discharge space, so that plasma discharge can be sufficiently generated even at a low discharge voltage. In addition, the carbon nanotubes have much stronger bonds between carbon atoms than silicon, which is currently dominated by semiconductors. Thus, the carbon nanotubes are chemically extremely stable and strong even at high temperatures, and are resistant to heat and friction. Therefore, carbon nanotubes can be used as a surface material, and thus, a separate protective layer is not required, and when the protective layer is formed, it is an obstacle to electron emission. In addition, the carbon nanotubes have high thermal conductivity and thus release heat well. The carbonate is a salt in which hydrogen of carbonate (H ₂ CO ₃ ) is replaced with a metal, and is a salt composed of carbon dioxide (CO ₂ ) and a metal oxide or hydroxide. Like the carbon nanotubes, the carbonates emit electrons or ions in an electric field of a predetermined size or more. Even when carbonate is used as the electron emission material layer 132, a protective layer is not formed for smooth discharge of charged particles.

Like the electron emission material layer 132, the first upper dielectric layer 132 is formed to have a thickness reaching the surface of the protective layer 135 by surrounding the lower portion of the M electrode 126. Left and right sides of the first upper dielectric layer 132 are in contact with the second upper dielectric layer 130, and may be formed by screen printing. The first upper dielectric layer 132 has a dielectric constant different from that of the second upper dielectric layer 130. The dielectric constant is adjustable by varying the material of the dielectric. Typically, the upper dielectric layer is composed of PbO / SiO ₂ / B ₂ O ₃ / Al ₂ O ₃ / TiO ₂ , and the first three materials constitute the mainstream of the upper dielectric layer. Here, the PbO is known to increase the dielectric constant, the SiO ₂ is known to lower the dielectric constant. Accordingly, the first upper dielectric layer 132 and the second upper dielectric layer 130 may be formed to have different dielectric constants by controlling the composition ratio of PbO and SiO ₂ . In this case, the first upper dielectric layer 132 may be formed to have a higher dielectric constant than the second upper dielectric layer 130. In this case, the dielectric constant of the first upper dielectric layer 132 may be formed to be at least 15, and the dielectric constant of the second upper dielectric layer 130 may be formed to be 10 to 14, except that It is not. Since the first upper dielectric layer 132 is formed to have a relatively high dielectric constant, a larger amount of wall charges may be stored. Therefore, even though the PDP is fixed, a large amount of wall charges may be accumulated, thereby lowering the discharge voltage. The method of forming the dielectric constant of the first upper dielectric layer 132 to be larger than that of the second upper dielectric layer 130 can be performed, for example, by reducing the composition ratio of SiO ₂ and increasing the composition ratio of PbO. However, the method of allowing the first upper dielectric layer 132 to have a relatively large dielectric constant is not limited to the above example.

The lower dielectric layer 160 covers the entire upper surface of the back substrate 140 including the A electrode 150. The lower dielectric layer 160 may also be formed of a material similar to or the same as that of the second upper dielectric layer 130.

The A electrodes 150 are formed on an upper side of the rear substrate 140 toward the second upper dielectric layer 130 of the front substrate 110. The A electrode 150 has a predetermined pitch on the top surface of the back substrate 140 and is formed in parallel with each other. The A electrode 150 is formed in a direction substantially crossing the display electrode 120. One A electrode 150 is formed in a discharge cell (191, 192, 193) or each of the different fluorescent layer 180 (y direction in Figure 1) that emits visible light of different colors, respectively. The A electrode 150 may be formed by sputtering, screen printing, photolithography or the like using Ag paste or the like, but the present invention is not limited to the material and method of forming the A electrode 150.

The display electrode 120 has a predetermined pitch on the lower surface of the front substrate 110 and is formed in parallel with each other. The display electrode 120 is a pair of the X electrode 122 and the Y electrode 124. The display electrode 120 is formed of the transparent electrodes 122a and 124a, and low-resistance bus electrodes 122b and 124b may be further formed to prevent voltage drop. The transparent electrodes 122a and 124a may be formed of any one selected from ITO (alloy oxide film of In and Sn) having good light transmittance, nesa film (SnO 2), or an equivalent thereof, but the present invention is not limited thereto. . In addition, the display electrode 120 may be formed mainly by sputtering, but the present invention is not limited thereto. In addition, the bus electrodes 122b and 124b may be formed of any one selected from Cr-Cu-Cr, Ag, or equivalents thereof, but the present invention is not limited thereto.

Referring to FIG. 2, the display electrode 120 is formed in the transverse direction along the partition wall 170. For example, the X electrode X1 is formed while laterally surrounding the R discharge cell and the G discharge cell. The Y electrode Y1 is formed while enclosing the G discharge cells and the B discharge cells laterally. Therefore, discharge cells coated with phosphors having different colors are contacted with the X electrode 122 and the Y electrode 124. For example, the X display electrode X1 forms a boundary between an R discharge cell and a G discharge cell, and also forms a boundary between a G discharge cell and a B discharge cell. The reason why the display electrode 120 is positioned on the partition wall 170 is to solve the problem of narrowing the discharge space according to the high definition of the PDP, and the visible light is blocked by the bus electrodes 122b and 124b so that the luminance is improved. This is to prevent the phenomenon of being lowered. The M electrode 126 is formed between the X electrode 122 and the Y electrode 124 constituting the display electrode 120 so as to correspond to each discharge cell and be parallel to the X electrode 122 and the Y electrode 124. do. Accordingly, the M electrode 126 is positioned on the rear surface of the front substrate 110 together with the display electrode 120.

Like the display electrode 120, the M electrode 126 also includes a transparent electrode 126a and a bus electrode 126b and is covered by the electron emission material layer 132 or the first upper dielectric layer 132. The M electrode 126 is a bus electrode 126a extending long over the discharge cell in a direction (x direction) intersecting with the A electrode 150, from the bus electrode 126b to the X electrode 122 and The transparent electrodes 126a protrude toward each of the Y electrodes 124. At this time, the bus electrode 126b is preferably made of a metal electrode in order to compensate for the high resistance of the transparent electrode 126a and to secure electricity conduction.

The M electrode 126 may be involved in a reset discharge in a reset period, and in an addressing period, the M electrode 126 is involved in selecting a discharge cell to be displayed while causing an address discharge between the A electrode 150. However, the role thereof may vary depending on the discharge voltage applied to each electrode, and the present invention is not limited thereto. As addressing is performed using the M electrode 126 and the A electrode 150, the opaque bus electrodes 122b and 124b that block light generated from the phosphor can be positioned above the partition 170. The brightness is improved. In addition, as the discharge between the display electrodes 120 becomes a discharge during the sustain discharge period, the gap between the display electrodes 120 increases, which leads to an increase in discharge efficiency.

The phosphor layer 180 has a component for generating visible light by receiving ultraviolet rays. The red phosphor layer formed in the red light emitting discharge cell includes a phosphor such as Y (V, P) O4: Eu, and the green light emitting discharge cell. The green phosphor layer formed at includes a phosphor such as Zn 2 SiO 4: Mn, and the blue phosphor layer formed at the blue light emitting discharge cell may be formed including a phosphor such as BAM: Eu. Accordingly, the phosphor layer 180 is divided into red, green, and blue light emitting phosphor layers, and is formed in each of the discharge cells 191, 192, and 193 adjacent to each other, and the red, green, and blue light emitting phosphor layers are formed. The formed discharge cells 191, 192, and 193 are combined to form unit pixels for implementing a color image.

Looking at the relationship between the phosphor layer 180 and the A electrode 150, for example, one A electrode 150 is commonly assigned to the red phosphor layer and the green phosphor layer among the phosphor layers 180, and the remaining blue Another A electrode 150 may be allocated to the phosphor layer. Of course, one A electrode 150 may be allocated to the green phosphor layer and the blue phosphor layer of the phosphor layer 180 in common, and the other A electrode 150 may be allocated to the other red phosphor layer. . In addition, one A electrode 150 may be allocated to the blue phosphor layer and the red phosphor layer of the phosphor layer 180 in common, and the other A electrode 150 may be allocated to the other green phosphor layer.

The discharge cells 191, 192, and 193 may include the lower dielectric layer 160, the barrier rib 170, the second upper dielectric layer 130, the electron emission material layer 132, or the first upper dielectric layer ( 132 is formed to be limited. The discharge cells 191, 192, and 193 are filled with a discharge gas (eg, a mixed gas including xenon (Xe), neon (Ne), etc.) to cause plasma discharge. In addition, as described above, the discharge cells 191, 192, and 193 have a phosphor layer 180 that absorbs ultraviolet rays and emits visible light in a predetermined region. The discharge cells 191, 192, and 193 may have different widths or lengths depending on the luminous efficiency of each phosphor. In the discharge cells 191, 192, and 193, electrodes which undergo address discharge and sustain discharge are disposed at the center and the bottom thereof.

A plurality of discharge cells 191, 192, and 193 are repeatedly arranged along one A electrode 150, and each discharge cell 191, 192, and 193 is arranged to emit visible light of different colors. have. For example, when centering on the A electrodes 150 in the first column from the left side shown in FIG. 2, the discharge cells R having a red fluorescent layer from the top to the bottom and the discharge cells G having a green fluorescent layer are shown. And the discharge cells B having the blue fluorescent layer may be repeatedly arranged in the vertical direction. In addition, when the A electrode 150 of the second column is centered, the discharge cell G having the green fluorescent layer from the top to the bottom direction G, the discharge cell B having the blue fluorescent layer B, and the discharge cell R having the red fluorescent layer R ) May be arranged in the vertical direction repeatedly.

A pair of display electrodes 120 may be allocated to one pixel 190 divided by the partition wall 170. That is, the X1 X electrode and the Y1 Y electrode are commonly allocated to the two discharge cells 191 and 192, and the Y1 Y electrode is allocated to the other discharge cell 193.

Next, a structure of a PDP according to another embodiment of the present invention will be described. 2 is a layout view of discharge cells and electrodes according to another embodiment of the present invention, and FIG. 3B is a vertical cross-sectional view of a PDP according to another embodiment of the present invention. Since the embodiment of FIG. 3B is similar to the embodiment of FIG. 3A except that the X electrode and the Y electrode are formed in the partition wall, the description will be mainly focused on differences.

The PDP 200 according to another embodiment of the present invention is formed by including the front substrate 210, the rear substrate 240, the X electrodes 222, the Y electrodes 224, and the M electrodes 226. In addition, the PDP 200 may include the first upper dielectric layer 232 or the electron emitting material layer 232, the second upper dielectric layer 230, the protective layer 235, the lower dielectric layer 260, and the A electrode 250. It is formed to include. In addition, the PDP 200 includes a partition 270 and a fluorescent layer 280. The front substrate 210, the back substrate 240, the first upper dielectric layer 232 or the electron emitting material layer 232, the second upper dielectric layer 230, the protective layer 235, the lower dielectric layer 260 and A Since the electrodes 250 have been sufficiently described in the embodiment of FIG. 3A, detailed description thereof will be omitted.

Referring to FIG. 3B, the X electrode 222 and the Y electrode 224 are formed parallel to each other in the partition 270. Since the X electrode 222 and the Y electrode 224 are disposed inside the partition wall 270 and do not require transparency, the X electrode 222 and the Y electrode 224 may be formed of a metal electrode of a general conductive metal. That is, it may be formed of only the bus electrode without the transparent electrode. The X electrode 222 and the Y electrode 224 are preferably formed of a metal material having high conductivity and low resistance, such as silver (Ag), aluminum (Al), copper (Cu), and the like, and the response speed of discharge It is fast and the signal is not distorted, and it can reduce power consumption required for sustain discharge. However, the material of the X electrode 222 and the Y electrode 224 is not limited thereto, and various metals having excellent conductivity and low resistance may be used. However, the M electrode 226 is disposed on the rear surface of the front substrate 210 as in the embodiment of FIG. 3A to contribute to reset discharge and address discharge. Thus, by placing the X electrode 222 and the Y electrode 224 inside the partition wall 270 to form an opposing electrode structure, the discharge space is larger and the discharge path is longer than the surface discharge electrode structure, so that the luminous efficiency is increased and the luminance is improved. It has the advantage of being.

In this way, in the PDP according to the present invention, two A electrodes are allocated to one pixel, so that the number of A electrodes is reduced to approximately 2/3 as compared with the prior art, and thus the power consumption is also reduced to approximately 2/3. . In addition, the power required by one circuit to drive the A electrode is also reduced compared with the conventional, the heat release rate is also significantly smaller than the conventional.

In addition, since the number of A electrodes in the same area is reduced, the pitch between A electrodes is naturally increased, so that the capacitance between A electrodes is also reduced. In other words, since it can be seen that the number of A electrodes can be increased in the same area as before, the structure is advantageous for high definition of the PDP.

In addition, the M electrode is covered with an electron emission material layer or a dielectric layer having a relatively high dielectric constant, thereby increasing the amount of charged particles or increasing the amount of wall charge, thereby lowering the discharge voltage despite high resolution.

Next, an embodiment of a driving waveform that can be applied to the PDP according to the present invention will be described in consideration of the fact that the M electrode is further provided. 4 is a driving waveform diagram of a PDP according to an exemplary embodiment of the present invention, and FIGS. 5A to 5E are schematic diagrams showing a wall charge distribution according to the driving waveform shown in FIG. 4. Hereinafter, a driving method according to the present exemplary embodiment will be described with reference to FIGS. 4 to 5E.

In the driving method according to the embodiment of the present invention, referring to FIG. 4, each subfield includes a reset section, an address section, and a sustain section. The reset section is composed of an erasing section, an M electrode rising waveform section and an M electrode falling waveform section.

The erasing section I of the reset section erases wall charges formed in the previous sustain discharge section. According to the present embodiment, it is assumed that the sustain discharge voltage pulse is applied to the X electrode at the last time of the sustain discharge interval, and that a voltage lower than the voltage applied to the X electrode (eg, the ground voltage) is applied to the Y electrode. Then, as illustrated in FIG. 5A, positive wall charges are formed on the Y electrode and the A electrode, and negative wall charges are formed on the X electrode and the M electrode. In the erasing period (I), while the Y electrode is biased with the voltage Vyc, a ramp waveform that gently drops from the Vmc voltage to the ground voltage is applied to the M electrode. Then, as shown in Fig. 5A, the wall charges formed during the sustain discharge section are erased.

In the reset period, the M electrode rising waveform section II applies a ramp waveform that rises slowly from the voltage Vmd to Vset to the M electrode while biasing the X electrode and the Y electrode with the ground voltage. While this rising waveform is applied, a weak reset discharge occurs in all discharge cells from the M electrode to the A electrode, the X electrode, and the Y electrode, respectively. As a result, as shown in Fig. 5B, negative wall charges are accumulated on the M electrode, and positive wall charges are accumulated on the A electrode, the X electrode, and the Y electrode at the same time.

In the M electrode falling waveform section III of the reset section, a ramp waveform that gently falls from the voltage Vme toward the ground voltage is applied to the M electrode while the X and Y electrodes are biased to Vxe and Vye, respectively. At this time, it is preferable to set Vxe = Vye and Vmd = Vme in that the circuit configuration can be simplified, but is not necessarily limited thereto. While this ramp voltage is falling, a weak reset discharge occurs again in all the discharge cells. At this time, since the M electrode falling waveform section is for slowly decreasing the wall charges accumulated by the M electrode rising waveform section, the wall charge amount that decreases with longer time of the falling waveform (that is, the slope is gentle) is precisely reduced. It is advantageous to address discharge because it can be controlled.

As a result of applying the falling waveform to the M electrode, the wall charges accumulated on each electrode of all the cells are evenly erased. As shown in FIG. 5C, positive wall charges are accumulated on the A electrode, and at the same time, the X electrode and the Y electrode (-) Wall charges are stored in the M electrode.

In the address period, while a plurality of M electrodes are biased to the Vsc voltage, scan pulses are sequentially applied to the M electrodes to apply scan pulses, and at the same time, an address voltage Va is applied to a cell to be discharged to the A electrode. ) Is applied. At this time, the X electrode is maintained at the ground voltage, and the voltage Vye is applied to the Y electrode. Then, discharge occurs between the M electrode and the A electrode, and the discharge is extended to the X electrode and the Y electrode. As a result, as shown in FIG. 5D, positive wall charges are accumulated on the X electrode and the M electrode, and Negative wall charges are accumulated in the electrode and the A electrode.

In the sustain discharge section, the sustain discharge voltage pulse is alternately applied to the X electrode and the Y electrode while the M electrode is biased at the sustain discharge voltage Vm. The sustain discharge occurs in the discharge cells selected in the address section through the application of such a voltage. At this time, according to the present embodiment, the discharge is generated by different discharge mechanisms at the initial and normal time of sustain discharge. For convenience of explanation, hereinafter, a discharge generated at the initial stage of sustain discharge is referred to as a short-gap discharge section, and a discharge at a normal time point is referred to as a long-gap discharge section.

In the start period of sustain discharge, as shown in (a) and (b) of FIG. 5E, a positive voltage pulse is applied to the X electrode and a negative voltage pulse is applied to the Y electrode, but at the same time, A positive voltage pulse is applied to the M electrode. Therefore, unlike the conventional case where the discharge occurs only between the X electrode and the Y electrode, the discharge occurs between the M electrode and the Y electrode. In particular, according to the present embodiment, since the distance between the M electrode and the Y electrode is closer than the distance between the X electrode and the Y electrode, the electric field applied between the M electrode and the Y electrode becomes larger. Therefore, the discharge between the M electrode and the Y electrode plays a leading role than the discharge between the X electrode and the Y electrode. As described above, in the present embodiment, since the discharge between the M electrode and the Y electrode having a relatively short distance plays a dominant role in the initial stage of sustain discharge, it is called a short gap discharge.

As described above, according to the present embodiment, since a short gap discharge occurs by applying a relatively high electric field at the initial stage of sustain discharge, sufficient discharge is performed even if sufficient charge particles are not generated in the discharge cell when the first sustain discharge pulse is applied after the address period. can do.

After application of the first sustain discharge pulse of sustain discharge, since the voltage of the M electrode is biased to a constant voltage Vm, the discharge between the M electrode and the X electrode or the discharge between the M electrode and the Y electrode contributes little to the discharge. The former is discharged between the X electrode and the Y electrode, and finally the image inputted by the number of discharge pulses applied to the X electrode and the Y electrode can be displayed. That is, as shown in (d) of FIG. 5E, (-) wall charges continuously accumulate in the M electrode, and (-) wall charge and ( +) Wall charges accumulate.

As described above, according to the present embodiment, since the discharge is performed by the short gap discharge between the X electrode and the M electrode or the Y electrode and the M electrode at the beginning of the sustain discharge, sufficient discharge is performed even in a state where there are few charged particles, and in the normal state, the X electrode Since the discharge is performed by the long gap discharge between the and Y electrodes, stable discharge can be performed.

As described above, the present invention is not limited to the specific preferred embodiments described above, and any person having ordinary skill in the art to which the present invention pertains without departing from the gist of the present invention claimed in the claims. Various modifications are possible, of course, and such changes are within the scope of the claims.

According to the PDP according to the present invention, by forming a barrier rib structure in which two address electrodes are allocated to one pixel, the capacitance between address electrodes can be reduced to reduce power consumption, and the sustain discharge voltage can be reduced by providing an intermediate electrode between display electrodes. There is an effect that can perform a low and stable discharge.

In addition, according to the present invention, it is advantageous for high resolution by reducing the number of address electrodes in the same area, and an opaque bus electrode which blocks light emitted from the phosphor by addressing the intermediate electrode and the address electrode is located on the partition wall. The luminous luminance can be improved.

In addition, according to the present invention, the intermediate electrode is covered with an electron emitting material layer or a dielectric layer having a relatively high dielectric constant, thereby increasing the amount of charged particles or increasing the amount of wall charge, thereby reducing the discharge voltage in spite of the high resolution. .

Claims (12)

A front substrate and a rear substrate facing each other; A partition wall formed between the front substrate and the rear substrate and partitioning the discharge cells such that three adjacent discharge cells that emit visible light of different colors form one pixel; First and second display electrodes formed between the front substrate and the rear substrate and formed of metal in parallel with each other in the partition walls; Two address electrodes formed to pass through each of the one pixel; Intermediate electrodes formed between the first display electrode and the second display electrode so that one discharge cell passes through each of the discharge cells; And And an electron-emitting material layer coated on the intermediate electrode. The method of claim 1, And one address electrode is commonly allocated to two selected discharge cells among the three discharge cells constituting the one pixel, and another address electrode is allocated to the other discharge cell. delete delete The method of claim 1, The intermediate electrode is formed on a rear surface of the front substrate, and the electron emission material layer is formed between upper dielectric layers when viewed in a direction perpendicular to the front substrate to form an interface with the upper dielectric layer. . The method according to claim 1 or 5, The electron emission material layer is plasma display panel, characterized in that made of carbon nanotubes (CNT) or carbonate. A front substrate and a rear substrate facing each other; A partition wall formed between the front substrate and the rear substrate and partitioning the discharge cells so that three discharge cells emitting different colors of visible light are adjacent to each other to form one pixel; First and second display electrodes formed between the front substrate and the rear substrate and formed of metal in parallel with each other in the partition walls; Two address electrodes each allocated to one pixel including discharge cells separated by the barrier ribs; An intermediate electrode disposed between the first display electrode and the second display electrode to correspond to each of the discharge cells; And An upper dielectric layer is formed between the intermediate electrode and the back substrate, and the upper dielectric layer includes a first upper dielectric layer in contact with the intermediate electrode and a second upper dielectric layer formed on a side of the first upper dielectric layer. And an upper dielectric layer and the second upper dielectric layer have different dielectric constants from each other. The method of claim 7, wherein And one address electrode is commonly allocated to two selected discharge cells among the three discharge cells constituting the one pixel, and another address electrode is allocated to the other discharge cell. delete delete The method of claim 7, wherein And the first upper dielectric layer is formed to have a higher dielectric constant than the second upper dielectric layer. The method according to claim 7 or 11, wherein And the dielectric constant of the first upper dielectric layer is at least 15, and the dielectric constant of the second upper dielectric layer is 10 to 14.

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