KR20070002510A - Method of forming field oxide layer in semiconductor device - Google Patents

Method of forming field oxide layer in semiconductor device Download PDF

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KR20070002510A
KR20070002510A KR1020050058078A KR20050058078A KR20070002510A KR 20070002510 A KR20070002510 A KR 20070002510A KR 1020050058078 A KR1020050058078 A KR 1020050058078A KR 20050058078 A KR20050058078 A KR 20050058078A KR 20070002510 A KR20070002510 A KR 20070002510A
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film
etching process
forming
hdp oxide
oxide layer
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KR101087727B1 (en
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김정근
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

A method for forming an isolation layer in a semiconductor device is provided to prevent the damage of a substrate due to plasma or fluorine gas by using an insulating layer for damage protection. A trench is formed in a semiconductor substrate(10). A first HDP(High Density Plasma) oxide layer(16) is partially formed in the trench. A damage protection insulating layer(18) is then formed on the resultant structure. By performing etch-back, the overhang of the first HDP oxide layer is removed. The trench is then entirely filled with a second HDP oxide layer(20).

Description

반도체 소자의 소자분리막 형성방법{Method of forming field oxide layer in semiconductor device}Method for forming a device isolation layer of a semiconductor device {Method of forming field oxide layer in semiconductor device}

도 1 내지 도 5는 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도들이다. 1 to 5 are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Explanation of symbols for main parts of drawings *

10: 반도체 기판 12: 패드 질화막10 semiconductor substrate 12 pad nitride film

18: 손상방지용 절연막 16, 20: HDP 산화막 18: damage preventing insulating film 16, 20: HDP oxide film

본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 반도체 소자의 소자분리막 형성방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device.

최근 반도체 소자의 고집적화, 고밀도화에 따라 소자분리막의 갭필 특성이 향상될 수 있도록 하는 기술들이 중요시되고 있다. Recently, technologies for improving the gapfill characteristics of device isolation layers have become important due to high integration and high density of semiconductor devices.

일반적으로 반도체 소자의 소자분리막 형성방법에 있어서, 형성된 트렌치내부에 제1 절연막을 형성한 후 식각공정을 수행하고 제2 절연막을 형성하여 트렌치 내부를 갭필하게 된다. 이는 절연막증착-식각-절연막증착의 공정을 계속적으로 반복 수행할 수 있다. In general, in the method of forming a device isolation layer of a semiconductor device, a first insulating film is formed in the formed trench, followed by an etching process, and a second insulating film is formed to fill a gap inside the trench. This can continuously repeat the process of insulating film deposition-etching-insulation film deposition.

그러나 상기 식각공정은 건식식각공정이 사용될 수도 있고, 습식 식각공정이 사용될 수도 있는 데, 상기 식각공정이 습식으로 진행되면, 습식 식각공정시 발생되는 플로오린(F)가스는 반도체 기판에 손상을 가하게 되고, 상기 식각공정이 건식으로 진행되면, 건식 식각 공정시 사용되는 플라즈마는 반도체 기판에 손상을 가하게 된다. However, the etching process may be a dry etching process or a wet etching process. When the etching process is wet, the fluoroine (F) gas generated during the wet etching process may damage the semiconductor substrate. When the etching process is performed in a dry manner, the plasma used in the dry etching process may damage the semiconductor substrate.

따라서 손상된 반도체 기판으로 인해 소자의 특성 열화를 야기시키는 문제점이 있다. Therefore, there is a problem that causes the deterioration of the characteristics of the device due to the damaged semiconductor substrate.

상술한 문제점을 해결하기 위한 본 발명의 목적은 절연막증착-식각-절연막증착의 공정을 통해 트렌치를 매립하여 소자분리막 형성공정을 수행할 때, 반도체 기판 손상을 방지할 수 있도록 하는 반도체 소자의 소자분리막 형성방법을 제공함에 있다. SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to prevent damage to a semiconductor substrate when a device isolation film forming process is performed by filling a trench through a process of insulating film deposition-etching-insulation film deposition. It is to provide a formation method.

상술한 목적을 달성하기 위한 본 발명의 사상은 반도체 기판에 트렌치를 형 성하는 단계, 상기 트렌치에 제1 HDP 산화막을 형성하는 단계, 상기 제1 HDP 산화막이 형성된 결과물 전면에 손상방지용 절연막을 형성하는 단계, 상기 손상방지용 절연막이 형성된 결과물 전면에 식각공정을 수행하여 상기 제1 HDP 산화막의 오버행을 제거하는 단계, 상기 식각공정이 완료된 결과물 전면에 제2 HDP 산화막을 형성하는 단계 및 상기 제2 HDP 산화막의 형성 후 상기 반도체 기판이 노출될 때까지 평탄화 공정을 수행하여 상기 트렌치 내부에만 상기 제1 HDP 산화막 및 제2 HDP 산화막이 매립되도록 하여 소자분리막의 형성을 완료하는 단계를 포함한다.The idea of the present invention for achieving the above object is to form a trench in a semiconductor substrate, to form a first HDP oxide film in the trench, to form a damage prevention insulating film on the entire surface of the resultant formed first HDP oxide film Step, removing the overhang of the first HDP oxide film by performing an etching process on the entire surface of the resultant insulating film is formed, forming a second HDP oxide film on the entire surface of the resultant etching process and the second HDP oxide film And forming the device isolation layer by performing a planarization process until the semiconductor substrate is exposed after the formation of the semiconductor layer to fill the first HDP oxide layer and the second HDP oxide layer only in the trench.

상기 손상방지용 절연막은 PE 질화막, LP 질화막을 사용하거나, PECVD공정을 통해 형성되는 PE-TEOS막, SiH4을 사용한 USG막, O3를 사용한 TEOS막을 사용하거나, 퍼니스CVD 공정을 통해 형성되는 LP-TEOS막, SiH4를 이용한 HTO막, DCS를 이용한 HTO막으로 사용하여 형성한다.The damage prevention insulating film is a PE nitride film, an LP nitride film, a PE-TEOS film formed through a PECVD process, a USG film using SiH4, a TEOS film using O3, or an LP-TEOS film formed through a furnace CVD process. And HTO film using SiH4 and HTO film using DCS.

상기 손상방지용 절연막을 사용할 때 상기 식각공정은 습식식각공정으로 수행된다.When using the damage prevention insulating film, the etching process is performed by a wet etching process.

상기 손상방지용 절연막은 HDP산화막을 사용하여 형성한다.The damage preventing insulating film is formed using an HDP oxide film.

상기 손상방지용 절연막을 사용할 때 상기 식각공정은 건식식각공정으로 수행된다.When using the damage prevention insulating film, the etching process is performed by a dry etching process.

상기 건식식각공정은 2000~ 3000W의 고주파바이어스전압을 가진 공정조건에서 수행된다.The dry etching process is performed under process conditions with a high frequency bias voltage of 2000 ~ 3000W.

상기 HDP 산화막은 200~ 400W의 고주파바이어스전압, 3000~ 5000W의 저주파바이어스전압, 500~ 1000sccm의 He 흐름분위기, 30~ 60sccm 의 O2 흐름분위기, 40~ 70sccm 의 SuH4흐름분위기를 가진 공정조건에서 수행된다.The HDP oxide film is performed under process conditions with a high frequency bias voltage of 200 to 400 W, a low frequency bias voltage of 3000 to 5000 W, a He flow atmosphere of 500 to 1000 sccm, an O2 flow atmosphere of 30 to 60 sccm, and a SuH4 flow atmosphere of 40 to 70 sccm. .

이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있지만 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해 제공되어지는 것이다. 또한 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 또는 접촉하고 있다 라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, but the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.

도 1 내지 도 5는 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도들이다. 1 to 5 are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.

도 1을 참조하면, 셀영역(A) 및 주변회로영역(B)이 구분 정의된 반도체 기판(10) 상에 패드 질화막(12) 및 패드 산화막(14)을 순차적으로 형성한다. 상기 패드 산화막(14)의 소정 영역 상에 소자분리 영역을 정의하는 포토레지스트 패턴(미도시)을 형성하고, 상기 포토레지스트 패턴(미도시)을 식각 마스크로 상기 패드 산화막(14), 패드 질화막(12) 및 반도체 기판(10)의 소정 깊이에 식각공정을 수행하여, 트렌치(T)를 정의한다. 상기 형성된 트렌치(T)의 측벽에 산화공정을 수행하여 측벽 산화막(15)을 형성한다. Referring to FIG. 1, a pad nitride film 12 and a pad oxide film 14 are sequentially formed on a semiconductor substrate 10 in which a cell region A and a peripheral circuit region B are defined. A photoresist pattern (not shown) defining a device isolation region is formed on a predetermined region of the pad oxide layer 14, and the pad oxide layer 14 and the pad nitride layer are formed using the photoresist pattern (not shown) as an etching mask. 12) and the trench T is defined by performing an etching process at a predetermined depth of the semiconductor substrate 10. An oxidation process is performed on sidewalls of the formed trenches T to form sidewall oxide layers 15.

상기 셀영역(A)에 형성되는 트렌치의 깊이와 폭은 주변회로영역(B)에 형성되는 트렌치의 깊이와 폭보다 좁고 얕다. The depth and width of the trench formed in the cell region A are narrower and shallower than the depth and width of the trench formed in the peripheral circuit region B. FIG.

상기 셀영역(A)의 트렌치는 1700~ 1900Å 정도의 깊이를 갖고, 상기 주변회로영역(B)의 트렌치는 2500~ 3000Å 정도의 깊이를 갖는다.The trench of the cell region A has a depth of about 1700 to 1900 ,, and the trench of the peripheral circuit region B has a depth of about 2500 to 3,000 Å.

도 2를 참조하면, 상기 측벽 산화막(15)이 구비된 결과물 전면에 제1 HDP(high density plasma)산화막(16)을 형성한다. Referring to FIG. 2, a first high density plasma (HDP) oxide layer 16 is formed on the entire surface of the resultant sidewall oxide layer 15.

상기 제1 HDP 산화막(16)은 10~ 100sccm 정도의 SiH4가스, 10~ 100sccm 정도의 O2가스, 100~ 1000sccm 정도의 He 가스, 50~ 1000sccm 정도의 H2가스, 1000~ 10000W 정도의 LF 파워 및 500~ 5000W 정도의 HF 파워를 가지는 공정조건에서 수행된다. The first HDP oxide layer 16 may include SiH 4 gas of about 10 to 100 sccm, O 2 gas of about 10 to 100 sccm, He gas of about 100 to 1000 sccm, H 2 gas of about 50 to 1000 sccm, LF power of about 1000 to 10000 W, and the like. It is performed under process conditions with HF power of 500 ~ 5000W.

상기 셀영역(A)에 형성되는 트렌치의 깊이와 폭보다 주변회로영역(B)에 형성되는 트렌치의 깊이와 폭은 깊고 넓기 때문에, 주변회로영역의 트렌치에는 상기 제1 HDP산화막이 완전히 갭필되지 않는다. 따라서 식각공정을 수행한 후, 갭필이 될 수 있는 막질의 증착공정이 한 번 더 수행된다. Since the depth and width of the trench formed in the peripheral circuit region B are deeper and wider than the depth and width of the trench formed in the cell region A, the trench of the peripheral circuit region does not completely gap fill the first HDP oxide film. . Therefore, after performing the etching process, the deposition process of the film quality, which may be a gap fill, is performed once more.

이어서, 상기 제1 HDP 산화막(18)을 형성한 후, 상기 제1 HDP 산화막(18)의 경계를 따라 손상방지용 절연막(18)을 형성한다. Subsequently, after the first HDP oxide film 18 is formed, a damage preventing insulating film 18 is formed along the boundary of the first HDP oxide film 18.

상기 손상방지용 절연막(18)은 HDP산화막을 사용하거나, PE 질화막, LP 질화막을 사용하거나, PECVD공정을 통해 형성되는 PE-TEOS막, SiH4을 사용한 USG막, O3를 사용한 TEOS막을 사용하거나, 퍼니스CVD 공정을 통해 형성되는 LP-TEOS막, SiH4 를 이용한 HTO막, DCS를 이용한 HTO막을 사용할 수 있다. The damage prevention insulating film 18 is a HDP oxide film, PE nitride film, LP nitride film, PE-TEOS film formed by PECVD process, USG film using SiH4, TEOS film using O3, furnace CVD LP-TEOS film formed through the process, HTO film using SiH4, HTO film using DCS can be used.

상기 제1 HDP 산화막(18)의 증착 공정 후 오버행(overhang)이 발생하여 트렌치의 입구를 막아 형성되는 보이드가 방지되도록, 버티컬한 측벽을 갖도록 하기 위해서 식각공정이 수행되는 데, 상기 식각공정이 습식으로 진행되면, 습식 식각공정시 발생되는 플로오린(F)가스에 따른 반도체 기판의 손상이 발생하게 되고, 상기 식각공정이 건식으로 진행되면, 건식 식각공정시 사용되는 플라즈마에 따른 반도체 기판의 손상이 발생하게 된다. An etching process is performed to have a vertical sidewall so that an overhang occurs after the deposition process of the first HDP oxide layer 18 to prevent a void formed by blocking an inlet of the trench, and the etching process is wet. In this case, damage to the semiconductor substrate due to the fluoroine (F) gas generated during the wet etching process occurs, and when the etching process proceeds to dry, damage to the semiconductor substrate due to the plasma used during the dry etching process occurs. Will occur.

따라서 상기 손상방지용 절연막(18)을 형성함으로써, 후속으로 진행되는 식각 공정시 발생될 수 있는 플라즈마에 따른 반도체 기판의 손상 또는 플로오린 가스에 따른 반도체 기판의 손상이 방지될 수 있다. Accordingly, by forming the damage preventing insulating layer 18, damage to the semiconductor substrate due to plasma or damage to the semiconductor substrate due to fluorine gas, which may occur in a subsequent etching process, may be prevented.

도 3을 참조하면, 상기 손상방지용 절연막(18)이 형성된 결과물 상에 제1 HDP 산화막(18)의 오버행을 제거하기 위해 식각공정을 수행하는 데, 상기 식각공정은 습식식각공정 또는 건식식각공정으로 사용될 수 있다. Referring to FIG. 3, an etching process is performed to remove an overhang of the first HDP oxide layer 18 on a resultant of the damage prevention insulating film 18. The etching process may be a wet etching process or a dry etching process. Can be used.

상기 손상방지용 절연막(18)을 형성함으로써, 후속으로 진행되는 식각 공정즉, 건식식각 공정시 사용되는 플라즈마에 따른 손상을 방지하거나 또는 습식식각 공정시 발생되는 플로오린 가스에 따른 손상이 방지될 수 있다. By forming the damage preventing insulating layer 18, damage due to a plasma used in a subsequent etching process, that is, a dry etching process, or damage due to a fluorine gas generated during a wet etching process may be prevented. .

상기 습식식각공정을 사용할 때는 PE 질화막, LP 질화막을 사용하거나, PECVD공정을 통해 형성되는 PE-TEOS막, SiH4을 사용한 USG막, O3를 사용한 TEOS막을 사용하거나, 퍼니스CVD 공정을 통해 형성되는 LP-TEOS막, SiH4를 이용한 HTO막, DCS를 이용한 HTO막으로 사용하여 손상방지용 절연막을 형성한다. When the wet etching process is used, a PE nitride film, an LP nitride film is used, a PE-TEOS film formed through a PECVD process, a USG film using SiH4, a TEOS film using O3, or an LP- formed through a furnace CVD process. A damage preventing insulating film is formed by using the TEOS film, the HTO film using SiH4, and the HTO film using DCS.

상기 건식식각공정을 사용할 때는 HDP산화막을 사용하여 손상방지용 절연막을 형성한다. When using the dry etching process, an insulating film for preventing damage is formed by using an HDP oxide film.

상기 건식식각공정은 2000~ 3000W 정도의 고주파바이어스전압을 가진 공정조건에서 수행하고, 상기 손상방지용 절연막인 HDP 산화막은 200~ 400W 정도의 고주파바이어스전압, 3000~ 5000W정도의 저주파바이어스전압, 500~ 1000sccm 정도의 He 흐름분위기, 30~ 60sccm 정도의 O2 흐름분위기, 40~ 70sccm 정도의 SuH4흐름분위기를 가진 공정조건에서 수행한다. The dry etching process is performed under process conditions with a high frequency bias voltage of about 2000 to 3000W, and the HDP oxide film, which is an insulating film for preventing damage, has a high frequency bias voltage of about 200 to 400W, a low frequency bias voltage of about 3000 to 5000W, and 500 to 1000sccm. It is carried out in the process conditions with He flow atmosphere of about 30 ~ 60sccm, O2 flow atmosphere of about 30 ~ 60sccm and SuH4 flow atmosphere of about 40 ~ 70sccm.

도 4를 참조하면, 상기 식각공정이 완료되어 오버행이 제거된 제1 HDP 산화막(16) 상에 제2 HDP 산화막(20)을 형성하여, 트렌치 내부를 완전히 갭필하도록 한다. Referring to FIG. 4, the etching process is completed to form a second HDP oxide layer 20 on the first HDP oxide layer 16 from which the overhang is removed, thereby completely filling the inside of the trench.

상기 제2 HDP 산화막(20)은 상기 제1 HDP 산화막의 형성시의 공정조건과 동일한 공정조건에서 수행된다. The second HDP oxide film 20 is performed under the same process conditions as those for forming the first HDP oxide film.

도 5를 참조하면, 상기 제2 HDP 산화막(20)이 형성된 결과물에 상기 반도체 기판(10)이 노출될 때까지 평탄화 공정을 수행하여 상기 트렌치 내부에만 상기 제1 HDP 산화막(16) 및 제2 HDP 산화막(20)이 매립되도록 하여 소자분리막의 형성을 완료한다. Referring to FIG. 5, a planarization process is performed until the semiconductor substrate 10 is exposed to a resultant product on which the second HDP oxide layer 20 is formed, so that the first HDP oxide layer 16 and the second HDP layer only in the trench. The oxide film 20 is buried to complete the formation of the device isolation film.

본 발명에 의하면, 제1 HDP 산화막을 형성한 후, 식각공정 수행 전에 손상방지용 절연막을 형성함으로써, 후속으로 진행되는 식각 공정시 발생될 수 있는 플라즈마에 따른 반도체 기판의 손상 또는 플로오린 가스에 따른 반도체 기판의 손상이 방지될 수 있다. According to the present invention, after forming the first HDP oxide film, and then forming a damage preventing insulating film before performing the etching process, the semiconductor according to the damage or the semiconductor substrate due to the plasma gas that can be generated during the subsequent etching process Damage to the substrate can be prevented.

이상에서 살펴본 바와 같이 본 발명에 의하면, 제1 HDP 산화막을 형성한 후, 식각공정 수행전에 손상방지용 절연막을 형성함으로써, 후속으로 진행되는 식각 공정시 발생될 수 있는 플라즈마에 따른 반도체 기판의 손상 또는 플로오린 가스에 따른 반도체 기판의 손상이 방지될 수 있는 효과가 있다. As described above, according to the present invention, after forming the first HDP oxide layer and then forming an insulating film for damage prevention before performing the etching process, damage or flow of the semiconductor substrate due to the plasma which may be generated during the subsequent etching process is performed. There is an effect that damage to the semiconductor substrate due to the stray gas can be prevented.

본 발명은 구체적인 실시 예에 대해서만 상세히 설명하였지만 본 발명의 기술적 사상의 범위 내에서 변형이나 변경할 수 있음은 본 발명이 속하는 분야의 당업자에게는 명백한 것이며, 그러한 변형이나 변경은 본 발명의 특허청구범위에 속한다 할 것이다.Although the present invention has been described in detail only with respect to specific embodiments, it is apparent to those skilled in the art that modifications or changes can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.

Claims (7)

반도체 기판에 트렌치를 형성하는 단계;Forming a trench in the semiconductor substrate; 상기 트렌치에 제1 HDP 산화막을 형성하는 단계;Forming a first HDP oxide layer in the trench; 상기 제1 HDP 산화막이 형성된 결과물 전면에 손상방지용 절연막을 형성하는 단계;Forming an damage preventing insulating film on the entire surface of the resultant product on which the first HDP oxide film is formed; 상기 손상방지용 절연막이 형성된 결과물 전면에 식각공정을 수행하여 상기 제1 HDP 산화막의 오버행을 제거하는 단계; Removing an overhang of the first HDP oxide layer by performing an etching process on the entire surface of the resultant layer on which the damage preventing insulating layer is formed; 상기 식각공정이 완료된 결과물 전면에 제2 HDP 산화막을 형성하여 트렌치를 매립하는 단계; 및Filling a trench by forming a second HDP oxide layer on the entire surface of the resultant product of which the etching process is completed; And 상기 제2 HDP 산화막의 형성 후 상기 반도체 기판이 노출될 때까지 평탄화 공정을 수행하여 상기 트렌치 내부에만 상기 제1 HDP 산화막 및 제2 HDP 산화막이 매립되도록 하여 소자분리막의 형성을 완료하는 단계를 포함하는 반도체 소자의 소자분리막 형성방법. Performing a planarization process until the semiconductor substrate is exposed after the formation of the second HDP oxide layer so that the first HDP oxide layer and the second HDP oxide layer are embedded only in the trench, thereby completing forming the device isolation layer. A device isolation film forming method of a semiconductor device. 제1 항에 있어서, 상기 손상방지용 절연막은 The method of claim 1, wherein the damage prevention insulating film PE 질화막, LP 질화막을 사용하거나, PECVD공정을 통해 형성되는 PE-TEOS막, SiH4을 사용한 USG막, O3를 사용한 TEOS막을 사용하거나, 퍼니스CVD 공정을 통해 형성되는 LP-TEOS막, SiH4를 이용한 HTO막, DCS를 이용한 HTO막으로 사용하여 형성 하는 반도체 소자의 소자분리막 형성방법. PE nitride film, LP nitride film, PE-TEOS film formed by PECVD process, USG film using SiH4, TEOS film using O3, LP-TEOS film formed by furnace CVD process, HTO using SiH4 A method of forming a device isolation film for a semiconductor device formed by using a film and an HTO film using DCS. 제1 항 또는 제2 항에 있어서, 상기 손상방지용 절연막을 사용할 때 상기 식각공정은 The method of claim 1, wherein the etching process is performed when the damage preventing insulating film is used. 습식식각공정으로 수행되는 반도체 소자의 소자분리막 형성방법. A device isolation film forming method of a semiconductor device performed by a wet etching process. 제1 항에 있어서, 상기 손상방지용 절연막은 The method of claim 1, wherein the damage prevention insulating film HDP산화막을 사용하여 형성하는 반도체 소자의 소자분리막 형성방법. A device isolation film formation method for a semiconductor device formed using an HDP oxide film. 제1 항 또는 제4 항에 있어서, 상기 손상방지용 절연막을 사용할 때 상기 식각공정은 The etching process according to claim 1 or 4, wherein the etching process is performed when the damage preventing insulating film is used. 건식식각공정으로 수행되는 반도체 소자의 소자분리막 형성방법. A device isolation film forming method of a semiconductor device performed by a dry etching process. 제5 항에 있어서, 상기 건식식각공정은 The method of claim 5, wherein the dry etching process 2000~ 3000W의 고주파바이어스전압을 가진 공정조건에서 수행하는 반도체 소자의 소자분리막 형성방법. A method of forming a device isolation film for a semiconductor device, which is performed under process conditions having a high frequency bias voltage of 2000 to 3000 W. 제4 항에 있어서, 상기 HDP 산화막은 The method of claim 4, wherein the HDP oxide film 200~ 400W의 고주파바이어스전압, 3000~ 5000W의 저주파바이어스전압, 500~ 1000sccm의 He 흐름분위기, 30~ 60sccm 의 O2 흐름분위기, 40~ 70sccm 의 SuH4흐름분위기를 가진 공정조건에서 수행되는 반도체 소자의 소자분리막 형성방법. Semiconductor device device with high frequency bias voltage of 200 ~ 400W, low frequency bias voltage of 3000 ~ 5000W, He flow atmosphere of 500 ~ 1000sccm, O2 flow atmosphere of 30 ~ 60sccm, SuH4 flow atmosphere of 40 ~ 70sccm Separator Formation Method.
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Publication number Priority date Publication date Assignee Title
KR100868656B1 (en) * 2007-06-26 2008-11-12 주식회사 동부하이텍 Method for fabricating semiconductor device
KR100929641B1 (en) * 2008-02-20 2009-12-03 주식회사 하이닉스반도체 Manufacturing method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100868656B1 (en) * 2007-06-26 2008-11-12 주식회사 동부하이텍 Method for fabricating semiconductor device
KR100929641B1 (en) * 2008-02-20 2009-12-03 주식회사 하이닉스반도체 Manufacturing method of semiconductor device

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