KR20070000151A - Method of manufacturing a nand flash memory device - Google Patents
Method of manufacturing a nand flash memory device Download PDFInfo
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- KR20070000151A KR20070000151A KR1020050055667A KR20050055667A KR20070000151A KR 20070000151 A KR20070000151 A KR 20070000151A KR 1020050055667 A KR1020050055667 A KR 1020050055667A KR 20050055667 A KR20050055667 A KR 20050055667A KR 20070000151 A KR20070000151 A KR 20070000151A
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- South Korea
- Prior art keywords
- polysilicon layer
- etching
- flash memory
- film
- nand flash
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 229920005591 polysilicon Polymers 0.000 claims abstract description 46
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 2
- 238000003860 storage Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
본 발명은 낸드 플래쉬 메모리 소자의 제조방법에 관한 것으로, 특히, 플로팅 게이트 상부 에지 부분을 둥글게 형성하여 전하 손실을 제거하기 위한 낸드 플래쉬 메모리 소자의 제조방법에 관한 것이다. The present invention relates to a method of manufacturing a NAND flash memory device, and more particularly, to a method of manufacturing a NAND flash memory device for removing charge loss by rounding an upper edge portion of a floating gate.
낸드 플래쉬 메모리 소자의 일반적인 게이트 형성방법 중 플로팅 게이트 상부 에지 부분의 프로파일(profile) 형성방법에 관해 설명하면 다음과 같다.A method of forming a profile of an upper edge portion of a floating gate in the general gate forming method of the NAND flash memory device will be described below.
도 1a를 참조하면, 반도체 기판(100) 내에 액티브 영역(a) 및 필드 영역(b)을 확정하기 위해 소자분리막(102)을 형성한다. 전체 구조 상부에 제1 폴리실리콘막(104)을 형성한 후, 제1 폴리실리콘막(104) 상부에 감광막 패턴(미도시)을 형성한다. 감광막 패턴을 마스크로 이용하여 제1 폴리실리콘막(104)을 식각하여 제1폴리실리콘막 (104)으로 이루어진 플로팅 게이트를 형성한다. 전체 구조 상부에 유전체막(미도시)을 증착한 후, 유전체막 상부에 제2 폴리실리콘막(미도시) 및 텅스텐 실리사이드막(미도시)을 형성한다.Referring to FIG. 1A, an isolation layer 102 is formed in the semiconductor substrate 100 to determine an active region a and a field region b. After the first polysilicon film 104 is formed on the entire structure, a photoresist pattern (not shown) is formed on the first polysilicon film 104. The first polysilicon film 104 is etched using the photosensitive film pattern as a mask to form a floating gate formed of the first polysilicon film 104. After depositing a dielectric film (not shown) on the entire structure, a second polysilicon film (not shown) and a tungsten silicide film (not shown) are formed on the dielectric film.
그러나, 상기와 같은 방법으로 플로팅 게이트를 형성하면, 플로팅 게이트 식각시 상부 에지 부분이 뾰족하게(A) 형성되어 이 뾰족한 부분(A)으로 전계가 집중되어 진다. 이로 인해, 전하 손실이 발생하게 된다. However, when the floating gate is formed in the above manner, the upper edge portion is sharply formed (A) during the etching of the floating gate, so that the electric field is concentrated on the sharp portion (A). This causes charge loss.
또한, 유전체막 증착시 플로팅 게이트 상부의 뾰족한 에지 부분은 제거 되지 않기 때문에 이 뾰족한 형태의 프로파일은 소자의 보존 특성을 악화시킨다. In addition, since the sharp edge portion on the floating gate is not removed when the dielectric film is deposited, this sharp profile worsens the storage characteristics of the device.
상술한 문제점을 해결하기 위해 안출된 본 발명의 목적은 플로팅 게이트 상부의 뾰족한 에지 부분을 둥글게 형성하여 전하 손실을 제거하고, 소자의 보존 특성 악화를 방지하기 위한 낸드 플래쉬 메모리 소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention devised to solve the above problems is to provide a method of manufacturing a NAND flash memory device for forming a sharp edge portion of an upper portion of a floating gate to eliminate charge loss and to prevent deterioration of storage characteristics of the device. have.
본 발명의 실시예에 따른 낸드 플래쉬 메모리 소자의 제조방법은, 소자분리막이 형성된 반도체 기판 상부에 제1 폴리실리콘막 및 에지 부분이 둥근 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 마스크로 상기 제1 폴리실리콘막을 1차로 식각하는 단계와, 상기 제1 폴리실리콘막을 2차 식각시 상기 감광막 패턴의 식각 선택비를 상기 제1 폴리실리콘막의 1차 식각시 보다 낮게하여 상기 제1 폴리실리콘막 에지 부분을 둥글게 형성하는 단계를 포함하는 낸드 플래쉬 메모리 소자의 제조방법을 제공한다.A method of manufacturing a NAND flash memory device according to an exemplary embodiment of the present invention may include forming a photoresist pattern having a rounded first polysilicon layer and an edge portion on an upper surface of a semiconductor substrate on which an isolation layer is formed, and using the photoresist pattern as a mask First etching the polysilicon layer and lowering the etch selectivity of the photoresist pattern during the second etching of the first polysilicon layer to be lower than that of the first polysilicon layer during the first etching of the first polysilicon layer It provides a method of manufacturing a NAND flash memory device comprising the step of forming a round.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 낸드 플래쉬 메모리 소자의 제조방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.2A through 2D are cross-sectional views sequentially illustrating devices for manufacturing a NAND flash memory device according to an exemplary embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(200) 내에 액티브 영역(a) 및 필드 영역(b)을 확정하기 위해 소자분리막(202)을 형성한다. 전체 구조 상부에 제1 폴리실리콘막(204) 및 감광막을 형성한 후, 사진 및 현상 공정을 실시하여 감광막 패턴(206)을 형성한다. 이때, 제1 폴리실리콘막(204)은 1500Å 내지 2500Å의 두께로 형성한다. 감광막 패턴(206)의 상부 에지 부분이 둥글게(B) 형성되도록 열처리 공정을 실시한다. 이때, 열처리 공정은 50℃ 내지 200℃의 온도로 1시간 내지 5시간 동안 실시한다.Referring to FIG. 2A, an isolation layer 202 is formed in the semiconductor substrate 200 to determine the active region a and the field region b. After forming the first polysilicon film 204 and the photosensitive film on the entire structure, the photosensitive film pattern 206 is formed by performing a photographic and developing process. At this time, the first polysilicon film 204 is formed to a thickness of 1500 kPa to 2500 kPa. The heat treatment process is performed such that the upper edge portion of the photosensitive film pattern 206 is rounded (B). At this time, the heat treatment process is carried out for 1 hour to 5 hours at a temperature of 50 ℃ to 200 ℃.
도 2b를 참조하면, 감광막 패턴(206)을 마스크로 이용하여 제1 폴리실리콘막(204)을 2단계로 식각하여 제1 폴리실리콘막(204) 상부 에지 부분을 둥글게(C) 형성한다. 이때, 제1 폴리실리콘막(204)은 ICP(Inductively Coupled Plasma) 타입, CCP(capacitively coupled plasma) 타입 또는 ECR(Electron Cyclotron Resonance) 타입의 식각 장비를 사용하여 식각한다. Referring to FIG. 2B, the first polysilicon layer 204 is etched in two steps by using the photoresist pattern 206 as a mask to round the upper edge portion (C) of the first polysilicon layer 204. In this case, the first polysilicon layer 204 is etched using an inductively coupled plasma (ICP) type, a capacitively coupled plasma (CCP) type, or an electron cyclone resonance (ECR) type etching equipment.
먼저, 2단계로 식각되는 제1 폴리실리콘막(204)을 1차로 식각한다. 이때, 감광막 패턴(206)의 식각 선택비를 5:1로 하여 식각한다. 그런 다음, 감광막 패턴(206)의 식각 선택비를 2:1 이하로 낮게하여 2차로 식각한다. 이때, 제1 폴리실리콘막(204)은 CL2의 단일 가스를 사용하거나, CL2에 O2, N2, HBR 또는 CF4 가스를 적합하게 혼합한 혼합 가스를 사용하여 식각한다. 또는, 2차로 등방성 식각 장비를 이용하여 감광막 패턴(206)을 유지하면서 제1 폴리실리콘막(204) 상부 에지 부분을 둥글게(C) 식각한다. 이렇게 제1 폴리실리콘막(204)을 2단계로 식각하면, 끝부분이 삼각형 모양을 가지는 감광막 패턴(206)이 형성된다. 식각된 제1 폴리실리콘막(204)의 상부 에지 부분은 100Å 내지 200Å의 두께 정도 식각되고, 20도 내지 50도의 각도를 가진다.First, the first polysilicon film 204 to be etched in two steps is primarily etched. At this time, the etching selectivity of the photoresist pattern 206 is set to 5: 1. Thereafter, the etch selectivity of the photoresist pattern 206 is lowered to 2: 1 or less to etch secondarily. In this case, the first polysilicon film 204 is etched by using a single gas or CL 2, using O 2, N 2, HBR or gas mixture suitable for mixing the CF 4 gas to CL 2. Alternatively, the upper edge portion of the first polysilicon layer 204 is rounded (C) while maintaining the photoresist pattern 206 using a second isotropic etching device. When the first polysilicon film 204 is etched in two steps as described above, a photosensitive film pattern 206 having a triangular shape at an end thereof is formed. The upper edge portion of the etched first polysilicon film 204 is etched to a thickness of 100 kPa to 200 kPa, and has an angle of 20 to 50 degrees.
도 2c를 참조하면, 감광막 패턴(206)을 제거하여 제1 폴리실리콘막(204) 상부 에지 부분이 둥글게(D) 형성된 플로팅 게이트를 형성한다. Referring to FIG. 2C, the photoresist pattern 206 is removed to form a floating gate in which the upper edge portion of the first polysilicon layer 204 is rounded (D).
도 2d를 참조하면, 플로팅 게이트 상부에 유전체막(208)을 형성한 후, 유전체막(208) 상부에 제2 폴리실리콘막(210), 텅스텐 실리사이드막(212) 및 하드 마스크막(214)을 형성한다.Referring to FIG. 2D, after the dielectric film 208 is formed on the floating gate, the second polysilicon film 210, the tungsten silicide film 212, and the hard mask film 214 are formed on the dielectric film 208. Form.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지하여야 한다. 또한, 본 발명의 기술 분야에서 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같이 본 발명에 의하면, 제1 폴리실리콘막 상부의 뾰족한 에지 부분을 둥글게 형성함으로써, 전하 손실을 방지할 수 있다. 이로 인해, 소자의 보존 특성 악화를 방지할 수 있다.As described above, according to the present invention, charge loss can be prevented by forming rounded edge portions of the upper portion of the first polysilicon film. For this reason, deterioration of the storage characteristic of an element can be prevented.
도 1은 종래 기술에 따른 낸드 플래쉬 메모리 소자의 제조방법을 설명하기 위해 도시한 단면도이다.1 is a cross-sectional view illustrating a method of manufacturing a NAND flash memory device according to the prior art.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 낸드 플래쉬 메모리 소자의 제조방법을 설명하기 위해 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to an exemplary embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
200 : 반도체 기판 202 : 소자분리막200: semiconductor substrate 202: device isolation film
204 : 제1 폴리실리콘 206 : 감광막 패턴204: first polysilicon 206: photosensitive film pattern
208 : 유전체막 210 : 제2 폴리실리콘막 208: dielectric film 210: second polysilicon film
212 : 텅스텐 실리사이드막 214 : 하드 마스크막212: tungsten silicide film 214: hard mask film
a : 액티브 영역 b : 필드 영역a: active area b: field area
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