KR20060118263A - Method of manufacturing a nand flash memory device - Google Patents

Method of manufacturing a nand flash memory device Download PDF

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KR20060118263A
KR20060118263A KR1020050040870A KR20050040870A KR20060118263A KR 20060118263 A KR20060118263 A KR 20060118263A KR 1020050040870 A KR1020050040870 A KR 1020050040870A KR 20050040870 A KR20050040870 A KR 20050040870A KR 20060118263 A KR20060118263 A KR 20060118263A
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film
flash memory
memory device
semiconductor substrate
nand flash
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KR1020050040870A
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Korean (ko)
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송필근
김영준
한경식
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67075—Apparatus for fluid treatment for etching for wet etching

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A method for manufacturing a NAND flash memory device is provided to improve characteristics of device by removing a seam generated in a poly silicon film and by enhancing step coverage. A pad oxide film and a pad nitride film are deposited on a semiconductor substrate(100). The pad nitride film, the pad oxide film, and the semiconductor substrate are etched to form a trench having a predetermined depth. An oxide film is deposited at the entire surface of the semiconductor substrate to fill the trench. After the resulting structure is patterned by a chemical mechanical polishing until the pad nitride film is exposed, the pad nitride film is removed to form a device isolation film(106) having a nipple. After a firs poly silicon film(110) is formed at an entire surface of the semiconductor substrate, a seam of the first poly silicon film is removed by an etch process. A second poly silicon film(114) is formed at a part of the first poly silicon film in which the seam is removed.

Description

낸드 플래쉬 메모리 소자의 제조방법{Method of manufacturing a nand flash memory device}Method of manufacturing a NAND flash memory device

도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 낸드 플래쉬 메모리 소자의 제조방법을 설명하기 위해 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100 : 반도체 기판 102 : 패드 산화막100 semiconductor substrate 102 pad oxide film

104 : 패드 질화막 106 : 소자분리막104: pad nitride film 106: device isolation film

108 : 터널 산화막 110 : 제1폴리실리콘막108 tunnel oxide film 110 polysilicon film

112 : 마스크 114 : 제2폴리실리콘막112 mask 114 second polysilicon film

본 발명은 낸드 플래쉬 메모리 소자의 제조방법에 관한 것으로, 특히, 심 (seam)을 제거하기 위한 낸드 플래쉬 메모리 소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a NAND flash memory device, and more particularly, to a method of manufacturing a NAND flash memory device for removing a seam.

현재 플래쉬 메모리 소자를 개발함에 있어 기존의 STI(Shallow Trench Isolation) 공정을 이용한 소자분리막 형성 공정은 이후 플로팅 게이트를 형성하기 위한 폴리실리콘막 증착 공정의 오버레이 마진(overlay margin)이 부족하여 사진 식각 공정이 어렵고, 폴리실리콘막 증착시 심 발생을 억제하기 위해 소자분리막간의 공간을 충분히 확보하면 소자의 축소화(shrink)가 이루어지지 않는다. 이러한 문제점을 해결하면서 동시에 사진 식각 장비의 원가 절감이 가능한 자기정렬 플로팅 게이트(Self Aligned Floating Gate; SAFG) 공정을 적용하였다.In developing flash memory devices, the device isolation film forming process using the conventional shallow trench isolation (STI) process has a lack of an overlay margin of the polysilicon film deposition process for forming a floating gate. It is difficult, and if the space between the device isolation film is sufficiently secured to suppress the generation of seam during polysilicon film deposition, the device does not shrink. In order to solve these problems, a Self Aligned Floating Gate (SAFG) process, which can reduce the cost of photolithography equipment, is applied.

이러한 자기정렬 플로팅 게이트 공정을 개략적으로 설명하면 다음과 같다.The self-aligning floating gate process will be described as follows.

반도체 기판 상부에 패드 산화막 및 패드 질화막을 증착한 후, 패드 질화막, 패드 산화막 및 반도체 기판을 식각하여 소정의 깊이를 갖는 트렌치를 형성한다. 트렌치 내를 매립하기 위해 반도체 기판 전면에 절연막을 증착한 후, CMP(Chemical Mechanical Polishing) 공정으로 패드 질화막이 노출될 때까지 평탄화 시킨다. 그런 다음, 패드 질화막을 제거하여 니플(nipple)을 갖는 소자분리막을 형성한 후, 반도체 기판 상부에 터널 산화막을 형성한다. 그리고 반도체 기판 상부에 폴리실리콘막을 형성한 후, 니플이 노출되도록 CMP 공정을 실시하여 플로팅 게이트를 형성한다.After depositing the pad oxide film and the pad nitride film on the semiconductor substrate, the pad nitride film, the pad oxide film and the semiconductor substrate are etched to form a trench having a predetermined depth. An insulating film is deposited on the entire surface of the semiconductor substrate to fill the trench, and then planarized until the pad nitride film is exposed by a chemical mechanical polishing (CMP) process. Thereafter, the pad nitride film is removed to form a device isolation film having a nipple, and then a tunnel oxide film is formed on the semiconductor substrate. After the polysilicon layer is formed on the semiconductor substrate, a floating gate is formed by performing a CMP process to expose the nipple.

그러나, 종래기술과 같은 방법으로 플래쉬 메모리 소자를 형성하면, 폴리실리콘막을 증착하기 전에 소자분리막의 니플의 프로파일(profile)이 버티컬 (vertical)하게 형성되고, 소자분리막 사이의 폭이 좁고 깊이가 깊어 폴리실리콘막 증착 공정시 폴리실리콘막에 대한 스텝커버리지(stepcoverage)가 좋지 않게되어 심 이 발생하게된다. 이로 인해, 후속 공정 단계인 ONO 유전체막을 형성할 때, ONO의 첫번째 산화막이 심 부분에 매몰되어 첫번째 산화막의 두께가 얇아지게 되어 소자의 전체적인 특성을 열화시킨다.However, when the flash memory device is formed in the same manner as in the prior art, a profile of the nipple of the device isolation film is vertically formed before the polysilicon film is deposited, and the width between the device isolation films is narrow and the depth is deep. In the silicon film deposition process, the step coverage of the polysilicon film becomes poor and leads to seam. As a result, when the ONO dielectric film, which is a subsequent process step, is formed, the first oxide film of ONO is buried in the core portion and the thickness of the first oxide film is thinned, thereby degrading the overall characteristics of the device.

상술한 문제점을 해결하기 위해 안출된 본 발명의 목적은 폴리실리콘막에 발생한 심을 제거하고, 스텝커버리지를 향상시켜 소자의 특성을 향상 시킬 수 있는 낸드 플래쉬 메모리 소자의 제조방법을 제공하는데 있다.An object of the present invention devised to solve the above problems is to provide a method of manufacturing a NAND flash memory device that can remove the seam generated in the polysilicon film, improve step coverage and improve the characteristics of the device.

본 발명의 일 실시예에 따른 낸드 플래쉬 메모리 소자의 제조방법은, 반도체 기판 상부에 패드 산화막 및 패드 질화막을 증착하는 단계와, 상기 패드 질화막, 패드 산화막 및 반도체 기판을 식각하여 소정의 깊이를 갖는 트렌치를 형성하는 단계와, 상기 트렌치가 매립되도록 상기 반도체 기판 전면에 산화막을 증착하는 단계와, 화학적 기계적 연마 공정으로 상기 패드 질화막이 노출될 때까지 평탄화 시킨 후, 상기 패드 질화막을 제거하여 니플을 갖는 소자분리막을 형성하는 단계와, 상기 반도체 기판 전면에 제1폴리실리콘막을 형성한 후, 심이 발생한 부분을 제외한 나머지 부분에 마스크를 형성하는 단계와, 상기 마스크를 이용하여 상기 제1폴리실리콘막의 심을 제거하는 단계와, 심이 제거된 부분에 제2폴리실리콘막을 형성하는 단계를 포함하는 낸드 플래쉬 메모리 소자의 제조방법을 제공한다.A method of manufacturing a NAND flash memory device according to an embodiment of the present invention includes depositing a pad oxide film and a pad nitride film on a semiconductor substrate, and etching the pad nitride film, the pad oxide film, and the semiconductor substrate to have a predetermined depth. Forming an oxide film, depositing an oxide film on the entire surface of the semiconductor substrate to fill the trench, and planarizing the pad nitride film by exposure to the pad nitride film by a chemical mechanical polishing process, and then removing the pad nitride film to obtain a device having a nipple. Forming a separator, forming a first polysilicon film on the entire surface of the semiconductor substrate, and then forming a mask on the remaining portions except for the portion where the seam is generated, and removing the seam of the first polysilicon film by using the mask. And forming a second polysilicon film on the portion from which the shim has been removed. It provides a method for producing de flash memory device.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 낸드 플래쉬 메모리 소자의 제조방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A to 1D are cross-sectional views sequentially illustrating devices for manufacturing a NAND flash memory device according to an exemplary embodiment of the present invention.

도 1a를 참조하면, 반도체 기판(100) 상부에 패드 산화막(102) 및 패드 질화막(104)을 증착한 후, 패드 질화막(104), 패드 산화막(102) 및 반도체 기판(100)을 식각하여 소정의 깊이를 갖는 트렌치를 형성한다. Referring to FIG. 1A, after the pad oxide layer 102 and the pad nitride layer 104 are deposited on the semiconductor substrate 100, the pad nitride layer 104, the pad oxide layer 102, and the semiconductor substrate 100 are etched. Form a trench with a depth of.

이어서, 트렌치 내를 매립하기 위해 반도체 기판(100) 전면에 산화막을 증착한 후, CMP 공정으로 패드 질화막(104)이 노출될 때까지 평탄화시킨다. 이때, CMP 공정은 LSS(Low Selectivity Slurry)를 이용하여 산화막을 일부 식각한 다음, HSS(High Selectivity Slurry)를 이용하여 패드 질화막(104) 상부까지 식각하여 평탄화시킨다.Subsequently, an oxide film is deposited on the entire surface of the semiconductor substrate 100 to fill the trench, and then planarized until the pad nitride film 104 is exposed by the CMP process. In this case, in the CMP process, the oxide layer is partially etched by using a low selectivity slurry (LSS), and then the planarized by etching to the top of the pad nitride layer 104 by using a high selectivity slurry (HSS).

도 1b를 참조하면, 패드 질화막(104)을 제거하여 니플을 갖는 소자분리막 (106)을 형성한 후, 반도체 기판(100) 상부에 터널 산화막(108)을 형성한다. 그런 다음, 반도체 기판(100) 상부에 제1폴리실리콘막(110)을 형성한다. 이때, 소자분리막(106) 사이의 폭이 좁고 깊이가 깊어 제1폴리실리콘막(110) 형성시 심(A)이 발생하게 된다. 심(A)을 제거하기 위해 심(A)이 발생한 부분을 제외한 나머지 부분에 마스크(112)를 형성한다. Referring to FIG. 1B, after the pad nitride layer 104 is removed to form an isolation layer 106 having a nipple, a tunnel oxide layer 108 is formed on the semiconductor substrate 100. Then, the first polysilicon film 110 is formed on the semiconductor substrate 100. At this time, since the width between the device isolation layer 106 is narrow and deep, the seam A is generated when the first polysilicon layer 110 is formed. In order to remove the shim A, a mask 112 is formed on the remaining portion except for the shim A.

도 1c를 참조하면, 마스크(112)를 이용하여 심(A)이 발생한 부분의 제1폴리 실리콘막(110)을 건식 식각하여 심(A)을 제거한다. 이때, 건식 식각은 Cl2, HBr, He 및 O2등의 가스를 이용하여 20mTorr 내지 100mTorr의 압력으로 실시한다. Referring to FIG. 1C, the first polysilicon film 110 of the portion where the shim A is generated is dry-etched using the mask 112 to remove the shim A. FIG. At this time, the dry etching is performed at a pressure of 20mTorr to 100mTorr using gases such as Cl 2 , HBr, He and O 2 .

한편, 심이 발생한 부분의 제1폴리실리콘막(110)을 습식 식각하여 심을 제거하기도 한다. 이때, 습식 식각은 KOH 용액 또는 DI 및 KOH 혼합 용액을 사용하고, DI 및 KOH 혼합 용액은 10:1 내지 20:1 비율로 희석하여 사용한다.Meanwhile, the seam may be removed by wet etching the first polysilicon film 110 at the portion where the seam is generated. In this case, wet etching is performed using a KOH solution or a DI and KOH mixed solution, and a DI and KOH mixed solution is diluted in a ratio of 10: 1 to 20: 1.

도 1d를 참조하면, 심 제거로 인하여 식각된 부분에 제2폴리실리콘막(114)을 한번 더 형성한 후, 인-시튜(in-situ)로 어닐 공정을 실시한다. Referring to FIG. 1D, after the second polysilicon film 114 is formed once more on the portion etched due to the removal of the seam, an annealing process is performed in-situ.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지하여야 한다. 또한, 본 발명의 기술 분야에서 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같이 본 발명에 의하면, 폴리실리콘막 형성시 발생된 심을 제거하기 위해 건식 식각 또는 습식 식각하여 심을 제거한 후, 식각된 부분에 다시 폴리실리콘막을 형성함으로써 스텝커버리지를 향상시켜 심 발생을 억제할 수 있다. 또한, 소자의 특성을 향상시켜 수율을 증대시킬 수 있는 효과가 있다.As described above, according to the present invention, after removing the seam by dry etching or wet etching to remove the seam generated during the polysilicon film formation, the polysilicon film is formed on the etched portion to improve the step coverage to suppress seam generation. Can be. In addition, there is an effect that can increase the yield by improving the characteristics of the device.

Claims (8)

반도체 기판 상부에 패드 산화막 및 패드 질화막을 증착하는 단계;Depositing a pad oxide film and a pad nitride film on the semiconductor substrate; 상기 패드 질화막, 패드 산화막 및 반도체 기판을 식각하여 소정의 깊이를 갖는 트렌치를 형성하는 단계;Etching the pad nitride film, the pad oxide film, and the semiconductor substrate to form a trench having a predetermined depth; 상기 트렌치가 매립되도록 상기 반도체 기판 전면에 산화막을 증착하는 단계;Depositing an oxide film over the semiconductor substrate so that the trench is buried; 화학적 기계적 연마 공정으로 상기 패드 질화막이 노출될 때까지 평탄화 시킨 후, 상기 패드 질화막을 제거하여 니플을 갖는 소자분리막을 형성하는 단계;Forming a device isolation film having a nipple by planarizing until the pad nitride film is exposed by a chemical mechanical polishing process, and then removing the pad nitride film; 상기 반도체 기판 전면에 제1폴리실리콘막을 형성한 후, 식각 공정으로 상기 제1폴리실리콘막의 심을 제거하는 단계; 및Forming a first polysilicon film on the entire surface of the semiconductor substrate, and then removing a core of the first polysilicon film by an etching process; And 심이 제거된 부분에 제2폴리실리콘막을 형성하는 단계를 포함하는 낸드 플래쉬 메모리 소자의 제조방법.A method of manufacturing a NAND flash memory device comprising forming a second polysilicon film on a portion where a shim is removed. 제1항에 있어서, 상기 화학적 기계적 연마 공정은 LSS 및 HSS를 이용하여 평탄화 시키는 것을 특징으로 하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 1, wherein the chemical mechanical polishing process is planarized using LSS and HSS. 제1항에 있어서, 상기 심은 건식 식각 또는 습식 식각으로 제거하는 것을 특 징으로 하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 1, wherein the shim is removed by dry etching or wet etching. 제3항에 있어서, 상기 건식 식각은 Cl2, HBr, He 및 O2등의 가스를 이용하여 20mTorr 내지 100mTorr의 압력으로 실시하는 것을 특징으로 하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 3, wherein the dry etching is performed at a pressure of 20 mTorr to 100 mTorr using gases such as Cl 2 , HBr, He, and O 2 . 제3항에 있어서, 상기 습식 식각은 KOH 용액 또는 DI 및 KOH 혼합 용액을 사용하는 것을 특징으로 하는 낸드 플래쉬 메모리 소자의 제조방법.The method of claim 3, wherein the wet etching uses a KOH solution or a mixture of DI and KOH. 제5항에 있어서, 상기 DI 및 KOH 혼합 용액은 10:1 내지 20:1 비율로 희석하는 것을 특징으로 하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 5, wherein the DI and KOH mixed solution is diluted in a ratio of 10: 1 to 20: 1. 제3항에 있어서, 상기 습식 식각은 80℃ 내지 160℃의 온도로 실시하는 것을 특징으로 하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 3, wherein the wet etching is performed at a temperature of 80 ° C. to 160 ° C. 5. 제1항에 있어서, 상기 제2폴리실리콘막을 형성한 후, 인-시튜에서 어닐공정을 실시하는 단계를 더 포함하는 것을 특징으로 하는 낸드 플래쉬 메모리 소자의 제조방법.The NAND flash memory device of claim 1, further comprising performing an annealing process in-situ after the second polysilicon film is formed.
KR1020050040870A 2005-05-16 2005-05-16 Method of manufacturing a nand flash memory device KR20060118263A (en)

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