KR20060111163A - Driving apparatus for display device - Google Patents

Abstract

A driving apparatus for a display device is provided to secure operation reliability at low and high temperature ranges by controlling the size of clock, gate, and scan signals applied to a gate driving unit according to the temperature, to decrease power consumption, and to prevent degradation of a transistor of the gate driving unit. A driving apparatus for a display device having plural pixels including switching elements comprises a gate driving unit applying a gate signal to the switching element; a level shifter(450) connected to the gate driving unit; and a sensing unit(700) for generating a control signal(SCONT1) corresponding to the peripheral temperature of the display device and applying the control signal to the level shifter.

Description

Drive device for display device {DRIVING APPARATUS FOR DISPLAY DEVICE}

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a gate driver according to an exemplary embodiment of the present invention.

FIG. 4 is an example of a circuit diagram of the j-th stage of the shift register for gate driver shown in FIG.

5 is a signal waveform diagram of the gate driver illustrated in FIG. 3.

6 is a block diagram of a detector according to an exemplary embodiment of the present invention.

FIG. 7 is an example of a circuit diagram of the temperature sensing unit shown in FIG. 6.

FIG. 8 is an equivalent circuit diagram of the temperature sensing unit shown in FIG. 7.

9 is a graph illustrating changes in gate voltage and common voltage according to temperature in the driving apparatus for a display device according to an exemplary embodiment of the present invention.

The present invention relates to a driving device of a display device.

Recently, organic light emitting display (OLED), plasma display panel (PDP), and liquid crystal display (LCD) are substituted for heavy and large cathode ray tube (CRT). Flat panel display devices such as are being actively developed.

PDP is a device that displays characters or images using plasma generated by gas discharge, and OLED displays characters or images by using electroluminescence of specific organic materials or polymers. The liquid crystal display device applies an electric field to a liquid crystal layer interposed between two display panels, and adjusts the intensity of the electric field to adjust a transmittance of light passing through the liquid crystal layer to obtain a desired image.

Among such flat panel display devices, for example, a liquid crystal display and an OLED may include a pixel including a switching element, a display panel having a display signal line, and a gate to turn on / off a switching element of a pixel by sending a gate signal to a gate line among the display signal lines. A driver, i.e. a shift register.

The shift register includes a plurality of stages connected to each other, each stage including a plurality of transistors, and outputting an output based on the output of the front and rear stages and in synchronization with any one of the plurality of clock signals.

Such a shift register may be formed in the same process as the switching element of the pixel and may be integrated in the display panel. In the case of integrating the shift register into the display device as described above, it is sensitive to temperature due to the characteristics of the polycrystalline silicon or amorphous silicon constituting the transistor, so that reliability of operation at high and low temperatures is problematic. The voltage is applied higher at room temperature.

However, at room temperature, even at a voltage lower than this, the power consumption increases due to the high voltage, and the characteristics of the transistor are easily deteriorated at high temperatures, thereby causing high temperature reliability.

Accordingly, an object of the present invention is to provide a driving device of a display device that can solve the problems of the prior art.

According to an embodiment of the present invention for achieving the above technical problem, a driving device of a display device including a plurality of pixels each including a switching element, a gate driver for applying a gate signal to the switching element, the gate driver A level shifter connected to the level shifter and a sensing unit generating a control signal according to an ambient temperature of the display device and applying the level shifter to the level shifter.

The sensing unit may include a temperature sensing unit generating a signal according to the ambient temperature, and a sampling and holding circuit connected to the temperature sensing unit, and further comprising a controller connected to the sampling and hold circuit. Can be.

The level shifter may apply a predetermined pulse signal to the detector.

The temperature sensing unit may include first and second resistors connected in series between the pulse signal and the ground voltage, and connected in series between the pulse signal and the voltage and connected in parallel with the first and second resistors. A third and fourth resistor, a differential amplifier connected between a first contact between the first resistor and the second resistor and a second contact between the third resistor and the fourth resistor; It is preferable that the resistance of the first resistor and the fourth resistor change according to the ambient temperature.

It is preferable that the resistance of the second and third resistors do not change according to the ambient temperature.

The first resistor is a transistor in which an input terminal and a control terminal are connected to the pulse signal, and an output terminal is connected to the first contact, and the fourth resistor is an input terminal and a control terminal connected to the second contact. Preferably, the output terminal is a transistor connected to the ground voltage.

The gate driver may be integrated in the display device, and the transistor may be integrated with the gate driver.

The gate signal includes a gate on voltage for turning on the switching element and a gate off voltage for turning off the switching element. When the ambient temperature is increased, the gate on voltage becomes smaller than room temperature and the gate off voltage becomes larger than room temperature. It is preferable.

The display device may further include a common voltage generator configured to provide a common voltage to the level shifter, wherein the common voltage is larger than room temperature as the ambient temperature increases.

The level shifter may supply a driving signal necessary for the operation of the gate driver, and the driving signal may include a clock signal.

The level shifter may supply a control signal required for the operation of the gate driver, and the control signal may include a scan start signal.

The pulse signal preferably has a duty ratio of 25% or less.

The magnitude of the pulse signal may vary depending on the output from the controller, and the controller may be a proportional controller, a proportional integral controller, or a proportional integral derivative controller.

The magnitude of the pulse signal may be constant.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A display device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the display device according to an exemplary embodiment of the present invention includes a display panel 300, a gate driver 400 connected thereto, a data driver 500, and a gray voltage generator connected to the data driver 500. 800, and a signal controller 600 for controlling them.

The display panel unit 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels Px connected to the plurality of display signal lines G ₁ -G _n and D ₁ -D _m in an equivalent circuit.

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n transmitting gate signals (also called scan signals) and data lines D ₁ transferring data signals. includes -D _m). gate lines (G ₁ -G _n) extend in a substantially row direction and are substantially parallel to the data lines (D ₁ -D _m) to each other and extending substantially in a column direction are substantially parallel to each other .

Each pixel includes a switching element Q connected to the display signal lines G ₁ -G _n , D ₁ -D _m , and a pixel circuit PX connected thereto.

The switching element Q is a three-terminal element whose control terminal and input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively, and the output terminal is the pixel circuit PX. Is connected to. In addition, the switching element Q is preferably a thin film transistor, and particularly preferably comprises amorphous silicon.

In the case of a liquid crystal display device which is a representative example of a flat panel display device, as shown in FIG. 2, the display panel unit 300 includes a lower panel 100, an upper panel 200, and a liquid crystal layer 3 therebetween. The display signal lines G ₁ -G _n , D ₁ -D _m and the switching elements Q are provided on the lower display panel 100. The pixel circuit PX of the liquid crystal display includes a liquid crystal capacitor C _LC and a storage capacitor C _ST connected in parallel to the switching element Q. The holding capacitor C _ST can be omitted as necessary.

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel should be able to display color, which is provided with a color filter 230 of three primary colors, for example, red, green, or blue, in a region corresponding to the pixel electrode 190. It is possible by doing. In FIG. 2, the color filter 230 is formed on the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

Polarizers (not shown) for polarizing light are attached to outer surfaces of at least one of the two display panels 100 and 200 of the display panel unit 300 of the liquid crystal display device.

Referring back to FIG. 1, the gray voltage generator 800 generates one or two gray voltages related to the luminance of the pixel. If there are two sets, one of the sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is integrated in the display panel unit 300 and is connected to the gate lines G ₁ -G _n to turn on the switching element Q and the gate on voltage V _on and the switching element Q. to be applied to turn the gate signal which is a combination of a gate-off voltage (V _off) which can be turned off the gate lines (G ₁ -G _n).

The data driver 500 is connected to the data lines D ₁ -D _m of the display panel 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal.

The detector 700 detects a temperature around the display device and generates a signal Vs accordingly.

The level shifter 450 emits a pulse signal Vp and a sensing control signal SCONT1 in response to the sensing signal Vs from the sensing unit 700.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

The display operation of such a display device will now be described in more detail.

The signal controller 600 may control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal and the input image signals R, G, and B, and generates the image signals R, G, and B. After appropriately processing the display panel unit 300 according to the operating conditions, the gate control signal CONT1 is sent to the level shifter 450, and the data control signal CONT2 and the processed image signal DAT are transferred to the data driver 500. Export.

The gate control signal (CONT1) is the gate-on scanning start instructing the start of output of a voltage (V _on) signal (STV), a gate-on voltage (V _on) on-voltage gate clock signal (CPV), and a gate for controlling the output timing of the An output enable signal OE or the like that defines the duration of V _on .

The data control signal CONT2 is a load signal LOAD and a data clock signal for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data DAT and the data lines D ₁ -D _m . (HCLK). In the case of the liquid crystal display shown in FIG. 2, an inverted signal (RVS) inverting the polarity of the data voltage with respect to the common voltage V _com (hereinafter, referred to as the polarity of the data voltage by reducing the polarity of the data voltage with respect to the common voltage). ) May also be included.

The data driver 500 sequentially receives the image data DAT corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and among the gray voltages from the gray voltage generator 800. By selecting the gray scale voltage corresponding to each image data DAT, the image data DAT is converted into a corresponding data voltage and applied to the data lines D ₁ -D _m .

The level shifter 450 adjusts the magnitude of the gate control signal CONT1 and the magnitude of the gate signals Von and Voff from the gate signal generator (not shown) according to the detection signal Vs from the detector 700. The adjusted sensing control signal SCONT1 is applied to the gate driver 400.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the sensing control signal SCONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to. The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

In the case of the liquid crystal display shown in FIG. 2, the difference between the data voltage applied to the pixel and the common voltage V _com is represented as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. This change in polarization is represented by a change in transmittance of light by polarizers attached to the display panels 100 and 200.

After one horizontal period (or 1H ″) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 may move to the next row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply the data voltages to all the pixels. In the case of the liquid crystal display shown in Fig. 2, in particular, when one frame ends, the next frame is started and the data driver 500 is applied to the data driver 500 such that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame. The state of the inverted signal RVS being controlled is controlled ("frame inversion"), in which the polarity of the data voltage flowing through one data line is changed ("line inversion") according to the characteristics of the inversion signal RVS within one frame. ), One pixel row The polarity of the data voltage to be applied may also be different from one another ( "dot inversion").

Next, the gate driver of the display device according to an exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 3 to 5.

3 is a block diagram of a gate driver according to an exemplary embodiment of the present invention. FIG. 4 is an example of a circuit diagram of the j-th stage of the shift register for gate driver shown in FIG. 3, and FIG. 5 is a signal waveform diagram of the gate driver shown in FIG.

The gate driver 400 shown in FIG. 3 is a shift register including a plurality of stages 410 arranged in a line and connected to the gate lines G ₁ -G _n , respectively, and include a scan start signal STV, The initialization signal INT, the plurality of clock signals CLK1 and CLK2 and the gate off voltage V _off are input.

Each stage 410 includes a set terminal S, a gate voltage terminal GV, a pair of clock terminals CK1 and CK2, a reset terminal R, a frame reset terminal FR, and a gate output terminal ( OUT1) and carry output terminal OUT2.

Each stage, for example, the j-th stage (ST _j) the set terminal (S), the carry output of the front end stage (ST _j-1), i.e. shear carry output [Cout (j-1)] is a reset terminal ( The gate output of the rear stage ST _{j + 1} , that is, the rear gate output Gout (j + 1) is input to R, and the clock signals CLK1 and CLK2 are input to the clock terminals CK1 and CK2. The gate off voltage V _off is input to the gate voltage terminal GV. The gate output terminal OUT1 outputs the gate output Gout (j) and the carry output terminal OUT2 outputs the carry output Cout (j).

However, the scan start signal STV is input to the first stage of the shift register 400 instead of the front carry output. Further, when the clock signal CLK1 is input to the clock terminal CK1 of the j-th stage ST _j and the clock signal CLK2 is input to the clock terminal CK2, the (j-1) th and (j) adjacent thereto are The clock signal CLK2 is input to the clock terminal CK1 of the ₊ 1th stage ST _j-1 and ST _{j + 1} , and the clock signal CLK1 is input to the clock terminal CK2.

Each clock signal CLK1 and CLK2 is equal to the gate-on voltage V _on when the voltage level is high and the gate-off voltage V _off when the voltage level is high so as to drive the switching element Q of the pixel. The same is preferable. As shown in FIG. 5, each clock signal CLK1 and CLK2 may have a duty ratio of 50%, and a phase difference between the two clock signals CLK1 and CLK2 may be 180 °.

Referring to FIG. 4, each stage of the gate driver 400 according to an embodiment of the present invention, for example, the j th stage, includes the input unit 420, the pull-up driver 430, And a pull-down driver 440 and an output unit 450. These include at least one NMOS transistor T1-T14, and the pull-up driver 430 and the output unit 450 further include capacitors C1-C3. However, PMOS transistors may be used instead of NMOS transistors. In addition, the capacitors C1-C3 may actually be parasitic capacitances between the gate and the drain / source formed during the process.

The input unit 420 includes three transistors T11, T10, and T5 connected in series to the set terminal S and the gate voltage terminal GV. Gates of the transistors T11 and T5 are connected to the clock terminal CK2, and gates of the transistor T5 are connected to the clock terminal CK1. The contact between the transistor T11 and the transistor T10 is connected to the contact J1, and the contact between the transistor T10 and the transistor T11 is connected to the contact J2.

The pull-up driving unit 430 includes a transistor T4 connected between the set terminal S and the contact J1, a transistor T12 connected between the clock terminal CK1 and the contact J3, and a clock terminal ( And transistor T7 connected between CK1) and contact J4. The gate and the drain of the transistor T4 are commonly connected to the set terminal S, the source is connected to the contact J1, and the gate and the drain of the transistor T12 are commonly connected to the clock terminal CK1. And the source is connected to contact J3. The gate of the transistor T7 is connected to the contact J3 and at the same time connected to the clock terminal CK1 through the capacitor C1, the drain is connected to the clock terminal CK1, the source is connected to the contact J4. , Capacitor C2 is connected between contact J3 and contact J4.

The pull-down driver 440 receives the gate-off voltage V _off through a source and outputs a plurality of transistors T6, T9, T13, T8, T3, and T2 through a drain to the contacts J1, J2, J3, and J4. ). The gate of the transistor T6 is connected to the frame reset terminal FR, the drain is connected to the contact J1, the gate of the transistor T9 is connected to the reset terminal R, and the drain is connected to the contact J1. The gates of the transistors T13 and T8 are commonly connected to the contact J2, and the drains are connected to the contacts J3 and J4, respectively. The gate of the transistor T3 is connected to the contact J4, the gate of the transistor T2 is connected to the reset terminal R, and the drains of the two transistors T3 and T2 are connected to the contact J2.

The output unit 450 includes a pair of transistors T1 and T14 having a drain and a source connected between the clock terminal CK1 and the output terminals OUT1 and OUT2 and a gate connected to the contact J1, respectively. And a capacitor C3 connected between the gate and the drain of T1, that is, between the contact J1 and the contact J2. The source of transistor T1 is also connected to contact J2.

The operation of such a stage will now be described.

For convenience of explanation, the voltage corresponding to the high level of the clock signals CLK1 and CLK2 is referred to as a high voltage, and the magnitude of the voltage corresponding to the low level of the clock signals CLK1 and CLK2 is equal to the gate off voltage V _off . This is called low voltage.

First, when the clock signal CLK2 and the front carry output Cout (j-1) become high, the transistors T11 and T5 and the transistor T4 are turned on. Then, the two transistors T11 and T4 transfer a high voltage to the contact J1, and the transistor T5 transfers a low voltage to the contact J2. As a result, the transistors T1 and T14 are turned on so that the clock signal CLK1 is output to the output terminals OUT1 and OUT2. At this time, since the voltage of the contact J2 and the clock signal CLK1 are both low voltages, the output voltage [ Gout (j) and Cout (j)] become low voltage. At the same time, the capacitor C3 charges a voltage having a magnitude corresponding to the difference between the high voltage and the low voltage.

At this time, since the clock signal CLK1 and the rear gate output Gout (j + 1) are low and the contact J2 is also low, the transistors T10, T9, T12, T13, T8, and T2 connected to the gate are connected. ) Are all off.

Subsequently, when the clock signal CLK2 becomes low, the transistors T11 and T5 are turned off. At the same time, when the clock signal CLK1 becomes high, the output voltage of the transistor T1 and the voltage of the contact J2 become high. do. At this time, a high voltage is applied to the gate of the transistor T10, but since the potential of the source connected to the contact J2 is also the same high voltage, the potential difference between the gate sources becomes zero, so that the transistor T10 remains turned off. do. Accordingly, the contact J1 is in a floating state, whereby the potential is further increased by the high voltage by the capacitor C3.

On the other hand, since the potentials of the clock signal CLK1 and the contact J2 are high voltage, the transistors T12, T13, and T8 are turned on. In this state, the transistor T12 and the transistor T13 are connected in series between the high voltage and the low voltage, so that the potential of the contact J3 is divided by the resistance value of the resistance state at the turn-on of the two transistors T12 and T13. Voltage value. However, assuming that the resistance value of the resistance state at the turn-on of the two transistors T13 is set to be very large compared to the resistance value of the resistance state at the turn-on of the transistor T12, for example, about 10,000 times, the voltage of the contact J3 is a high voltage. Is almost the same as Accordingly, the transistor T7 is turned on and connected in series with the transistor T8, so that the potential of the contact J4 is divided by the resistance value of the resistance state at the turn-on of the two transistors T7 and T8. Have At this time, if the resistance values of the resistance states of the two transistors T7 and T8 are set to be almost the same, the potential of the contact J4 has an intermediate value between the high voltage and the low voltage, whereby the transistor T3 is turned off. Keep it. At this time, since the rear gate output Gout (j + 1) is still low, the transistors T9 and T2 also remain turned off. Therefore, the output terminals OUT1 and OUT2 are connected only to the clock signal CLK1 and cut off from the low voltage to emit a high voltage.

On the other hand, the capacitor C1 and the capacitor C2 charge voltages corresponding to the potential difference between both ends, respectively, and the voltage of the contact J3 is lower than the voltage of the contact J5.

Subsequently, when the rear gate output Gout (j + 1) and the clock signal CLK2 go high and the clock signal CLK1 goes low, the transistors T9 and T2 are turned on to low voltage to the contacts J1 and J2. To pass. At this time, the voltage of the contact J1 falls to the low voltage while the capacitor C3 discharges, but it takes some time to completely lower to the low voltage due to the discharge time of the capacitor C3. Therefore, the two transistors T1 and T14 remain turned on for a while even after the rear gate output Gout (j + 1) becomes high, so that the output terminals OUT1 and OUT2 are connected to the clock signal CLK1. To emit low voltage. Subsequently, when the capacitor C3 is completely discharged and the potential of the contact J1 reaches a low voltage, the transistor T14 is turned off and the output terminal OUT2 is cut off from the clock signal CLK1, so that the carry output Cout (j) is performed. Becomes floating and maintains low voltage. At the same time, the output terminal OUT1 is continuously connected to the low voltage through the transistor T2 even when the transistor T1 is turned off, thereby continuously outputting the low voltage.

On the other hand, since the transistors T12 and T13 are turned off, the contact J3 is in a floating state. In addition, the voltage of the contact J5 is lower than the voltage of the contact J4. The transistor T7 is turned off because the voltage of the contact J3 is kept lower than the voltage of the contact J5 by the capacitor C1. . At the same time, since the transistor T8 is also turned off, the voltage at the contact J4 is lowered by that amount, so that the transistor T3 also remains turned off. In addition, the transistor T10 maintains the turn-off state because the gate is connected to the low voltage of the clock signal CLK1 and the voltage of the contact J2 is low.

Next, when the clock signal CLK1 becomes high, the transistors T12 and T7 are turned on, the voltage at the contact J4 is increased to turn on the transistor T3, and the low voltage is transferred to the contact J2. OUT1) continues to emit a low voltage. That is, even if the rear gate output Gout (j + 1) has a low output, the voltage of the contact J2 can be made low.

Meanwhile, since the gate of the transistor T10 is connected to the high voltage of the clock signal CLK1 and the voltage of the contact J2 is a low voltage, the gate of the transistor T10 is turned on to transfer the low voltage of the contact J2 to the contact J1. On the other hand, the clock terminal CK1 is connected to the drains of the two transistors T1 and T14, and the clock signal CLK1 is continuously applied. In particular, the transistor T1 is made relatively larger than the rest of the transistors, so that the parasitic capacitance between gate drains is large, so that the voltage change of the drain may affect the gate voltage. Therefore, when the clock signal CLK1 becomes high, the gate voltage may increase due to the parasitic capacitance between the gate and drain gates, thereby turning on the transistor T1. Therefore, the low voltage of the contact J2 is transferred to the contact J1 to maintain the gate voltage of the transistor T1 at a low voltage, thereby preventing the transistor T1 from turning on.

Thereafter, the voltage at the contact J1 maintains a low voltage until the front carry output Cout (j-1) becomes high, and the voltage at the contact J2 has the clock signal CLK1 high and the clock signal CLK2. Is low, the low voltage is maintained through the transistor T3, and vice versa, the low voltage is maintained through the transistor T5.

On the other hand, the transistor T6 receives the initialization signal INT generated in the last dummy stage ST _{n + 1} (not shown) and transfers the gate-off voltage V _off to the contact J1 to contact the contact ( Set the voltage of J1) to the low voltage again.

In this manner, the stage 410 is based on the front carry signal Cout (j-1) and the back gate signal Gout (j + 1) and is synchronized with the clock signals CLK1 and CLK2 to carry the carry signal Cout ( j)] and the gate signal Gout (j).

Next, the sensing unit of the display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 6 to 8.

FIG. 6 is a detector of a display device according to an exemplary embodiment of the present invention, FIG. 7 is a circuit diagram of the temperature detector shown in FIG. 6, FIG. 8 is an equivalent circuit diagram of the temperature detector illustrated in FIG. 7, and FIG. It is a graph showing the change of the gate voltage and the common voltage according to the temperature.

Referring to FIG. 6, the detector 700 of the display device according to an exemplary embodiment may include a temperature detector 710, a sampling and hold circuit 720 connected thereto, and a PI controller. 730.

The temperature sensor 710 receives the pulse signal Vp from the level shifter 450 and outputs information on the surrounding temperature in the form of voltage Vout.

The sampling and holding circuit 720 samples and holds the output Vout from the temperature sensing unit 710 in a predetermined time unit, and maintains an instantaneous value for a predetermined time to provide the PI controller 730 as known. It is preferable that the sampling period of the sampling and holding circuit 720 be adjusted to a high period of the pulse voltage Vp.

The PI controller 730, as is known, provides the level shifter 450 with a control signal Vs obtained by multiplying and integrating a sampled output voltage Vout with a predetermined gain. Of course, a proportional controller or proportional integral derivative controller can be used.

The level shifter 450 adjusts the magnitude of the control signals STV, CLK1 and CLK2 including the gate voltages Von and Voff according to the detection signal Vs from the PI controller 730 and sends them to the gate driver 400. On the other hand, by adjusting the magnitude of the pulse voltage (Vp) is fed back to the temperature sensor 710.

As illustrated in FIG. 7, the temperature detector 710 includes a plurality of transistors M1 and M2, a plurality of resistors R2 and R3 and a differential amplifier 10 connected thereto.

Transistor M1 has an input terminal and a control terminal commonly connected to the pulse signal Vp, and an output terminal connected to the node N1, and the transistor M2 is commonly connected to the node N2. It has an input terminal, a control terminal, and an output terminal grounded. The two transistors M1 and M2 are connected to each other by an input terminal and a control terminal to operate as a kind of diode, and a resistance element whose resistance value changes with temperature. That is, as the temperature increases, the resistance value decreases, and when the temperature decreases, the resistance value increases.

The resistor R2 is connected between the node N1 and the ground through the pads 11 and 12, and the resistor R3 is connected between the pads 21 and 22 to the node N2 and the pulse voltage Vp. have.

In this case, the pads 11, 12, 21, and 22 may include the resistors R2 and R3 provided in the transistors M1 and M2 integrated in the display device and the printed circuit board (not shown). It plays a role. Here, the two resistors R2 and R3 are provided on a printed circuit board or the like and have a property that the resistance value hardly changes with temperature change.

The pulse voltage Vp is applied in the form of a pulse having a constant period to prevent deterioration of the transistors M1 and M2. In addition, the duty ratio of the pulse voltage Vp may be, for example, 25% or less.

In the differential amplifier 10, the non-inverting terminal (+) is connected to one end of the resistor R2, and the inverting terminal (−) is connected to one end of the resistor R3.

As described above, when the transistors M1 and M2 are regarded as resistance elements whose resistance values change with temperature, the resistance values of each of the transistors M1 and M2 are 'R1' and 'R4', as shown in FIG. 7. It can be represented by an equivalent circuit.

The equivalent circuit shown in FIG. 7 is substantially a Wheatstone bridge circuit, in which no current flows between the nodes N1 and N2 when the voltages are the same, and in this case, the output voltage Vout of the differential amplifier 10. Becomes zero.

Here, since the transistors M1 and M2 are formed and integrated in the same process, the characteristics may be considered to be the same, and the resistance values of the two resistors R2 and R3 are also assumed to be the same. Assume the resistance is the same. Then, at room temperature, the values of all resistors (R1-R4) are the same, so the ratio of the resistors located on the left and right with respect to nodes (N1, N2), i.e. The voltage Vout becomes zero.

At this time, for example, when the temperature increases, the resistance values R1 and R4 of the transistors M1 and M2 decrease, so that the voltage of the node N1 increases while the voltage of the node N2 decreases. . The voltage at the node N1 is higher than the voltage at the node N2 so that the output voltage Vout of the differential amplifier 10 has a positive value. On the contrary, when the temperature decreases, the resistance values R1 and R4 increase, so that the output voltage Vout of the differential amplifier 10 has a negative value.

For example, when the node voltages N1 and N2 at room temperature are VN1 and VN2, and the voltage is changed by aV due to the increase in temperature, each node voltage VN1 'and VN2' at the temperature increase is,

VN1 '= VN1 + aV, VN2' = VN2-aV

And the output voltage Vout is

Vout = VN1'-VN2 '= G * 2aV

Same as Where G is the gain of the differential amplifier 10.

The output voltage Vout is an analog signal including information on temperature, and is generated as a sensing signal Vs through the sampling and hold 720 and the PI controller 730 as described above.

At this time, as shown in FIG. 9, the sensing signal Vs controls the level shifter 450 so that the difference between the gate on voltage Von and the gate off voltage Voff decreases when the temperature increases, and when the temperature decreases. The level shifter 450 is controlled to increase the difference between the gate on voltage Von and the gate off voltage Voff.

In addition, since the magnitudes of the clock signals CLK1 and CLK2 and the scan start signal STV described above are the same as the gate-on voltage Von, as the temperature increases, the clock-on voltage Von becomes smaller.

In addition, the level shifter 450 may receive a common voltage Vcom from a common voltage generator (not shown) and control its magnitude. For example, as the temperature increases, the magnitude of the kickback voltage is proportional to the difference between the gate-on voltage Von and the gate-off voltage Voff. As the magnitude of the kickback voltage decreases, the positive pixel voltage becomes larger and the negative pixel voltage becomes smaller, so that the magnitude of the common voltage Vcom can be increased as shown. Of course, when the temperature decreases, the size of the common voltage Vcom may be reduced.

Subsequently, when the gate signals Von and Voff reach a desired level, the output voltage Vout may be zero to maintain the set value by adjusting the magnitude of the pulse voltage Vp.

Meanwhile, according to another embodiment of the present invention, the PI controller 730 may not be used. In this case, as an open-loop system, the pulse voltage Vp always has a constant magnitude. That is, in the above-described embodiment, the magnitude of the pulse voltage Vp may be varied in a closed-loop system using the PI controller 730, while the influence of the output voltage Vout in the open loop system is variable. Since we do not consider, we export a fixed value. Instead, in an open loop system, the output of the sampling and hold circuit 720 includes information about temperature and controls the level shifter 450 based on this information.

As described above, the magnitudes of the clock signals CLK1 and CLK2, the gate signals Von and Voff and the scan signal STV applied to the gate driver 400 are controlled according to temperature. Accordingly, it is possible to ensure operational reliability at low and high temperatures, and to reduce power consumption and prevent degradation of transistors constituting the gate driver 400, thereby extending the lifespan.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (17)

A driving device of a display device including a plurality of pixels each including a switching element, A gate driver for applying a gate signal to the switching element, A level shifter connected to the gate driver, and A detector configured to generate a control signal according to the ambient temperature of the display device and apply the control signal to the level shifter Containing Drive device for display device. In claim 1, The sensing unit A temperature sensor for generating a signal according to the ambient temperature, and Sampling and hold circuit connected to the temperature sensing unit Containing Drive device for display device. In claim 2, And the sensing unit further comprises a controller connected to the sampling and hold circuit. The method of claim 2 or 3, And the level shifter applies a predetermined pulse signal to the sensing unit. In claim 4, The temperature sensing unit First and second resistors connected in series between the pulse signal and a ground voltage; Third and fourth resistors connected in series between the pulse signal and the voltage and connected in parallel with the first and second resistors, A differential amplifier connected between a first contact between the first resistor and the second resistor and a second contact between the third resistor and the fourth resistor Including; The first resistor and the fourth resistor is the resistance changes according to the ambient temperature Drive device for display device. In claim 5, The second and third resistors do not vary in resistance with the ambient temperature. In claim 6, The first resistor is a transistor in which an input terminal and a control terminal are connected to the pulse signal, and an output terminal is connected to the first contact, and the fourth resistor is an input terminal and a control terminal connected to the second contact. And a transistor having an output terminal connected to the ground voltage. In claim 7, And the gate driver is integrated in the display device. In claim 8, And the transistor is integrated with the gate driver. In claim 1, The gate signal includes a gate on voltage for turning on the switching element and a gate off voltage for turning off the switching element; When the ambient temperature is high, the gate on voltage becomes smaller than room temperature and the gate off voltage becomes larger than room temperature. Drive device for display device. In claim 1, The display device further includes a common voltage generator which provides a common voltage to the level shifter. The common voltage increases with respect to room temperature as the ambient temperature increases. Drive device for display device. In claim 1, The level shifter supplies a driving signal necessary for the operation of the gate driver, The drive signal includes a clock signal Drive device for display device. In claim 1, The level shifter supplies a control signal necessary for the operation of the gate driver, The control signal includes a scan start signal. Drive device for display device. In claim 4, And the pulse signal has a duty ratio of 25% or less. In claim 3, And a magnitude of the pulse signal varies in accordance with an output from the controller. The method of claim 15, And the controller is a proportional controller, a proportional integral controller, or a proportional integral differential controller. In claim 2, And a pulse signal having a constant magnitude.

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