KR20060100878A - A liquid crystal display device and a method for driving the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof capable of quickly discharging an afterimage generated when a screen is turned off, and to display a clean image display. A liquid crystal panel having three pixels; A storage capacitor formed between the pixel electrode of each pixel and the gate line; A gate driver sequentially driving the gate lines by sequentially supplying a scan pulse voltage having a gate high voltage and a gate low voltage to gate lines of the liquid crystal panel; And a discharge unit configured to discharge the auxiliary capacitor capacitor to the ground voltage by supplying a pulse voltage to the gate line instantaneously to reach the ground voltage according to a power supply voltage for operating the liquid crystal panel. It is characterized by the configuration.

Liquid crystal display, gate high voltage (VGH), gate low voltage (VGL), front gate, storage capacitor, gate line, discharge, afterimage

Description

A liquid crystal display device and a method for driving the same

1 is an equivalent circuit diagram of one pixel in a conventional liquid crystal display device.

2 is a graph showing voltage-current characteristics of a thin film transistor

3 is a configuration diagram of a liquid crystal display device according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a transmission path with respect to the power supply voltage of FIG. 3.

FIG. 5 is a first configuration diagram of the discharge unit of FIG. 1. FIG.

FIG. 6 is a view for explaining a time point when the power supply voltage, the gate high voltage, and the gate low voltage each fall to the ground voltage when the LCD is turned off.

7 is a view for explaining the principle that the present invention can further reduce the afterimage effect compared to the prior art, when the liquid crystal display is turned off

8 is a diagram illustrating a second configuration of the discharge unit of FIG. 1.

* Explanation of symbols on the main parts of the drawings

210: system 211: interface circuit

212: Timing Controller 213: Data Driver

214: gate driver 215: discharge part

216: DC-DC converter 217: liquid crystal panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and a driving method thereof, and more particularly, to a liquid crystal display and a driving method thereof capable of quickly discharging a gate low voltage applied to a gate line to remove an afterimage on a screen.

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of minimizing kickback voltage by forming a storage capacitor between a pixel electrode and a next gate line.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixels are arranged in an active matrix form, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor formed at each intersection of gate lines and data lines, and a pixel connected to the thin film transistor.

The gate electrode of the thin film transistor is connected to any one of the gate lines in the horizontal line unit, and the source electrode is connected to any one of the data lines in the vertical line unit. The thin film transistor supplies the data signal from the data line to the pixel in response to the gate driving pulse from the gate line.

The pixel includes a pixel electrode connected to the drain electrode of the thin film transistor, and a common electrode facing the pixel electrode and the liquid crystal therebetween. Such a pixel adjusts the light transmittance by driving the liquid crystal in response to a data signal supplied to the pixel electrode.

Hereinafter, a liquid crystal display according to the related art will be described in detail with reference to the accompanying drawings.

1 is an equivalent circuit diagram of one pixel in a conventional liquid crystal display.

That is, as illustrated in FIG. 1, each pixel of the liquid crystal display is defined by a plurality of gate lines GL and data lines DL that cross each other. Each pixel includes a thin film transistor TFT and a pixel. A pixel electrode is provided. Specifically, the thin film transistor TFT is formed at a portion where the gate line GL and the data line DL cross each other, and a gate terminal of the thin film transistor TFT is connected to the gate line GL. A source terminal is connected to the data line DL, and a drain terminal is connected to the pixel electrode.

Meanwhile, the liquid crystal display includes two glass substrates bonded to each other and a liquid crystal layer formed between the glass substrates. FIG. 1 illustrates a bottom glass substrate of the liquid crystal display, that is, the thin film transistor (TFT) array. One pixel in the formed first substrate is shown.

Although not shown in the drawings, the common glass 150 for displaying an R, G, B color filter layer and an image is provided on the upper glass substrate, that is, the second substrate, facing the first substrate with the liquid crystal layer interposed therebetween. Formed. The pixel electrode of the first substrate described above faces the common electrode 150 of the second substrate and the liquid crystal layer therebetween, and the light of the liquid crystal layer is changed by the magnitude of the electric field generated between the two electrodes. The transmittance is controlled. In this case, the pixel electrode and the common electrode 150 facing each other with the liquid crystal layer interposed therebetween function as a liquid crystal capacitor Clc having the liquid crystal layer as a dielectric.

In addition, a part of the pixel electrode included in each pixel is designed to overlap a part of the gate line GL for driving another neighboring pixel, wherein the pixel electrode and the gate line GL facing each other are It functions as a storage capacitor Cst with an insulator as a dielectric. In general, a structure in which the pixel electrode of each pixel overlaps with the gate line GL of another neighboring pixel as described above is called a front gate structure.

The operation of the pixel configured as described above will be described in detail as follows.

First, when the gate high voltage is applied to the gate line GL and the liquid crystal capacitor Clc is turned on, the source terminal and the drain of the turned-on thin film transistor TFT are turned on. The gray level is represented by receiving a voltage applied from the data line DL through a terminal. After the desired voltage is applied to the liquid crystal capacitor Clc, a gate low voltage is applied to the gate line GL to turn off the thin film transistor TFT for one frame. As such, the thin film transistor TFT is turned off due to the gate low voltage, so that the charges charged in the liquid crystal capacitor Clc do not escape through the thin film transistor TFT, thereby displaying a gray scale of one frame. Is maintained. In this case, when the thin film transistor TFT is turned off by charging the charge like the liquid crystal capacitor Clc, the storage capacitor Cst is the liquid crystal capacitor Clc due to the leakage charge amount of the thin film transistor TFT. Reduce the voltage drop across both ends to ensure stable gradation representation for one frame.

The voltage-current characteristics of the thin film transistor TFT are shown in FIG. 2.

2 is a graph illustrating voltage-current characteristics of a thin film transistor.

That is, as shown in FIG. 2, when the Von voltage, that is, the gate high voltage is applied to the gate terminal of the TFT, the Ion current flows, and the voltage already applied to the source terminal is the liquid crystal capacitance. When the Voff voltage, i.e., the gate low voltage, is applied to the gate terminal, the amount of current is extremely limited to the Ioff level so that the liquid crystal capacitor Clc charged by the voltage applied at Von. This will prevent the charge from escaping.

However, the above-described conventional technology has the following problems when the power supply voltage is cut after driving the TFT liquid crystal display.

That is, since the gate low voltage is applied to most of the gate lines GL just before the external power supply voltage of the liquid crystal display is blocked from outside, the gate low voltage is applied to the gate terminal of most TFTs. In the liquid crystal display of the front gate structure, this voltage is charged in the storage capacitor Cst. Therefore, the gate low voltage is always applied to the gate terminal of the thin film transistor TFT until the voltage of the storage capacitor Cst is discharged so that the screen of the liquid crystal display device does not turn off immediately even when the power supply voltage is cut off.

In order to discharge the voltage of the storage capacitor Cst, the thin film transistor TFT must be turned off. Since the storage capacitor Cst maintains the gate low voltage, the storage capacitor Cst ) Is difficult to discharge. For this reason, the liquid crystal display device employing the conventional front gate structure does not disappear quickly even when the power supply voltage is blocked, which causes a problem that an afterimage occurs on the screen.

The present invention has been made to solve the above problems, and detects this when the driving power supply voltage is cut off, and at this time, by applying a gate high voltage to the gate line, the gate low voltage applied to the gate line before the driving power supply voltage blocking is quickly grounded. It is an object of the present invention to provide a liquid crystal display and a driving method thereof capable of rapidly discharging the gate line by allowing the voltage to rise to a voltage.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal panel having a plurality of pixels defined by a plurality of gate lines and data lines perpendicular to each other; A storage capacitor formed between the pixel electrode of each pixel and the gate line; A gate driver sequentially driving the gate lines by sequentially supplying a scan pulse voltage having a gate high voltage and a gate low voltage to gate lines of the liquid crystal panel; And a discharge unit configured to discharge the auxiliary capacitor capacitor to the ground voltage by supplying a pulse voltage to the gate line instantaneously to reach the ground voltage according to a power supply voltage for operating the liquid crystal panel. It is characterized by the configuration.

In addition, the driving method of the liquid crystal display device according to the present invention for achieving the above object, the liquid crystal panel having a plurality of pixels defined by a plurality of gate lines and data lines perpendicular to each other, A liquid crystal including an auxiliary capacitance capacitor formed between the pixel electrode of the pixel and the gate line, and a gate driver sequentially driving the gate line by sequentially supplying a scan pulse voltage including a gate high voltage and a gate low voltage to the gate lines of the liquid crystal panel. In the method of driving a display device, the auxiliary capacitance capacitor is grounded by supplying a pulse voltage to the gate line instantaneously to reach the ground voltage according to a power supply voltage for operating the liquid crystal panel. It is characterized by discharging at a voltage.

Hereinafter, a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4 is a diagram illustrating a transmission path with respect to the power supply voltage of FIG. 3.

In the liquid crystal display according to the exemplary embodiment of the present invention, as shown in FIG. 3, m × n pixels are arranged in a matrix type, and m data lines DL and n gate lines GL are vertically crossed. A liquid crystal panel 217 having a thin film transistor TFT formed at an intersection thereof, a data driver 213 for supplying a data voltage to the data line DL of the liquid crystal panel 217, and the gate line GL. The data driver 213 and the gate using a gate driver 214 for supplying a scan pulse voltage (consisting of a gate low voltage VGL and a gate high voltage VGH) to the gate signal, and a synchronization signal from the interface circuit 211. A timing controller 212 for controlling the driver 214, a DC-DC converter 216 for generating voltages supplied to the liquid crystal panel 217 by receiving a power supply voltage VCC from the system 210; , System 210 It is determined that the liquid crystal display is turned off by detecting whether the power supply voltage VCC is output from the display device. When the liquid crystal display is turned off, a pulse voltage higher than the gate low voltage VGL applied to the gate line GL is detected. And a discharge unit 215 for supplying the gate line GL to discharge the gate line GL to the ground voltage GND.

The system 210 supplies a vertical / horizontal synchronization signal, a clock signal, and data (RGB) to the interface circuit 211 through a low voltage differential signaling (LVDS) transmitter of a graphic controller. The power supply voltage VCC is supplied to each of the digital circuit elements 211, 212, 213, 214, and 215 and the DC-DC converter 216.

Meanwhile, each pixel of the liquid crystal panel 217 is defined by a plurality of gate lines GL and data lines DL that cross each other vertically. Each pixel includes a thin film transistor TFT and a pixel electrode. have. Specifically, the thin film transistor TFT is formed at a portion where the gate line GL and the data line DL cross each other, and a gate terminal of the thin film transistor TFT is connected to the gate line GL. A source terminal is connected to the data line DL, and a drain terminal is connected to the pixel electrode.

Here, the liquid crystal panel 217 includes two glass substrates bonded to face each other and a liquid crystal layer formed between the glass substrates. FIG. 3 illustrates a lower glass substrate of the liquid crystal display, that is, the thin film transistor TFT. ) Shows a first substrate on which an array is formed.

Although not shown in the drawings, the common glass 250 for displaying R, G, and B color filter layers and an image is provided on the upper glass substrate, that is, the second substrate, facing the first substrate with the liquid crystal layer interposed therebetween. Formed. The pixel electrode of the first substrate described above faces the common electrode 250 of the second substrate and the liquid crystal layer therebetween, and has a light transmittance of the liquid crystal layer due to the magnitude of the electric field generated between the two electrodes. This is regulated. In this case, the pixel electrode and the common electrode 250 facing each other with the liquid crystal layer interposed therebetween function as a liquid crystal capacitor Clc having the liquid crystal layer as a dielectric.

In addition, a part of the pixel electrode included in each pixel is designed to overlap a part of the gate line GL for driving another neighboring pixel, wherein the pixel electrode and the gate line GL facing each other are It functions as a storage capacitor Cst with an insulator as a dielectric. In general, a structure in which the pixel electrode of each pixel overlaps with the gate line GL of another neighboring pixel as described above is called a front gate structure.

The data driver 213 converts the digital video data RGB into an analog gamma voltage corresponding to the gray scale value in response to the data control signal DDC from the timing controller 212, and converts the analog gamma voltage into the data. Supply to the line DL. A power voltage VCC is supplied to a data drive integrated circuit in which the data driver 213 is integrated.

The gate driver 214 sequentially supplies a scan pulse voltage to the gate line GL in response to the gate control signal GDC from the timing controller 212 to supply a data voltage. Select the horizontal line. The power supply voltage VCC is supplied to the gate drive integrated circuit in which the gate driver 214 is integrated.

The timing controller 212 is a gate control signal (GDC) for controlling the gate driver 214 using a vertical / horizontal synchronization signal and a clock signal input from the graphic controller of the system 210 via the interface circuit 211. ) And a data control signal DDC for controlling the data driver 213.

On the other hand, the DC-DC converter 216 boosts or reduces the power supply voltage VCC input from the system 210 via a connector (not shown) to generate a voltage supplied to the liquid crystal panel 217. . To this end, the DC-DC converter 216 is an output switching element for switching the output voltage to the output terminal, the pulse width for boosting or reducing the output voltage by controlling the duty ratio or frequency of the control signal of the output switching element It includes a pulse width modulator (PWM) or a pulse frequency modulator (PFM). The pulse width modulator increases the control signal duty ratio of the output switching device to increase the output voltage of the DC-DC converter 216 or decreases the duty ratio of the control signal of the output switching device to the DC-DC converter 216. Decrease the output voltage.

In addition, the pulse frequency modulator increases the control signal frequency of the output switching device to increase the output voltage of the DC-DC converter 216, or lower the frequency of the output switching device to reduce the output voltage of the DC-DC converter 216. Lowers.

Here, the output voltage of the DC-DC converter 216 is a reference voltage (VDD) of 6V or more, a gamma reference voltage (GMA1-10) of less than 10 steps, a common voltage (VCOM) of 2.5 to 3.3V, a gate high voltage of 15V or more. (VGH) and gate low voltage (VGL) of -4V or less. The gamma reference voltages GMA1 to 10 are voltages generated by the divided voltage of the reference voltage VDD.

The reference voltage VDD and the gamma reference voltages GMA1 to 10 are supplied to the data driver 213 as analog gamma voltages. The common voltage VCOM is a voltage supplied to the common electrode 250 formed on the liquid crystal panel 217 via the data driver 213. Here, the gate high voltage VGH is supplied to the gate driver 214 as a high logic voltage of a scan pulse voltage that is set above a threshold voltage of the thin film transistor TFT, and the gate low voltage VGL is supplied to the thin film transistor TFT. Is supplied to the gate driver 214 as the low logic voltage of the scan pulse voltage set to the off voltage. In addition, the gate high voltage VGH and the gate low voltage VGL output from the DC-DC converter 216 are also supplied to the discharge unit 215.

Meanwhile, the discharge unit 215 will be described in more detail as follows.

FIG. 5 is a first configuration diagram of the discharge unit of FIG. 1.

The discharge unit 215, which is a feature of the present invention, includes an inverter 222 that outputs a gate high voltage VGH or a gate low voltage VGL according to the magnitude of the power supply voltage VCC, and the inverter 222. A first NMOS transistor that is turned off in response to a gate low voltage VGL, and is turned on in response to a gate high voltage VGH from the inverter 222 to apply a gate high voltage VGH to the gate line GL (Tr501).

The inverter 222 may include a PMOS transistor Tr502 having a gate terminal to which the power supply voltage VCC is applied, and a source terminal to which a gate high voltage VGH from the DC-DC converter 216 is applied. A gate terminal connected to the gate terminal of the PMOS transistor Tr502, a source terminal connected to the drain terminal of the PMOS transistor Tr502, and a gate low voltage VGL output from the DC-DC converter 216 And a second NMOS transistor Tr503 having a drain terminal applied thereto. The first NMOS transistor Tr501 has a gate high voltage VGH output from the drain terminal of the PMOS transistor 502 or a gate low voltage VGL output from the drain terminal of the second NMOS transistor Tr503. And a gate terminal to which the gate high voltage VGH from the DC-DC converter 216 is applied, and a source terminal connected to the gate line GL.

The scan pulse voltage output from the gate driver 214 is applied to the gate line GL. The scan pulse voltage includes the gate high voltage VGH and the gate low voltage VGL. That is, the gate driver 214 receives the gate high voltage VGH and the gate low voltage VGL from the DC-DC converter 216, and the gate driver 216 receives the gate driver 216 from the timing controller 212. The selected gate line GL is driven by selecting a specific gate line GL in response to a control signal and outputting a gate high voltage VGH to the selected gate line GL. The gate driver 214 supplies the gate low voltage VGL to the remaining gate lines GL except for the selected gate line GL.

More specifically, the gate driver 214 sequentially selects the gate lines GL, and sequentially supplies the gate high voltage VGH to the selected gate line GL. Therefore, the gate high voltage VGH is sequentially supplied to the gate lines GL in time. In this case, as described above, the gate low voltage VGL is supplied to the remaining gate lines GL to which the gate high voltage VGH is not applied.

Hereinafter, the driving of the liquid crystal display according to the exemplary embodiment of the present invention configured as described above will be described in detail.

First, when a user presses a power switch of a liquid crystal display (for example, a monitor such as a monitor) to turn on the liquid crystal display, the power supply voltage VCC having a predetermined voltage magnitude from the system 210 is DC-DC. Applied to the converter 216 and the discharge portion 215. In general, the voltage magnitude of the power supply voltage VCC is 3.3V.

Then, the DC-DC converter 216 boosts or reduces the power voltage VCC applied to the DC-DC converter 216 and outputs various driving voltages including the gate high voltage VGH and the gate low voltage VGL. In particular, the gate high voltage VGH and the gate low voltage VGL output from the DC-DC converter 216 are input to the gate driver 214 and the discharge unit 215.

Then, the gate driver 214 generates a scan pulse voltage by switching the gate high voltage VGH and the gate low voltage VGL through PWM, and sequentially supply them to the gate lines GL, thereby supplying the gate line GL. ) Will be driven sequentially. In other words, the gate driver 214 sequentially supplies the gate high voltage VGH to the gate lines GL, while the gate driver 214 supplies the gate high voltage VGH to any one gate line GL. The gate low voltage VGL is supplied to the GLs so that only one gate line GL is driven at a time.

In this case, an image is displayed on pixels of one horizontal line arranged along the gate line GL to which the gate high voltage VGH is applied.

On the other hand, the discharge unit 215 receiving the power supply voltage VCC from the system 210 operates as follows.

That is, as described above, when the liquid crystal display is turned on, the power supply voltage VCC has a predetermined voltage level and is applied to the discharge unit 215. In this case, the power supply voltage VCC is applied to the discharge unit ( 215 is simultaneously applied to the gate terminal of the PMOS transistor Tr502 and the gate terminal of the second NMOS transistor Tr503. Then, the PMOS transistor 502 is turned off in response to the power supply voltage VCC having the predetermined magnitude, specifically, the voltage magnitude of positive polarity, while the second NMOS is responded to in response to the power supply voltage VCC. Transistor Tr503 is turned on. Then, the gate low voltage VGL is applied to the gate terminal of the first NMOS transistor Tr501 via the source terminal and the drain terminal of the turned-on second NMOS transistor Tr503. In this case, since the gate low voltage VGL is a negative polarity voltage, the first NMOS transistor Tr501 is turned off.

In summary, when the liquid crystal display is turned on, an image is displayed on the liquid crystal panel 217, and the discharge unit 215 does not supply any voltage to the gate line GL. That is, in the normal driving state in which the liquid crystal display is turned on and an image is displayed on the liquid crystal panel 217, the discharge unit 215 may be connected to the gate line GL so as not to interfere with the normal driving of the liquid crystal display. It does not supply any voltage. This is because the first NMOS transistor Tr501 included in the discharge unit 215 is turned off.

Meanwhile, when the user turns off the LCD by pressing the power button again, the operation of the LCD according to an exemplary embodiment of the present invention will be described in detail.

FIG. 6 is a view illustrating a time point in which the power supply voltage, the gate high voltage, and the gate low voltage each fall to the ground voltage when the liquid crystal display is turned off, and FIG. 7 is an afterimage of the present invention when the liquid crystal display is turned off. It is a figure for demonstrating the principle which can reduce an effect further.

When the user presses the power button again while the liquid crystal display is normally driven, the supply of the power supply voltage VCC from the system 210 is cut off. This, in turn, means that the voltage of the power supply voltage VCC drops to a voltage (ground voltage) of 0 [V]. Thus, the liquid crystal display device is turned off.

Here, as the power supply voltage VCC is cut off, the gate high voltage VGH and the gate low voltage VGL generated by being stepped up or down from the power supply voltage VCC also fall to a voltage of 0 [V]. In this case, as shown in FIG. 6, the power supply voltage VCC first drops to a voltage of 0 [V], a gate low voltage VGL drops to 0 [V], and finally a gate high voltage VGH. ) Drops to 0 [V].

As such, when the power supply voltage VCC falls to 0 [V], the gate low voltage VGL is applied to all the gate lines GL except for any one gate line GL of the liquid crystal panel 217. The gate low voltage VGL is charged in the storage capacitor Cst of almost all of the pixels included in the liquid crystal panel since the voltage is applied.

In the related art, the gate low voltage VGL is gradually discharged by the leakage voltage of the thin film transistor TFT provided in each pixel, which causes a long discharge time.

However, in the present invention, when the liquid crystal display is turned off, the discharge unit 215 operates as follows, thereby quickly discharging the gate low voltage VGL charged in the gate line GL.

That is, the power supply voltage VCC, that is, the power supply voltage VCC having a magnitude of 0 [V], is the gate terminal of the PMOS transistor Tr502 and the gate of the second NMOS transistor Tr503 provided in the discharge unit 215. When applied to a terminal, the second NMOS transistor Tr503 is turned off, and conversely, the PMOS transistor Tr502 is turned on.

Then, the gate high voltage VGH is applied to the gate terminal of the first NMOS transistor Tr501 via the drain terminal and the source terminal of the turned-on PMOS transistor 502, whereby the first NMOS transistor Tr501. ) Is turned on. Then, the gate high voltage VGH is applied to the gate line GL via the drain terminal and the source terminal of the turned-on first NMOS transistor Tr501. On the other hand, as described above, the gate high voltage (VGH) maintains its size for a predetermined time after the power supply voltage (VCC) falls to 0 [V], the same as the power supply voltage (VCC) to 0 [V] Will fall. Therefore, the gate high voltage VGH applied to the gate line GL is maintained at a predetermined voltage 15 [V] only for a predetermined period.

In other words, the gate high voltage VGH applied to the gate line at the moment the liquid crystal display is turned off, that is, the gate high voltage VGH output from the source terminal of the first NMOS transistor Tr501, has a predetermined amplitude and a predetermined pulse. It functions as a pulse voltage having a width, the pulse voltage having an amplitude equal to the amplitude of the gate high voltage VGH. In addition, the pulse width of the pulse voltage, as shown in Figure 6, the time when the power supply voltage (VCC) reaches the ground voltage (GND; voltage of 0 [V]) and the gate high voltage (VGH) the ground voltage Corresponds to the period T0 between the points of time reaching (GND; voltage of 0 [V]). In conclusion, the gate high voltage VGH applied to the gate line GL at the moment when the liquid crystal display is turned off is a pulse voltage maintained for a period T0 corresponding to the pulse width at an amplitude of its own size.

As a result, as shown in FIG. 7, when the power supply voltage VCC falls to a voltage of 0 [V], the voltage of the gate line GL is controlled by the gate high voltage VGH supplied by the gate low voltage (VGH). VGL) is instantaneously increased to the gate high voltage VGH, and the gate high voltage VGH falls to 0 [V] together in synchronization with a falling time of falling to 0 [V]. In the present invention, the gate line GL can be maintained at 0 [V] in a shorter time. That is, the gate line GL can be discharged in a faster time. That is, as shown in FIG. 7, the gate line GL is completely maintained at the ground voltage GND only after a time corresponding to the T2 period, but in the present invention, the gate line GL corresponds to the T1 period. Over time, it remains fully at ground voltage (GND). This is because the gate low voltage VGL applied to the gate line GL is rapidly increased toward 0 [V] by the gate high voltage VGH.

On the other hand, it is preferable that one discharge unit 215 is provided in each gate line GL. In this way, it is possible to quickly discharge all the gate lines GL at the same time as the liquid crystal display is turned off.

Hereinafter, a liquid crystal display according to a second embodiment of the present invention will be described in detail with reference to the accompanying drawings.

8 is a second configuration diagram of the discharge unit of FIG. 1.

The liquid crystal display device according to the second embodiment of the present invention is the same as that of the first embodiment, except that the structure of the discharge portion is different as follows.

That is, as shown in FIG. 8, the discharge unit 815 of the liquid crystal display according to the second embodiment of the present invention may have a gate high voltage VGH or a gate low voltage (VG) according to the magnitude of the power supply voltage VCC. An inverter 888 for outputting a VGL, and is turned off in response to a gate low voltage VGL from the inverter 888, and turned on in response to a gate high voltage VGH from the inverter 888 to ground. A first NMOS transistor Tr801 is applied to apply the voltage GND to the gate line GL. That is, in the second embodiment, the drain terminal of the first NMOS transistor Tr801 is grounded.

The inverter 888 may include a PMOS transistor T802 having a gate terminal to which the power supply voltage VCC is applied, a source terminal to which a gate high voltage VGH from the DC-DC converter 216 is applied, and A gate terminal connected to the gate terminal of the PMOS transistor Tr802, a source terminal connected to the drain terminal of the PMOS transistor Tr802, and a gate low voltage VGL output from the DC-DC converter 216 are applied. And a second NMOS transistor Tr803 having a drain terminal. The first NMOS transistor Tr801 may have a gate high voltage VGH output from the drain terminal of the PMOS transistor Tr802 or a gate low voltage VGL output from the drain terminal of the second NMOS transistor Tr803. And a gate terminal to which the gate high voltage VGH from the DC-DC converter 216 is applied, and a source terminal connected to the gate line GL.

As described above, the discharge unit 815 configured as described above applies a ground voltage GND, that is, a voltage of 0 [V], to each gate line GL when the LCD is turned off. Since the ground voltage GND also has a larger voltage value than the gate low voltage VGL applied to the gate line GL, the gate line GL may be discharged at a higher speed than in the related art.

Of course, as described above, it is preferable that one discharge unit 815 is provided at each gate line GL. By doing so, it is possible to quickly discharge all the gate lines GL at the same time as the liquid crystal display is turned off. have.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the liquid crystal display device and the driving method thereof according to the present invention have the following effects.

In the present invention, when the liquid crystal display is turned off, the gate line can be discharged at a high speed by applying a pulse voltage higher than the gate low voltage previously charged to each gate line of the liquid crystal panel.

Therefore, when the liquid crystal display is turned off, the afterimage on the screen may be prevented.

Claims (11)

A liquid crystal panel having a plurality of pixels defined by a plurality of gate lines and data lines perpendicular to each other; A storage capacitor formed between the pixel electrode of each pixel and the gate line; A gate driver sequentially driving the gate lines by sequentially supplying a scan pulse voltage having a gate high voltage and a gate low voltage to gate lines of the liquid crystal panel; And According to a power supply voltage for operating the liquid crystal panel, by supplying a pulse voltage to the gate line instantaneously so that the voltage of the gate line to reach the ground voltage, including a discharge unit for discharging the storage capacitor capacitor to ground voltage Liquid crystal display, characterized in that configured. The method of claim 1, The amplitude of the pulse voltage output from the discharge unit is equal to the amplitude of the gate high voltage, and the pulse width of the pulse voltage is between the time point at which the power supply voltage reaches the ground voltage and the time point at which the gate high voltage reaches the ground voltage. Liquid crystal display device, characterized in that corresponding to the width. The method of claim 1, The discharge unit may include an inverter for selectively outputting the gate low voltage and the pulse voltage according to the magnitude of the power supply voltage; And, And a first switching device for applying the pulse voltage to the gate line in response to an output from the inverter. The method of claim 3, wherein When the applied power supply voltage drops to zero voltage, the inverter outputs the pulse voltage in response to the power supply voltage and applies the same to the gate terminal of the first switching device to turn on the first switching device. A second switching element; And, When the applied power supply voltage is maintained at a predetermined voltage, outputting the gate low voltage in response to the power supply voltage and applying the same to the gate terminal of the first switching device to turn off the first switching device. 3. A liquid crystal display comprising a switching element. The method of claim 1, And the amplitude of the pulse voltage output from the discharge unit is the same as the amplitude of the ground voltage. The method of claim 1, The discharge unit may include an inverter for selectively outputting the gate low voltage and the pulse voltage according to the magnitude of the power supply voltage; And, And a first switching element applying the ground voltage to the gate line in response to an output from the inverter. The method of claim 1, The DC-DC converter is further configured to generate various driving voltages including the gate high voltage and the gate low voltage by receiving the power supply voltage and boosting or reducing the voltage, and supplying the gate high voltage and the gate low voltage to the gate driver and the discharge unit. Liquid crystal display device comprising a. The method of claim 1, Each pixel includes a pair of pixel electrodes and a common electrode for displaying an image; A liquid crystal capacitor formed using a liquid crystal formed between the pixel electrode and the common electrode as a dielectric; A thin film transistor applying a data voltage from a data line to the pixel electrode in response to a scan pulse from the gate line; And, And a storage capacitor formed on an overlapping portion of a gate line for driving another pixel adjacent to the pixel and a pixel electrode provided therein. A liquid crystal panel having a plurality of pixels defined by a plurality of gate lines and data lines perpendicular to each other, a storage capacitor formed between the pixel electrode and the gate line of each pixel, and a gate high voltage and a gate low voltage A driving method of a liquid crystal display device including a gate driver sequentially driving a gate line by sequentially supplying a scan pulse voltage to gate lines of the liquid crystal panel. According to a power supply voltage for operating the liquid crystal panel, by supplying a pulse voltage to the gate line instantaneously so that the voltage of the gate line to reach the ground voltage, characterized in that to discharge the storage capacitor capacitor to ground voltage Driving method of liquid crystal display device. The method of claim 9, The amplitude of the pulse voltage is equal to the amplitude of the gate high voltage, the pulse width of the pulse voltage corresponds to the width between the time when the power supply voltage reaches the ground voltage and the time when the gate high voltage reaches the ground voltage. A method of driving a liquid crystal display device. The method of claim 9, And the amplitude of the pulse voltage is the same as the amplitude of the ground voltage.

Images