JP2007212688A - Liquid crystal display element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal panel in which occurrence of an image remaining after interruption of power supply is prevented. <P>SOLUTION: A signal is generated with a signal generating means 22 when a voltage drop on interruption of the power supply is detected with a voltage drop detecting means 20. A common electrode, a storage capacitor, and a signal line are respectively made to be at the same electric potential by an initializing means 23 based on the signal, and at the same time, electric charges of the common electrode and the storage capacitor are compulsorily discharged to the ground with a discharge means 24. The occurrence of the image remaining after interruption of the power supply is prevented because the electric charges held by a liquid crystal capacitor and the storage capacitor of each pixel are certainly discharged without producing an electric potential difference between the common electrode and the storage capacitor and the signal line. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device including a storage capacitor electrically connected to a pixel electrode, and a common electrode disposed to face the pixel electrode with a liquid crystal layer interposed therebetween.

  2. Description of the Related Art Conventionally, liquid crystal display devices use liquid crystal display elements, and have characteristics such as light weight, thinness, and low power consumption. Therefore, they are used in various fields such as OA equipment, information terminal devices, watches, and televisions. ing. In particular, among liquid crystal display devices, liquid crystal display devices using thin film transistor (TFT) elements are excellent in responsiveness, so that many display devices such as mobile phones, televisions, computers, etc. It is used.

  As such a liquid crystal display element, there is an active matrix type having a display region in which pixels driven by thin film transistors are formed in a matrix. In this liquid crystal display element, an array substrate and a counter substrate are arranged to face each other, and a liquid crystal layer is interposed between the substrates.

  In the display region, scanning lines electrically connected to the gate driver and signal lines electrically connected to the source driver are arranged in a lattice pattern between the pixels. Near the intersection with the signal line, a thin film transistor and a storage capacitor electrically connected to the scanning line and the signal line are disposed. Further, the pixel is configured such that a liquid crystal layer is located between a pixel electrode disposed on the array substrate side and a common substrate disposed on the counter substrate side.

  Then, based on the scanning line driving signal input to the gate driver and the signal line driving signal input to the source driver, the thin film transistor located in the vicinity of the intersection of the scanning line and the signal line is turned on / off. By changing the voltage applied to the pixel electrode of each pixel, the display state of each pixel changes.

  However, in such a liquid crystal display element, after the power source is shut off, charges remain in the storage capacitor and the liquid crystal capacitor, so that an image displayed by the pixel until immediately before the power source is shut off may be displayed as an afterimage. There is.

Therefore, in order to discharge the charges charged in the storage capacitor and the liquid crystal capacitor, when the power supply is shut off, the common electrode potential that is the potential of the common electrode electrically connected to the liquid crystal capacitor, the storage capacitor potential, A configuration in which the signal line potential is set to the same potential is known (for example, see Patent Document 1).
JP-A-11-271707

  However, in the above-described liquid crystal display element, after the power supply is cut off, the signal line potential passes through the source driver to the earth, that is, the ground relatively quickly, whereas the common electrode potential and the storage capacitor potential are Since it takes time to discharge to the ground due to the influence of a large-capacitance capacitor mounted as a countermeasure against coupling to the signal line or scanning line, a potential difference occurs for a moment after discharging the charge, and an afterimage occurs due to this potential difference. Has the problem.

  In general, after the power supply is cut off, the analog power supply of the drive circuit is immediately discharged, so that it is not easy to control the circuit, and a liquid crystal display element is incorporated in the control of such a circuit. It was necessary to input a signal to notify power shutdown from the device body.

  The present invention has been made in view of these points, and an object of the present invention is to provide a liquid crystal display element that prevents an afterimage after power-off.

  The present invention relates to a plurality of signal lines and a plurality of scanning lines arranged in an intersecting manner, a pixel electrode provided at each intersection of the signal lines and the scanning lines, and a drive signal supplied to the scanning lines. A switching element that is controlled to drive the pixel electrode, a storage capacitor electrically connected to the pixel electrode, and a common electrode disposed to face the pixel electrode through a liquid crystal layer A liquid crystal display element, a voltage drop detecting means for detecting a voltage drop when the power is cut off, a signal generating means for generating a signal when the voltage drop is detected by the voltage drop detecting means, and a signal generating means The common electrode, the storage capacitor, and the signal line are set to the same potential based on the generated signal, and the common electrode and the storage line are set based on the signal generated by the signal generation unit. It is obtained by and a discharge means for discharging to the ground the electric charge of the capacitor.

  Then, based on the signal generated by the signal generation means when the voltage drop at the time of power interruption is detected by the voltage drop detection means, the initialization means sets the common electrode, the storage capacitor, and the signal line to the same potential, The discharging means forcibly discharges the charges of the common electrode and the storage capacitor to the ground.

  According to the present invention, since the charge held in each pixel can be reliably discharged without causing a potential difference with the signal line, an afterimage after the power is shut off can be prevented.

  Hereinafter, a configuration of a liquid crystal display element according to an embodiment of the present invention will be described with reference to the drawings.

  3 and 4, reference numeral 1 denotes a liquid crystal panel as a liquid crystal display element. The liquid crystal panel 1 is, for example, driven by HV inversion driving (dot inversion driving) or capacitively coupled driving (line inversion driving). A substrate 2 and a counter substrate 3 are arranged to face each other, and a liquid crystal layer (not shown) is filled between the substrates 2 and 3, and pixels 6 are arranged in a square display area 5 in a matrix form. A plurality of gate drivers 7 serving as scanning line driving ICs are disposed along one side of the display area, and a plurality of source drivers 8 serving as signal line driving ICs are disposed along one end of the display area 5. .

  The array substrate 2 includes a scanning line 11 electrically connected to the gate driver 7 and a signal line 12 electrically connected to the source driver 8 on a glass substrate as a light-transmitting insulating substrate. A thin film transistor as a switching element corresponding to the liquid crystal capacitor 13 of the pixel 6 is arranged near the intersection of the scanning line 11 and the signal line 12 as shown in FIG. 14 and the storage capacitor 15 are electrically connected to each other.

  The array substrate 2 is formed with a pixel electrode 16, which is a transparent electrode formed of, for example, ITO on the glass substrate so as to cover the thin film transistor 14 and the storage capacitor 15, and is not shown on the pixel electrode 16. An alignment film is formed.

  The counter substrate 3 is provided with a color filter (not shown) corresponding to, for example, red (R), green (G), and blue (B) for each pixel 6 on a glass substrate as a light-transmitting insulating substrate. On the color filter, a common electrode 18 which is a transparent electrode made of, for example, ITO is formed, and an alignment film (not shown) is formed on the common electrode 18.

  The gate driver 7 is supplied with a positive voltage (VDD) and a negative voltage (VSS) and a digital voltage (DVDD) corresponding to the digital gradation data of each pixel 6 as a drive voltage. The operation is controlled by a gate driver control signal (XDON), and a scanning line drive signal (GS) output from a drawing engine of a PC (not shown) or the like is input in accordance with image data to be displayed.

  The source driver 8 is supplied with an analog voltage (AVDD), a digital voltage (DVDD), and a reference voltage (VREF) corresponding to the digital gradation data of each pixel 6 as drive voltages, and depends on image data to be displayed. A signal line drive signal (SS) output from a drawing engine of a PC (not shown) is input.

  Next, the circuit configuration of the above embodiment will be described.

  As shown in FIG. 1, a voltage drop detecting means 20 (hereinafter simply referred to as a voltage drop detecting means 20) for detecting a voltage drop of the power supply P with respect to a power supply P that supplies a power supply voltage (POWER) to the liquid crystal panel 1 (FIG. 3). The detection means 20 is electrically connected to each of the charge storage means 21, the signal generation means 22, the initialization means 23, and the discharge means 24 that is a common electrode potential discharge means. Electrically connected.

  Specifically, as shown in FIG. 2, the detecting means 20 includes a resistor 26 to which a digital voltage (DVDD) is supplied, and a reset IC 27 as a control signal output means having an output terminal electrically connected to the resistor 26. And have.

  The reset IC 27 outputs a reset signal (RST) that is an initialization pulse signal when the input voltage from the power supply P is equal to or lower than a predetermined value set in advance, and the gate of the MOSFET 31 as a switching element is output to the output terminal. The electrode, the gate electrode of the MOSOFET 32 as a switching element, and the signal generating means 22 are electrically connected in parallel with the resistor 26.

  The MOSFET 31 is, for example, an n-type, the source electrode is grounded, the resistor 34 is supplied with a positive side voltage (VDD) to the drain electrode, the gate electrode of the MOSFET 35 as a switching element, and the switch unit 37, the switch unit 38, and the discharge means 24 are electrically connected in parallel. From the drain electrode, initialization for selecting the operation of the MOSFET 35, the switch unit 36, the switch unit 37, the switch unit 38, and the discharge unit 24 is performed. A selection signal (SELECT) as a signal is output.

  The MOSFET 35 is, for example, an n-type, and includes a resistor 41 whose source electrode is grounded and a positive voltage (VDD) is supplied to the drain electrode, a gate electrode of the MOSFET 42 serving as a switching element as a switch unit, and a switch The gate electrode of the MOSFET 43 which is a switching element as a unit is electrically connected in parallel. From the drain electrode, the selection signal (/ SELECT) for selecting the operation of the MOSFETs 42 and 43 is in phase opposite to the selection signal (SELECT). ) Is output. That is, the MOSFETs 42 and 43 are controlled by the selection signal (/ SELECT) so as to perform the reverse operation of the switch units 36, 37, and 38 and the discharging means 24.

  The MOSFET 42 is, for example, an n-type, and the source electrode is electrically connected to the switch unit 36, the drain electrode is electrically connected to the reference voltage input unit V1, and the input common electrode voltage (VCOM_IN) is Have been supplied.

  The MOSFET 43 is of an n-type, for example, and the source electrode is electrically connected to the switch unit 36, the drain electrode is electrically connected to the common electrode voltage input unit V2, and the input reference voltage (VP_IN) is Have been supplied.

  In the switch unit 36, for example, the drain electrodes of n-type MOSFETs 44 and 45 as switching elements are electrically connected to each other, and the gate electrodes of these MOSFETs 44 and 45 are electrically connected to the drain electrode of the MOSFET 31, The source electrode of the MOSFET 44 is electrically connected to the source electrode of the MOSFET 42, and the source electrode of the MOSFET 45 is electrically connected to the source electrode of the MOSFET 43.

  On the other hand, in the switch unit 37, for example, the drain electrodes of n-type MOSFETs 47 and 48 as switching elements are electrically connected to each other, and the gate electrodes of these MOSFETs 47 and 48 are electrically connected to the drain electrode of the MOSFET 31. At the same time, the source electrode of the MOSFET 47 is electrically connected to the source electrode of the MOSFET 44, and the source electrode of the MOSFET 48 is electrically connected to the voltage divider 49.

  Here, the voltage divider 49 divides the supplied analog voltage (AVDD). For example, a series circuit of resistors 51 and 52 having the same resistance value is formed between the resistors 51 and 52. The gap is electrically connected to the source electrode of the MOSFET 48 of the switch unit 37 and the operational amplifier circuit 54. Therefore, the voltage dividing unit 49 is configured to output a voltage half the analog voltage as the voltage dividing unit output voltage (AVDD / 2).

  The operational amplifier circuit 54 includes, for example, four amplifiers 56a, 56b, 56c, and 56d such as operational amplifiers, and an amplifier IC 56 as an arithmetic unit to which an analog voltage (AVDD) is supplied, and different output terminals of the amplifier IC 56 And resistors 57 and 58 connected in series with each other.

  In the amplifying unit 56a, the source electrode of the MOSFET 42 and the source electrode of the MOSFET 48 of the switch unit 37 are electrically connected to the plus input terminal, respectively, the output terminal is the minus input terminal, the resistor 57, and the reference voltage circuit 61. And is electrically connected.

  In the amplifying unit 56b, the resistors 51 and 52 of the voltage dividing unit 49 are electrically connected to the positive input terminal, the resistors 57 and 58 are electrically connected to the negative input terminal, and the output terminal is a resistor. 57 and the reference voltage circuit 61 are electrically connected in parallel.

  Here, the reference voltage circuit 61 generates reference voltages (VREF0, VREF1,..., VREF (n−1), VREFn) of the source driver 8 (FIG. 3), and a plurality of terminals have resistors 63 and capacitors. The positive side is electrically connected to the output terminal of the amplifying unit 56a, and the negative side is electrically connected to the output terminal of the amplifying unit 56b. Therefore, the plus side potential (VP) of the source driver 8 (FIG. 3) which is the plus side potential of the reference voltage circuit 61 is set equal to the input reference voltage (VP_IN) by the amplifier 56a. The minus side potential (VN) of the source driver 8 (FIG. 3), which is a minus side potential, is a differential voltage between twice the divided voltage output voltage (AVDD / 2) and the plus side potential (VP) by the amplifier 56b. It is set to (2 × (AVDD / 2) −VP).

  Further, in the amplifying unit 56c, the source electrode of the MOSFET 43 and the source electrode of the MOSFET 45 of the switch unit 36 are electrically connected to the negative input terminal, and the output terminal is electrically connected to the positive input terminal and the common electrode 18. The common electrode line L1 to be connected and the switch unit 38 are electrically connected. The common electrode line L1 is electrically connected with a large-capacitance capacitor 66 as a countermeasure against coupling to the ground, and the discharge means 24 is electrically connected to the common electrode 18 side of the capacitor 66. It is connected to the.

  The resistors 57 and 58 are set to have the same resistance values as the resistors 51 and 52 of the voltage dividing section 49, respectively.

  The switch unit 38 includes a MOSFET 67 as a switching element and a resistor 68 electrically connected to the source electrode of the MOSFET 67.

  The MOSFET 67 is, for example, of the n-type, and the drain electrode is electrically connected to the output terminal of the amplification unit 56c of the amplification IC 56 of the operational amplifier circuit 54. The drain electrode of the MOSFET 31 and the gate electrode of the MOSFET 35 are connected to the gate electrodes. And the gate electrode of the MOSFET 44 of the switch unit 36 are electrically connected in parallel.

  The resistor 68 is electrically connected to the storage capacitor line L2 that is electrically connected to each storage capacitor 15 and the drain electrode of the MOSFET 71 serving as a switch unit. The MOSFET 71 is, for example, an n-type, and the source electrode is electrically connected to the storage capacitor voltage input unit V3 to be supplied with the input storage capacitor voltage (VCST_IN), and the positive voltage ( A resistor 73 to which (VDD) is supplied and a drain electrode of a MOSFET 74 as a switching element are electrically connected in parallel.

  Here, the MOSFET 74 is of a p-type, for example, and a positive voltage (VDD) and a negative voltage (VSS) are supplied to the source electrode, and a negative voltage (VSS) is supplied to the gate electrode. The resistor 76 and the drain electrode of the MOSFET 32 are electrically connected in parallel, and a reset signal (NRST) is output from the drain electrode to the gate electrode of the MOSFET 71.

  The MOSFET 32 is, for example, a p-type, and the gate electrode is electrically connected to the output terminal of the reset IC 27 of the detecting means 20 to be supplied with a reset signal (RST). The means 21 and the signal generating means 22 are electrically connected in parallel to output a reset signal (RST) having a phase opposite to that of the reset signal (RST) from the drain electrode to the gate electrode of the MOSFET 74.

  The charge accumulating means 21 holds the charge for a predetermined time when the input voltage from the power source P is lower than the predetermined value, that is, delays the timing of the decrease of the digital voltage (DVDD), and uses the delayed delay voltage (DVDD_DELAY). The signal generating means 22 is supplied to drive the signal generating means 22, and a diode 83 as a rectifying element to which a digital voltage (DVDD) is supplied to the anode side, and between the cathode side of the diode 83 and the ground And a capacitor 84 as a holding element electrically connected to the capacitor 83, and the source electrode of the MOSFET 32 is electrically connected between the diode 83 and the capacitor 84.

  The diode 83 is a protective element that prevents current from flowing to the power supply P side.

  The signal generation means 22 is turned on by the initialization pulse signal output from the reset IC 27, and generates a signal for controlling on / off of the gate electrodes of all the gate drivers 7. The gate electrode is connected to the output terminal of the reset IC 27. MOSFET 86 as a switching element electrically connected to each other, and a resistor 87 electrically connected between the drain electrode of MOSFET 86 and the source electrode of MOSFET 32.

  The MOSFET 86 is, for example, an n-type, and when the source electrode is grounded and the reset signal (RST) output from the reset IC 27 is an H level output, the gate driver control signal (XDON) is output as an L level output. When the gate driver 7 is normally operated and the reset signal (RST) output from the reset IC 27 is an L level output, the gate driver control signal (XDON) is output as an all-on signal that is an H level output, The gate electrodes of all the thin film transistors 14 are turned on via the gate driver 7.

  The MOSFET 86 and the resistor 87 are electrically connected to the gate electrode of the gate driver 7 (FIG. 3).

  When the power supply voltage (POWER) decreases, the initialization unit 23 performs common electrode potential (VCOM) that is the liquid crystal capacitance potential of the pixel 6 (FIG. 4) and positive side potential (VP) of the source driver 8 that is the signal line potential. The negative potential (VN) and the holding capacitance potential (VCST) are set to the same potential, and are composed of a switch unit 36, a switch unit 37, a switch unit 38, and MOSFETs 42, 43, 71. Yes.

  The discharge means 24 is for forcibly discharging the common electrode potential (VCOM) and the retention capacitance potential (VCST) to the ground by grounding the common electrode line L1 and the retention capacitance line L2. MOSFET 91 as a transistor which is a switching element electrically connected to the drain electrode of MOSFET 31, and a resistor 92 electrically connected between the drain electrode of MOSFET 91 and the common electrode line L1 .

  The MOSFET 91 is, for example, an n-type, and its source electrode is grounded, and its operation is controlled by a selection signal (SELECT) output from the MOSFET 31. This selection signal (SELECT) is generated so as to have a sufficient amplitude with respect to the threshold voltage of the MOSFET 91 in particular.

  Further, the resistor 92 limits the current at the time of discharging in the discharging means 24 by the resistance value, and in this embodiment, discharging of the positive potential (VP) and the negative potential (VN) shown in FIG. The resistance value is set so that the slope at the time of discharge of the common electrode potential (VCOM) and the storage capacitor potential (VCST) matches the slope at the time.

  Next, the operation of the above embodiment will be described.

  As shown in FIG. 5, when the power supply P is on, for example, a voltage of 5V is supplied as the power supply voltage (POWER). At this time, for example, the digital voltage (DVDD) is 3.3V, and the positive voltage (VDD) is 24V and -6V are supplied as the negative side voltage (VSS), respectively.

  At this time, since the reset IC 27 does not detect a drop in the power supply voltage (POWER), an H level output of 3.3 V is output as the reset signal (RST) from the reset IC 27.

  The MOSFET 31 is turned on by the reset signal (RST) from the reset IC 27, and the switch portions 36, 37, and 38 and the MOSFET 91 of the discharging means 24 are turned off by the selection signal (SELECT) that is the ground potential (GND), that is, the L level output. In addition, the positive side voltage (VDD) is supplied to the gate electrodes of the MOSFETs 42 and 43 as the selection signal (/ SELECT), so that the MOSFETs 42 and 43 are turned on.

  Further, the MOSFET 32 is turned off by the reset signal (RST) from the reset IC 27 and the negative side voltage (VSS) is supplied to the gate electrode of the MOSFET 74 as the reset signal (/ RST), whereby the MOSFET 74 is turned off and the positive side voltage ( VDD) is supplied as a reset signal (NRST) to the gate electrode of the MOSFET 71, and the MOSFET 71 is turned on.

  Further, when the MOSFET 86 is turned on by the reset signal (RST) from the reset IC 27, the gate driver control signal (XDON) becomes the same potential as the ground potential (GND), that is, an L level output and is output to the gate driver 7. Is done.

  As a result, the input reference voltage (VP_IN) input from the reference voltage input unit V1 is supplied to the plus side of the reference voltage circuit 61 through the amplifying unit 56a to become the plus side potential (VP), and the common electrode voltage input The input common electrode voltage (VCOM_IN) input from the unit V2 is supplied as the common electrode potential (VCOM) to the common electrode 18 through the common electrode line L1 through the amplifier unit 56c, and the storage capacitor line L2 has a storage capacitor. The input storage capacitor voltage (VCST_IN) input from the voltage input unit V3 is supplied as a storage capacitor potential (VCST) via the storage capacitor line L2.

  Further, on the negative side of the reference voltage circuit 61, a differential voltage (2 × (AVDD /) between the input reference voltage (VP_IN) and twice the divided voltage output voltage (AVDD / 2) output from the voltage divider 49 is provided. 2) -VP) is supplied and becomes a negative potential (VN).

  Then, the reference voltages (VREF0, VREF1,...) Divided by the resistors 63 of the reference voltage circuit 61 are supplied to the source driver 8 (FIG. 3) according to a plurality of digital gradation data of the pixel 6 (FIG. 4). Supplied.

  As a result, as shown in FIG. 3, the gate driver 7 and the source driver 8 convert the scanning line drive signal (GS) and the signal line drive signal (SS) through the scanning line 11 and the signal line 12 into the thin film transistor 14 (FIG. 4). And each pixel 6 (FIG. 4) is driven to have a predetermined gradation.

  On the other hand, when the power source P is shut off, that is, turned off, the power source voltage (POWER) and the digital voltage (DVDD) gradually decrease.

  At this time, by holding the charge of the digital voltage (DVDD) by the capacitor 84, the charge storage means 21 generates a delay voltage (DVDD_DELAY) whose drop is delayed.

  In the reset IC 27, when the power supply voltage (POWER) becomes lower than a predetermined voltage set in advance, the reset signal (RST) becomes an L level output.

  For this reason, when the reset signal (RST) is supplied to the gate electrode, the MOSFET 31 is turned off, so that the positive voltage (VDD) gradually decreasing to the ground potential (GND) is changed to the switch units 36, 37, 38 are supplied as selection signals (SELECT), the MOSFETs 44, 45, 47, 48, and 67 of the switch sections 36, 37, and 38 are turned on, and the selection signal (/ SELECT) is set to the ground potential (GND). The MOSFETs 42 and 43 are turned off when they are equal, that is, the L level output, and further, the MOSFET 32 is turned off by the reset signal (RST), and the negative voltage (VSS) gradually rising to the ground potential (GND) is selected. (/ RST) is supplied to the gate electrode of the MOSFET 74 to turn on the MOSFET 74, and the negative voltage (VS ) This MOSFET71 is turned off is supplied to the gate electrode of the MOSFET71 as a reset signal (NRST).

  That is, when the MOSFETs 47 and 48 of the switch unit 37 are turned on, the input reference voltage (VP_IN) input to the amplifying unit 56a and the input common electrode voltage (VCOM_IN) input to the amplifying unit 56c become the resistance of the voltage dividing unit 49. Since the same potential as that between 51 and 52, in other words, equal to the output voltage of the voltage dividing section (AVDD / 2), the common electrode potential (VCOM) and the positive potential (VP) of the source driver 8 (FIG. 3) Each is equal to the voltage divider output voltage (AVDD / 2), and the negative potential (VN) of the source driver 8 (FIG. 3) obtained by 2 × (AVDD / 2) −VP is also the voltage divider output voltage (AVDD). / 2), and further, when the MOSFET 67 of the switch unit 38 is turned on, the storage capacitor potential (VCST) also becomes the divided voltage output voltage (AVDD / 2) equal to the common electrode potential (VCOM).

  In this state, the MOSFET 86 is turned off by the reset signal (RST) from the reset IC 27, so that the delay voltage (DVDD_DELAY) becomes an H level output of the gate driver control signal (XDON) and is output to the gate driver 7. Through these gate drivers 7, the gate electrodes of the thin film transistors 14 corresponding to all the pixels 6 (FIG. 4) are opened.

  Then, each potential (VP, VN) of the source driver 8 (FIG. 3) is discharged to the ground.

  Further, the common electrode potential (VCOM) and the storage capacitor potential (VCST) are selected when the positive voltage (VDD) is supplied to the gate electrode of the MOSFET 91 of the discharging means 24 and the MOSFET 91 is turned on. While SELECT is at the H level output, it is discharged to ground through resistor 92.

  As described above, in the above-described embodiment, the initialization unit 23 includes the common electrode 18 and the storage capacitor based on the signal generated by the signal generation unit 22 when the voltage drop at the time of power-off is detected by the detection unit 20. 15 and the signal line 12 are set to the same potential, and the discharging means 24 forcibly discharges the charges of the common electrode 18 and the storage capacitor 15 to the ground.

  That is, the electric potential of each of the common electrode potential (VCOM) and the holding capacitance potential (VCST) is held by the large-capacitance capacitor 66 as a countermeasure against coupling, so that the discharge speed is reduced. The rate of discharge is slower than the rate at which the plus potential (VP) and minus potential (VN), which are signal line potentials, are discharged to ground, and an instantaneous potential difference occurs during this discharge. May cause an afterimage for a moment, that is, an image pattern related to the image displayed on the pixel 6 until immediately before may be formed in the display area 5, so that the initialization means 23 causes the positive potential (VP) and the negative potential (VP) The common electrode potential (VCOM) and the holding capacitance potential (VCST), which are set to the same potential as VN), are forcibly and quickly discharged to the ground via the discharge means 24, so that the common electrode potential is discharged. The liquid crystal capacitance 13 and the holding capacitance 15 of each pixel 6 (FIG. 4) without causing a potential difference between the potential (VCOM) and the holding capacitance potential (VCST) and the plus side potential (VP) and the minus side potential (VN). Thus, the electric charge held in the first and second discharges can be surely discharged, and afterimages after power-off can be surely prevented.

  Specifically, since the discharging means 24 is composed of a MOSFET 91 and a resistor 92, if the threshold voltage of the MOSFET 91 is about 1.5V, switching control can be easily performed at a CMOS logic level and the like. By changing the resistance value of 92, the discharge rate by the discharge means 24 can be easily set.

  Moreover, since the discharging means 24 is a series circuit of the MOSFET 91 and the resistor 92, it can be easily configured.

  In addition, since the voltage is generally discharged immediately after the power supply is cut off, and it is not easy to control various circuits such as the signal generation unit 22, the charge storage unit 21 that holds the charge for a predetermined time is provided. The signal generator 22 and the like can be easily controlled without separately outputting a predetermined signal for notifying the power shut-off when the power is shut down from the device main body side in which the device is incorporated, and the charge of the pixel 6 (FIG. 4) is surely secured. Can be discharged.

  In the above embodiment, the detecting means 20 is not limited to the above configuration as long as it can detect a voltage drop when the power is shut off.

  Similarly, the charge storage means 21 is limited to the above configuration as long as it can hold the charge for a predetermined time when the detection means 20 detects a drop in the power supply voltage (POWER) and can drive the signal generation means 22 by this charge. The signal generating means 22 is not limited to the above configuration as long as it can generate a signal when the detecting means 20 detects a drop in the power supply voltage (POWER). As long as the holding capacitor 15 and the signal line 12 can be set to the same potential based on the signal generated by the generation unit 22, the configuration is not limited to the above, and the discharge unit 24 is generated by the signal generation unit 22. If the common electrode 18, the holding capacitor 15 and the signal line 12 can be set to the same potential and the electric charge of the common electrode 18 and the holding capacitor 15 can be discharged to the ground based on the signal, the configuration is limited to the above. No.

  Further, details of the array substrate 2 and the counter substrate 3 of the liquid crystal panel 1 are not limited to the above configuration.

It is a block diagram which shows the liquid crystal display element of one embodiment of this invention. It is a circuit diagram which shows the principal part of a liquid crystal display element same as the above. It is a top view which shows a liquid crystal display element same as the above. It is a circuit diagram which shows the pixel of a liquid crystal display element same as the above. It is a timing chart which shows control of a liquid crystal display element same as the above.

Explanation of symbols

1 LCD panel
11 Scan lines
12 Signal line
14 Thin film transistor
15 Holding capacity
16 pixel electrodes
18 Common electrode
20 Voltage drop detection means
21 Charge storage means
22 Signal generation means
23 Initialization method
24 Discharge means
91 MOSFET
92 Resistance

Claims (3)

Controlled by a plurality of signal lines and a plurality of scanning lines arranged in an intersecting manner, pixel electrodes provided at each intersection of the signal lines and the scanning lines, and a drive signal supplied to the scanning lines. A liquid crystal display element comprising: a switching element for driving a pixel electrode; a storage capacitor electrically connected to the pixel electrode; and a common electrode disposed facing the pixel electrode with a liquid crystal layer interposed therebetween. There,
A voltage drop detection means for detecting a voltage drop when the power is shut off;
A signal generating means for generating a signal when a voltage drop is detected by the voltage drop detecting means;
Initialization means for setting the common electrode, the storage capacitor, and the signal line to the same potential based on the signal generated by the signal generation means;
A liquid crystal display element comprising: a discharge unit that discharges charges of the common electrode and the storage capacitor to a ground based on a signal generated by the signal generation unit. The discharging means includes
A transistor in which the drain electrode is grounded and the signal generated by the signal generating means is input to the gate electrode;
The liquid crystal display element according to claim 1, further comprising a resistor electrically connected between the common electrode and a source electrode of the transistor. 3. A liquid crystal display according to claim 1, further comprising charge storage means for holding a charge for a predetermined time when the voltage drop is detected by the voltage drop detection means and driving the signal generation means by the charge. element.

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