JP2009003207A - Display device and driving circuit for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix display device provided with a circuit of a simple constitution, capable of turning on all switching elements of a pixel forming part after turning off a power source. <P>SOLUTION: An off-detection circuit 122 included in a second potential supply circuit 120 of the display device comprises a resistive element 12 and a capacitative element 13 which function as a delay circuit, and a differential voltage between a gate-on potential VGH supplied from a power circuit 200 turned off and a delay signal potential Va of the gate-on potential VGH is applied between a gate terminal and a source terminal of FET 11 constituting a switch circuit 121. When this potential difference exceeds a prescribed threshold, the FET 11 is turned on, and the potential Va is applied to a scanning signal line. Thus, by supplying the potential Va to the switching elements of the pixel formation part by using a simple circuit comprising three elements, all the switching elements can be turned on. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an active matrix display device using a switching element such as a thin film transistor and a driving method thereof.

  In general, an active matrix liquid crystal display device includes a display unit including two substrates sandwiching a liquid crystal layer, and one of the two substrates has a plurality of video signals as video signal lines. A plurality of pixel forming portions in which signal lines and a plurality of scanning signal lines as scanning signal lines are arranged in a lattice shape, and are arranged in a matrix corresponding to the intersections of the plurality of video signal lines and the scanning signal lines, respectively. Is provided. Each pixel formation portion constitutes a display portion of the device, and a TFT (Thin Film Transistor) which is a switching element having a gate terminal connected to a scanning signal line and a source terminal connected to a video signal line, And a pixel electrode connected to the drain terminal of the TFT. In addition, the other substrate among the above substrates is provided with a common electrode for applying a common potential to the pixel electrode of each pixel formation portion.

  Such an active matrix liquid crystal display device includes a source driver for driving the video signal line of the display unit, a gate driver for driving the scanning signal line of the display unit, and a common electrode drive for driving the common electrode. And a display control circuit for controlling the source driver, the gate driver, and the common electrode driving circuit.

  In such an active matrix liquid crystal display device, it has been pointed out that there is a problem that an image such as an afterimage remains without being immediately cleared even if a user performs an operation to turn off the power of the device. Yes. This problem is caused by having to wait for the charge to gradually decrease due to self-discharge because the discharge path of the charge held in the liquid crystal capacitor is cut off when the power of the device is turned off. . In addition, if a state where charges are accumulated in the liquid crystal capacitor for a long time continues, a direct current component is continuously applied between the electrodes sandwiching the liquid crystal, and the liquid crystal deteriorates and a permanent afterimage is generated.

  Therefore, in order to solve such a problem, there is a conventional liquid crystal display device that detects a signal non-input state to the liquid crystal display device and outputs a signal for making all scanning signal lines active for a predetermined period at the time of detection. (For example, refer to Patent Document 1). With this configuration (hereinafter referred to as the first conventional example), all the switching elements in the pixel formation portion are turned on, so that the charge accumulated in the liquid crystal can be discharged.

In order to solve the above problem, there is a conventional liquid crystal display device that lowers the potential of the common electrode below the minimum value of the gate potential of the switching element when the operation of the display device stops (see, for example, Patent Document 2). With this configuration (hereinafter referred to as the second conventional example), as in the first conventional example, all the switching elements in the pixel formation portion are turned on, so that the charge accumulated in the liquid crystal can be discharged.
JP 2001-209355 A JP 2003-12211 A

  However, the first and second conventional examples require a relatively complicated circuit such as a circuit for detecting that the power is turned off and a circuit for generating a predetermined potential, and the circuit scale is large as a whole. Become. In particular, the first conventional example requires a circuit that supplies power for a certain period of time after the power is turned off, further increasing the circuit scale.

  Accordingly, an object of the present invention is to provide an active matrix display device including a circuit having a simple configuration capable of turning on all the switching elements of a pixel formation portion after the power is turned off, and a driving circuit thereof. .

The first invention provides a plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals. A scanning signal line drive circuit for driving the plurality of scanning signal lines in an active matrix display device comprising a plurality of pixel forming portions arranged in a matrix corresponding to intersections of lines and the plurality of scanning signal lines, respectively Because
A driver circuit for supplying a scanning signal for selectively driving the plurality of scanning signal lines to the plurality of scanning signal lines;
A potential supply circuit for supplying a potential for turning on the switching elements included in the plurality of pixel forming portions to the plurality of scanning signal lines when the power of the scanning signal line driving circuit is turned off;
The potential supply circuit includes:
When the power supply is turned off, the potential is higher than a predetermined reference potential and is the same as the first potential supplied from the power supply as a starting point, and later in the same direction as the change in the first potential. A delay circuit for generating a changing second potential;
A switch circuit that is provided for each scanning signal line and applies the second potential to the corresponding scanning signal line when a differential voltage between the first potential and the second potential is greater than a predetermined threshold; It is characterized by including.

According to a second invention, in the first invention,
The switch circuit is a field effect transistor in which the first potential is applied to a gate terminal, and one of a source terminal and a drain terminal is connected to a corresponding scanning signal line,
The delay circuit is
A capacitive element having one end grounded and the other end connected to the other of the source terminal and the drain terminal;
And a resistor element having one end connected to the gate terminal and the other end connected to the other of the source terminal and the drain terminal.

  A third invention is an active matrix display device comprising the scanning signal line driving circuit described in the first or second invention.

According to a fourth aspect of the present invention, a plurality of video signal lines for transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals Video signal line driving circuit for driving the plurality of video signal lines in an active matrix display device comprising a plurality of pixel forming portions arranged in a matrix corresponding to intersections of lines and the plurality of scanning signal lines, respectively Because
A driver circuit for providing the plurality of video signals to the plurality of video signal lines;
A potential supply circuit for providing the plurality of video signal lines with a potential for turning on the switching elements included in the plurality of pixel formation portions when the power of the video signal line driving circuit is turned off;
The potential supply circuit includes:
When the power is turned off, the potential is lower than a predetermined reference potential and is the same potential as the first potential supplied from the power source, and later in the same direction as the change in the first potential. A delay circuit for generating a changing second potential;
A switch circuit that is provided for each video signal line and applies the second potential to a corresponding video signal line when a differential voltage between the first potential and the second potential is greater than a predetermined threshold; It is characterized by including.

A fifth invention is the fourth invention,
The switch circuit is a field effect transistor in which the first potential is applied to a gate terminal and one of a source terminal and a drain terminal is connected to a corresponding video signal line,
The delay circuit is
A capacitive element having one end grounded and the other end connected to the other of the source terminal and the drain terminal;
And a resistor element having one end connected to the gate terminal and the other end connected to the other of the source terminal and the drain terminal.

  A sixth invention is an active matrix display device comprising the video signal line driving circuit according to the fourth or fifth invention.

According to a seventh aspect of the present invention, a plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting the plurality of video signal lines, and the plurality of video signals A plurality of pixel forming portions arranged in a matrix corresponding to intersections of the lines and the plurality of scanning signal lines, and a common provided in common to apply a common potential to the plurality of pixel forming portions. A common electrode driving circuit for driving the common electrode in an active matrix display device comprising electrodes,
A driver circuit for applying the common potential to the common electrode;
A potential supply circuit that provides the common electrode with a potential for turning on the switching elements included in the plurality of pixel formation portions when the common electrode drive circuit is powered off;
The potential supply circuit includes:
When the power is turned off, the potential is lower than a predetermined reference potential and is the same potential as the first potential supplied from the power source, and later in the same direction as the change in the first potential. A delay circuit for generating a changing second potential;
And a switch circuit that applies the second potential to the common electrode when a differential voltage between the first potential and the second potential is greater than a predetermined threshold value.

In an eighth aspect based on the seventh aspect,
The switch circuit is a field effect transistor in which the first potential is applied to a gate terminal, and one of a source terminal and a drain terminal is connected to the common electrode,
The delay circuit is
A capacitive element having one end grounded and the other end connected to the other of the source terminal and the drain terminal;
And a resistor element having one end connected to the gate terminal and the other end connected to the other of the source terminal and the drain terminal.

  A ninth invention is an active matrix display device comprising the common electrode driving circuit according to the seventh or eighth invention.

According to a tenth aspect of the present invention, a plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals A plurality of pixel forming portions arranged in a matrix corresponding to intersections of the lines and the plurality of scanning signal lines, and a common provided in common to apply a common potential to the plurality of pixel forming portions. An active matrix display device comprising electrodes,
A gate driver circuit for selectively driving the plurality of scanning signal lines;
A source driver circuit for providing the plurality of video signals to the plurality of video signal lines;
A common driver circuit for applying the common potential to the common electrode;
A gate potential supply circuit that applies a predetermined potential to the plurality of scanning signal lines to turn on the switching elements included in the plurality of pixel formation portions when the power of the display device is turned off;
The gate potential supply circuit includes:
A gate delay circuit that generates a second potential that is higher than a predetermined reference potential and changes more slowly than a change in the first potential supplied from the power source when the power is turned off;
A gate switch circuit which is provided for each scanning signal line and applies the second potential to the corresponding scanning signal line when a differential voltage between the first potential and the second potential is larger than a predetermined threshold; It is characterized by including.

In an eleventh aspect based on the tenth aspect,
A source potential supply circuit for supplying a potential for turning on the switching elements included in the plurality of pixel formation portions to the plurality of video signal lines when the power is turned off;
The source potential supply circuit includes:
A source delay circuit that generates a fourth potential that is lower than a predetermined reference potential and changes more slowly than a third potential supplied from the power source when the power is turned off;
A source switch circuit provided for each of the video signal lines, which applies the fourth potential to a corresponding video signal line when a differential voltage between the third potential and the fourth potential is greater than a predetermined threshold; It is characterized by including.

In a twelfth aspect based on the tenth or eleventh aspect,
A common potential supply circuit for providing the common electrode with a potential for turning on switching elements included in the plurality of pixel formation portions when the power is turned off;
The common potential supply circuit is
A common delay circuit that generates a sixth potential that is lower than a predetermined reference potential and changes more slowly than a fifth potential supplied from the power source when the power is turned off;
A common switch circuit that is provided for each of the scanning signal lines and applies the sixth potential to the common electrode when a differential voltage between the fifth potential and the sixth potential is greater than a predetermined threshold value. It is characterized by that.

  According to the first aspect of the invention, the simple potential supply circuit including the delay circuit and the switch circuit can turn on all the switching elements of the pixel formation portion after the power is turned off. Can provide a scanning signal line driver circuit capable of discharging charges accumulated in a pixel formation portion including a liquid crystal element. Therefore, such a simple circuit configuration can solve the problem that an image such as an afterimage remains after the power is turned off and the problem that a permanent afterimage due to deterioration of a liquid crystal element or the like occurs.

  According to the second aspect, the potential supply circuit can be a very simple circuit including an electric field transistor, a resistance element, and a capacitance element.

  According to the third aspect, the same effect as that of the first or second aspect can be achieved in the display device.

  According to the fourth aspect of the invention, the simple potential supply circuit including the delay circuit and the switch circuit can turn on all the switching elements of the pixel formation portion after the power is turned off. Can provide a video signal line driver circuit capable of discharging charges accumulated in a pixel formation portion including a liquid crystal element. Note that when the video signal line driver circuit is incorporated in the display device, the power source is the same as the power source of the scanning signal line driver circuit. Therefore, by sufficiently reducing the potential of the video signal line with respect to the scanning signal line, the pixel All the switching elements in the formation portion can be turned on. Therefore, such a simple circuit configuration can solve the problem that an image such as an afterimage remains after the power is turned off and the problem that a permanent afterimage due to deterioration of a liquid crystal element or the like occurs.

  According to the fifth aspect, the potential supply circuit can be a very simple circuit including an electric field transistor, a resistance element, and a capacitance element.

  According to the sixth aspect, the same effect as in the fourth or fifth aspect can be achieved in the display device.

  According to the seventh aspect, a simple potential supply circuit including a delay circuit and a switch circuit can turn on all the switching elements of the pixel formation portion after the power is turned off. Can provide a common electrode driving circuit capable of discharging charges accumulated in a pixel formation portion including a liquid crystal element. Note that when the common electrode driving circuit is incorporated in the display device, the power source is common with the power source of the scanning signal line driving circuit. Therefore, by sufficiently reducing the potential of the common electrode with respect to the scanning signal line, the pixel formation portion All the switching elements can be turned on. Therefore, such a simple circuit configuration can solve the problem that an image such as an afterimage remains after the power is turned off and the problem that a permanent afterimage due to deterioration of a liquid crystal element or the like occurs.

  According to the eighth aspect, the potential supply circuit can be a very simple circuit including an electric field transistor, a resistance element, and a capacitance element.

  According to the ninth aspect, the same effects as those of the seventh or eighth aspect can be achieved in the display device.

  According to the tenth aspect, by providing the same potential supply circuit as the potential supply circuit included in the first aspect, the same effect as that of the first aspect can be achieved in the display device.

  According to the eleventh aspect of the present invention, the potential of the video signal line with respect to the scanning signal line can be sufficiently lowered by providing the same power supply circuit as the potential supply circuit included in the first and fourth aspects of the invention. As a result, the charges accumulated in the pixel formation portion can be sufficiently discharged.

  According to the twelfth aspect, each of the scanning signal lines includes the same power supply circuit as the potential supply circuit included in the first and seventh aspects or the first, fourth, and seventh aspects. Since the potential of the common electrode can be sufficiently lowered, the charge accumulated in the pixel formation portion can be sufficiently discharged.

  Hereinafter, the configuration and operation of an active matrix liquid crystal display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

<1. Overall configuration and operation>
FIG. 1 is a block diagram showing the configuration of the liquid crystal display device according to this embodiment together with an equivalent circuit of the display unit. This liquid crystal display device includes an active matrix display unit 100, a source driver 101 as a video signal line driving circuit, a gate driver 102 as a scanning signal line driving circuit, and a common electrode driving circuit 103 for driving a common electrode. Specifically, first to third potential supply circuits 110, 120, and 130, which will be described later, a display control circuit 300 for controlling the source driver 101, the gate driver 102, and the common electrode driving circuit 103, and these circuits And a power supply circuit 200 for supplying power to the device.

  The power supply circuit 200 is described so as to apply a gate-off potential VGL, which will be described later, to the first and third potential supply circuits 110, 130, and to supply a gate-on potential VGH, which will be described later, to the second potential supply circuit 120. These descriptions are intended to emphasize the characteristics of the operation described later in each potential supply circuit, and potentials other than these potentials are also supplied to each circuit.

  In the present embodiment, the display unit 100 includes a plurality (m) of scanning signal lines (gate lines) GL1 to GLm and a plurality (n) of video signals that intersect with each of the scanning signal lines GL1 to GLm. Lines (data lines) SL1 to SLn and a plurality (m × n) of pixel forming portions provided corresponding to the intersections of the scanning signal lines GL1 to GLm and the video signal lines SL1 to SLn, respectively. Including.

  These pixel forming portions are arranged in a matrix to form a pixel array, and each pixel forming portion has a gate terminal connected to a scanning signal line GLj (j is a natural number of m or less) passing through a corresponding intersection. TFT 10 which is a switching element having a source terminal connected to a video signal line SLk (k is a natural number equal to or less than n) passing through the intersection, a pixel electrode connected to the drain terminal of the TFT 10, and the plurality of pixel forming portions A common electrode Ec, which is a common electrode provided in common, and a liquid crystal layer sandwiched between the pixel electrode and the common electrode Ec provided in common to the plurality of pixel formation portions. An auxiliary capacitor is added in parallel to the capacitor formed by the pixel electrode and the common electrode Ec. A pixel capacitor Cp is configured by a capacitor formed by the pixel electrode and the common electrode Ec (a capacitor obtained by adding an auxiliary capacitor to the capacitor if an auxiliary capacitor is added). The driving method and driving circuit of the present invention for the display unit 100 of the present embodiment having such a configuration will be described below.

  In this embodiment, image data (in a narrow sense) representing an image to be displayed on the liquid crystal panel and data (for example, data indicating the frequency of the display clock) (hereinafter referred to as “display control data”) for determining the timing of the display operation, etc. The data is sent from the CPU or the like in the external computer to the display control circuit 300 (hereinafter, these data Dv sent from outside are referred to as “broadly defined image data”). That is, an external CPU or the like writes image data and display control data (in a narrow sense) constituting image data Dv in a broad sense to display memories and registers (not shown) in the display control circuit 300, respectively.

  The display control circuit 300 displays the source driver start pulse signal SSP and the source driver clock signal SCK as signals for causing the display unit 100 to display the image data Dv and the image represented by the image data Dv. A digital image signal DA (a signal corresponding to the image data Dv) representing a power image, a gate driver start pulse signal GSP, and a gate driver clock signal GCK are generated and output.

  More specifically, the image data Dv is output from the display control circuit 300 as the digital image signal DA after timing adjustment or the like is performed as necessary in the internal memory, and corresponds to each pixel of the image represented by the digital image signal DA. A source driver clock signal SCK is generated as a signal composed of pulses, and a source driver start pulse signal SSP is generated as a signal that is high level (H level) for a predetermined period every one horizontal scanning period, and one frame period (1 A gate driver start pulse signal GSP is generated as a signal that becomes H level only for a predetermined period every vertical scanning period), and a gate driver clock signal GCK that repeatedly includes a predetermined pulse is generated.

  Of the signals generated in the display control circuit 300 as described above, the digital image signal DA, the source driver start pulse signal SSP, and the clock signal SCK are input to the source driver 101 and the gate driver start pulse. The signal GSP and the clock signal GCK are input to the gate driver 102, and the polarity inversion signal Sec indicating the polarity inversion timing described later is input to the common electrode driving circuit 103.

  Based on the digital image signal DA, the source driver start pulse signal SSP, and the clock signal SCK, the source driver 101 uses the video signal S as an analog voltage corresponding to the pixel value in each horizontal scanning line of the image represented by the digital image signal DA. (1) to S (n) are sequentially generated for each horizontal scanning period, and these video signals S (1) to S (n) are applied to the video signal lines SL1 to SLn, respectively. The source driver 101 according to the present embodiment is configured so that the polarity of the voltage applied to the liquid crystal layer is inverted every frame period and is also inverted every horizontal scanning line in each frame. A driving method in which S (n) is output, that is, a line inversion driving method is employed. The polarity inversion timing for each horizontal scanning line is given by the polarity inversion signal Sec. In addition, from the viewpoint of improving display quality, in addition to this, a driving method that reverses the polarity of the voltage applied to the liquid crystal layer for each video signal line (each vertical line), that is, a dot inversion driving method is adopted. Also good. That is, the source driver 101 may output the video signals S (1) to S (n) so that the polarity of the voltage applied to the video signal lines SL1 to SLn is inverted for each video signal line.

  The gate driver 102 typically includes an m-stage shift register, receives the gate driver start pulse signal GSP and the gate driver clock signal GCK from the display control circuit 300, and based on these signals GSP and GCK, Scanning G (1) to G (m) is performed by sequentially shifting a pulse having a width equal to the rising edge of the gate driver clock signal GCK from the rising edge to the next rising edge (that is, the length of one horizontal scanning period) from the input end to the output end. ) Is generated. That is, the gate driver 102 sequentially selects the scanning signal lines GL1 to GLm in each frame period (each vertical scanning period) of the digital image signal DA, and the active scanning signals G (1) to G (G) to the selected scanning signal line. Apply (m). Here, each of the scanning signal lines GL1 to GLm is selected once in each frame period.

  In the display unit 100, when each of the scanning signal lines GL1 to GLm is selected in each frame period, each TFT 10 whose gate terminal is connected to the selected scanning signal line GLj is turned on in each selection period. Become. Thus, a voltage corresponding to the value of the corresponding pixel in the image represented by the digital image signal DA is held in the pixel capacitor Cp connected to the drain terminal of each TFT 10.

  In the display unit 100, the video signals S (1) to S (n) are applied to the video signal lines SL1 to SLn and the scanning signals GL1 to GLm are scanned by the source driver 101 and the gate driver 102, respectively. G (1) to G (m) are respectively applied. As a result, a voltage corresponding to the value of the corresponding pixel in the image represented by the digital image signal DA is given to the pixel capacitance Cp of each pixel forming unit in the display unit 100 by the video signals S (1) to S (n). A voltage corresponding to the potential difference between the pixel electrode and the common electrode Ec is applied to the liquid crystal layer according to the digital image signal DA. That is, the voltage held in each pixel capacitor Cp becomes the voltage applied to the corresponding liquid crystal portion.

  The display unit 100 displays the image represented by the digital image signal DA, that is, the image represented by the digital video signal received from an external signal source, by controlling the light transmittance of the liquid crystal layer by the applied voltage. Next, among the first to third potential supply circuits 110, 120, and 130, the detailed configuration of the second potential supply circuit 120 will be described below with reference to FIGS.

<2. Configuration and Operation of Potential Supply Circuit>
<2.1 Configuration and Operation of Second Potential Supply Circuit>
FIG. 2 is a diagram showing a detailed configuration of the second potential supply circuit in the present embodiment. The second potential supply circuit 120 shown in FIG. 2 outputs the scanning signals G (1) to G (m) received from the gate driver 102 as they are and performs all scanning when the power supply circuit 200 is turned off. A predetermined signal for activating the signal line is output.

  The second potential supply circuit 120 includes m switch circuits provided corresponding to all the scanning signal lines GL1 to GLm, and one off detection circuit 122. Note that the second potential supply circuit 120 including these circuits is described as being configured separately from the gate driver 102, but may be configured integrally in one integrated circuit. The off detection circuit 122 may be provided for each switch circuit.

  The off-detection circuit 122 receives an active potential (hereinafter referred to as “gate-on potential”) VGH of the scanning signal supplied from the power supply circuit 200, and responds to the decrease in the gate-on potential VGH when the power supply circuit 200 is turned off. A plurality of switch circuits are turned on, and a predetermined signal for turning on the TFTs in all the pixel formation portions (typically making all scanning signal lines active) is given to all the switch circuits.

  Here, as the switch circuit 121 corresponding to the scanning signal line GLm among the plurality of switch circuits, the configuration of the switch circuit 121 and the off detection circuit 122 will be described in detail with reference to FIG.

  FIG. 3 is a circuit diagram showing a configuration of a certain switch circuit and off detection circuit included in the second potential supply circuit 120. As shown in FIG. 3, the switch circuit 121 includes a P-channel FET (Field Effect Transistor) 11, and the off detection circuit 122 includes a resistance element 12 and a capacitance element 13.

  The FET 11 constituting the switch circuit 121 has its gate terminal connected to the wiring for supplying the gate-on potential VGH from the power supply circuit 200, its drain terminal connected to the scanning signal line GLm, and its source terminal connected to the resistor element 12. And connected to one end of the capacitive element 13. The other end of the resistance element 12 is connected to the gate terminal, and the other end of the capacitive element 13 is grounded. Here, the ground potential is assumed to be 0 [V]. Next, an operation for supplying a predetermined signal for activating the scanning signal line GLm when the power supply circuit 200 is turned off will be described in detail with reference to FIG.

  FIG. 4 is a diagram simply showing potential changes such as the gate-on potential when the power supply circuit is turned off. In FIG. 4, a change in the source potential Va at the source terminal of the FET 11 is simply shown together with a potential change in which the gate-on potential VGH decreases toward the ground potential GND when the power supply circuit 200 is turned off.

  First, when the power supply circuit 200 is turned off at time t1, the gate-on potential VGH starts to decrease toward the ground potential GND. At this time, the source potential Va, which is the same potential as the gate-on potential VGH, also starts to decrease toward the ground potential GND. However, the decrease in the source potential Va is caused by the delay circuit configured by the resistance element 12 and the capacitor element 13. As shown in FIG. 4, it becomes more gradual than the decrease in VGH.

  Thereafter, at time t2, the source potential Va becomes higher than the gate-on potential VGH by a predetermined threshold voltage Vth. Here, the threshold voltage Vth is a minimum voltage value for turning on the FET 11, and when the potential of the gate terminal of the FET 11 is larger than the potential of the source terminal by the threshold voltage Vth or more, the FET 11 is turned on and the drain terminal Is equal to the potential of the source terminal. Therefore, the source potential Va starts to be applied to the scanning signal line GLm from time t2.

  This source potential Va is given to each TFT 10 whose gate terminal is connected to the scanning signal line GLm. Here, in the normal display where the power supply circuit 200 is not turned off, the normal gate-on potential VGH given when the scanning signal line GLm is selected is set to a potential sufficiently higher than the minimum potential at which the TFT 10 is turned on. ing. Therefore, at time t2, the TFT 10 to which the source potential Va slightly lower than the normal gate-on potential VGH is turned on in the same manner as when the scanning signal line GLm is selected.

  However, as will be described later, in the present embodiment, since the potential lower than the ground potential GND is applied to the video signal line SL1 and the common electrode Ec at time t2, the potential difference between the gate terminal and the source terminal of the TFT 10 or the gate terminal It is extremely easy to make the potential difference between the drain terminal and the drain terminal sufficiently larger than the minimum potential at which the TFT 10 is turned on. Therefore, after time t2, even when the source potential Va is considerably lower than the normal gate-on potential VGH, the TFT 10 can be turned on as in the case where the scanning signal line GLm is selected. .

  After that, the source potential Va continues to decrease after the gate-on potential VGH reaches the ground potential GND, so that the source potential Va becomes lower than the predetermined threshold voltage Vth than the gate-on potential VGH from the time immediately after time t3. Therefore, the FET 11 is turned off from this point.

  As described above, during the period from time t2 to time t3, the off detection circuit 122 functioning as a delay circuit composed of the resistance element 12 and the capacitance element 13 turns on the switching circuit composed of the FET 11, thereby turning on each scanning signal. A potential sufficiently larger than the minimum potential for turning on the TFT in the pixel formation portion can be applied via the line.

<2.2 Configuration and Operation of First Potential Supply Circuit>
The configuration of the second potential supply circuit 120 as described above is substantially the same in the first and third potential supply circuits 110 and 130.

  That is, the first potential supply circuit 110 includes n switch circuits provided corresponding to all the video signal lines SL1 to SLn and one off detection circuit. However, this off detection circuit, unlike the off detection circuit 122 included in the second potential supply circuit 120, receives the inactive potential (hereinafter referred to as “gate off potential”) VGL of the scanning signal supplied from the power supply circuit 200. When the power supply circuit 200 is turned off, the plurality of switch circuits are turned on in response to the rise of the gate-off potential VGL, and a predetermined signal for turning on the TFTs 10 in all the pixel formation portions is given to all the switch circuits. .

  Here, the configuration of the switch circuit and the off detection circuit included in the first potential supply circuit 110 is almost the same as the configuration of the switch circuit 121 and the off detection circuit 122 included in the second potential supply circuit 120 shown in FIG. Since it is the same, it demonstrates further in detail with reference to FIG.

  FIG. 5 is a circuit diagram showing a configuration of a certain switch circuit and off detection circuit included in the first potential supply circuit 110. As shown in FIG. 5, the switch circuit 111 includes an N-channel type FET 14, and the off detection circuit 112 includes a resistance element 15 and a capacitance element 16.

  The FET 14 constituting the switch circuit 121 has its gate terminal connected to the wiring for applying the gate-off potential VGL from the power supply circuit 200, its drain terminal connected to the video signal line SLn, and its source terminal connected to the resistance element 15 And connected to one end of the capacitive element 16. The other end of the resistance element 15 is connected to the gate terminal, and the other end of the capacitive element 16 is grounded. Next, an operation for giving a predetermined signal lower than the reference ground potential to the video signal line SLn when the power supply circuit 200 is turned off will be described in detail with reference to FIG.

  FIG. 6 is a diagram simply showing a potential change such as a gate-off potential when the power supply circuit is turned off. In FIG. 6, a change in the source potential Vb at the source terminal of the FET 14 is simply shown together with a potential change in which the gate-off potential VGL increases toward the ground potential GND when the power supply circuit 200 is turned off.

  Here, as can be seen by comparing FIG. 6 with FIG. 5 described above, the change in the source potential Vb of the FET 14 is the same except that the polarity of the change in the source potential Va of the FET 11 is opposite. Therefore, detailed explanation is omitted.

  Here, since the source potential Vb applied to the video signal line SL1 is sufficiently lower than the ground potential GND as shown in FIG. 6, the source potential Va is considerably higher than the normal gate-on potential VGH. Even when the voltage is low, the potential difference between the gate terminal and the source terminal of the TFT 10 can be made sufficiently higher than the minimum potential at which the TFT 10 is turned on. Therefore, from time t2 to time t3, the off detection circuit 112 functioning as a delay circuit composed of the resistor element 15 and the capacitor element 16 turns on each video signal line and scan by turning on the switch circuit composed of the FET 14. A potential sufficiently higher than the minimum potential for turning on the TFT in the pixel formation portion can be applied via the signal line.

<2.3 Configuration and Operation of Third Potential Supply Circuit>
The configuration of the switch circuit and the off detection circuit included in the third potential supply circuit 130 is the same as the configuration of the switch circuit 111 and the off detection circuit 112 included in the first potential supply circuit 110 shown in FIG. Since it is substantially the same except that the source potential Vb is applied to the common electrode Ec instead of the signal line, detailed description thereof is omitted.

  Here, since the source potential Vb applied to the common electrode Ec is sufficiently lower than the ground potential GND, the source potential Va is considerably lower than the normal gate-on potential VGH. However, the potential difference between the gate terminal and the drain terminal of the TFT 10 can be made sufficiently larger than the minimum potential at which the TFT 10 is turned on. Therefore, from time t2 to time t3, a potential sufficiently larger than the minimum potential for turning on the TFT in the pixel formation portion can be applied via the common electrode Ec and the scanning signal line.

<3. Effect>
As described above, the first to third potential supply circuits 110, 120, and 130 in the above embodiment are each an off detection circuit that is a delay circuit including one resistance element and one capacitance element, and (scanning signal line) Every switching element of the pixel formation portion is turned on after the power supply circuit 200 is turned off by a simple circuit configuration including a switching circuit composed of one FET for each video signal line and for each common electrode). As a result, the charge accumulated in the liquid crystal can be discharged. Therefore, such a simple circuit configuration can solve the problem that an image such as an afterimage remains even after the power is turned off and the problem that a permanent afterimage due to deterioration of the liquid crystal occurs.

<4. Modification>
In the above embodiment, the first potential supply circuit 110 is provided outside the source driver 101, but a part or all of the first potential supply circuit 110 may be built in the source driver 101. That is, the first potential supply circuit 110 and the source driver 101 can be collectively referred to as a video signal line driving circuit.

  Similarly, the second potential supply circuit 120 is provided outside the gate driver 102, but part or all of the second potential supply circuit 120 may be built in the gate driver 102. That is, the second potential supply circuit 120 and the gate driver 102 can be collectively referred to as a scanning signal line driving circuit.

  Similarly, the third potential supply circuit 130 is provided outside the common electrode drive circuit 103, but a part or all of the third potential supply circuit 130 may be built in the common electrode drive circuit 103. That is, the third potential supply circuit 130 and the common electrode drive circuit 103 can be collectively referred to as a common electrode drive circuit.

  In the above-described embodiment, the first to third potential supply circuits 110, 120, and 130 are all provided, but any configuration that includes at least one of these may be used. That is, the potential difference between at least one of the video signal line and the common electrode and the scanning signal line when the power is turned off by any one of the first to third potential supply circuits 110, 120, and 130 provided in the display device. Thus, any configuration may be used as long as a potential capable of turning on the TFT in the pixel formation portion is applied. However, in the configuration in which all of the first to third potential supply circuits 110, 120, and 130 are provided, all the potentials of the gate terminal, the source terminal, and the drain terminal in the TFT of the pixel formation portion can be appropriately set. Therefore, it is most preferable in that the TFT of the pixel formation portion can be easily turned on with a lower gate potential than when only the second potential supply circuit 120 is provided.

  Further, even in a configuration in which only the second potential supply circuit 120 and any one of the first or third potential supply circuits 110 and 130 are provided, the potential of the gate terminal, the source terminal, and the drain in the TFT of the pixel formation portion Since one potential of the terminal can be set as appropriate, it is preferable in that the TFT of the pixel formation portion can be easily turned on with a lower gate potential than when only the second potential supply circuit 120 is provided. is there.

  In the above embodiment, the off-detection circuit 122 included in the second potential supply circuit 120 has a potential VGH that is higher than the ground potential GND and is supplied from the power supply circuit 200 when the power supply circuit 200 is turned off. It functions as a delay circuit that generates a potential Va that changes later than the change, but the potential VGH does not necessarily have to be higher than the ground potential GND of 0 [V], and the potential VGH when the scanning signal is active It is not necessary that the voltage is higher than a predetermined reference voltage as long as it can turn on the TFT of the pixel formation portion.

  Similarly, the off detection circuits included in the first and third potential supply circuits 110 and 130 function as a delay circuit that generates a potential Vb that changes later than the change in the gate off potential VGL. It does not necessarily have to be lower than the ground potential GND of 0 [V], and does not necessarily have to be the gate-off potential VGH. When the voltage is lower than a predetermined reference voltage, the TFT in the pixel formation portion is not connected to the scanning signal line. Any potential that can be turned on is acceptable.

  The switch circuits included in the first to third potential supply circuits 110, 120, and 130 are not necessarily FETs, and may be configured by other elements or circuits that function as switching elements such as bipolar transistors. .

  In the above-described embodiment, the active matrix liquid crystal display device has been described as an example. However, the present invention can be applied to devices other than the liquid crystal display device as long as the display device is based on active matrix voltage control.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on one Embodiment of this invention with the equivalent circuit of the display part. It is a figure which shows the detailed structure of the 2nd electric potential supply circuit in the said embodiment. FIG. 4 is a circuit diagram showing a configuration of a certain switch circuit and an off detection circuit included in a second potential supply circuit in the embodiment. In the said embodiment, it is a figure which shows simply potential changes, such as a gate-on potential, when a power supply circuit is turned off. FIG. 3 is a circuit diagram showing a configuration of a certain switch circuit and an off detection circuit included in the first potential supply circuit in the embodiment. In the said embodiment, it is a figure which shows simply potential changes, such as a gate-off potential, when a power supply circuit is turned off.

Explanation of symbols

10 ... TFT (switching element)
11, 14 ... FET
DESCRIPTION OF SYMBOLS 12,15 ... Resistance element 13,16 ... Capacitance element 100 ... Display part 101 ... Source driver 102 ... Gate driver 103 ... Common electrode drive circuit 110 ... 1st electric potential supply circuit 111, 121 ... Switch circuit 112, 122 ... Off detection Circuit 120 ... Second potential supply circuit 130 ... Third potential supply circuit 200 ... Power supply circuit 300 ... Display control circuit G (n) ... Scanning signal (n = 1 to N)
GLn: Scanning signal line (n = 1 to N)
SLm Video signal line (m = 1 to M)
P (n, m): Pixel formation portion (n = 1 to N, m = 1 to M)
VGH: Gate on potential VGL: Gate off potential GND: Ground potential

Claims (12)

A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings A scanning signal line driving circuit for driving the plurality of scanning signal lines in an active matrix display device comprising a plurality of pixel forming portions arranged in a matrix corresponding to the intersections with the signal lines,
A driver circuit for supplying a scanning signal for selectively driving the plurality of scanning signal lines to the plurality of scanning signal lines;
A potential supply circuit for supplying a potential for turning on the switching elements included in the plurality of pixel forming portions to the plurality of scanning signal lines when the power of the scanning signal line driving circuit is turned off;
The potential supply circuit includes:
When the power supply is turned off, the potential is higher than a predetermined reference potential and is the same as the first potential supplied from the power supply as a starting point, and later in the same direction as the change in the first potential. A delay circuit for generating a changing second potential;
A switch circuit that is provided for each scanning signal line and applies the second potential to the corresponding scanning signal line when a differential voltage between the first potential and the second potential is greater than a predetermined threshold; A scanning signal line driver circuit comprising: The switch circuit is a field effect transistor in which the first potential is applied to a gate terminal, and one of a source terminal and a drain terminal is connected to a corresponding scanning signal line,
The delay circuit is
A capacitive element having one end grounded and the other end connected to the other of the source terminal and the drain terminal;
The scanning signal line drive circuit according to claim 1, further comprising: a resistance element having one end connected to the gate terminal and the other end connected to the other of the source terminal and the drain terminal.   An active matrix display device comprising the scanning signal line driving circuit according to claim 1. A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings A video signal line driving circuit for driving the plurality of video signal lines in an active matrix type display device comprising a plurality of pixel forming portions arranged in a matrix corresponding to the intersections with the signal lines,
A driver circuit for providing the plurality of video signals to the plurality of video signal lines;
A potential supply circuit for providing the plurality of video signal lines with a potential for turning on the switching elements included in the plurality of pixel formation portions when the power of the video signal line driving circuit is turned off;
The potential supply circuit includes:
When the power is turned off, the potential is lower than a predetermined reference potential and is the same potential as the first potential supplied from the power source, and later in the same direction as the change in the first potential. A delay circuit for generating a changing second potential;
A switch circuit that is provided for each video signal line and applies the second potential to a corresponding video signal line when a differential voltage between the first potential and the second potential is greater than a predetermined threshold; A video signal line driving circuit comprising: The switch circuit is a field effect transistor in which the first potential is applied to a gate terminal and one of a source terminal and a drain terminal is connected to a corresponding video signal line,
The delay circuit is
A capacitive element having one end grounded and the other end connected to the other of the source terminal and the drain terminal;
5. The video signal line driving circuit according to claim 4, further comprising: a resistance element having one end connected to the gate terminal and the other end connected to the other of the source terminal and the drain terminal.   An active matrix display device comprising the video signal line driving circuit according to claim 4. A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings An active matrix comprising a plurality of pixel formation portions arranged in a matrix corresponding to each intersection with a signal line, and a common electrode provided in common to apply a common potential to the plurality of pixel formation portions A common electrode driving circuit for driving the common electrode in the display device,
A driver circuit for applying the common potential to the common electrode;
A potential supply circuit that provides the common electrode with a potential for turning on the switching elements included in the plurality of pixel formation portions when the common electrode drive circuit is powered off;
The potential supply circuit includes:
When the power is turned off, the potential is lower than a predetermined reference potential and is the same potential as the first potential supplied from the power source, and later in the same direction as the change in the first potential. A delay circuit for generating a changing second potential;
A common electrode driving circuit, comprising: a switch circuit that applies the second potential to the common electrode when a differential voltage between the first potential and the second potential is greater than a predetermined threshold value; . The switch circuit is a field effect transistor in which the first potential is applied to a gate terminal, and one of a source terminal and a drain terminal is connected to the common electrode,
The delay circuit is
A capacitive element having one end grounded and the other end connected to the other of the source terminal and the drain terminal;
The common electrode driving circuit according to claim 7, further comprising: a resistance element having one end connected to the gate terminal and the other end connected to the other of the source terminal and the drain terminal.   An active matrix display device comprising the common electrode driving circuit according to claim 7. A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings An active matrix comprising a plurality of pixel formation portions arranged in a matrix corresponding to each intersection with a signal line, and a common electrode provided in common to apply a common potential to the plurality of pixel formation portions Type display device,
A gate driver circuit for selectively driving the plurality of scanning signal lines;
A source driver circuit for providing the plurality of video signals to the plurality of video signal lines;
A common driver circuit for applying the common potential to the common electrode;
A gate potential supply circuit that applies a predetermined potential to the plurality of scanning signal lines to turn on the switching elements included in the plurality of pixel formation portions when the power of the display device is turned off;
The gate potential supply circuit includes:
A gate delay circuit that generates a second potential that is higher than a predetermined reference potential and changes more slowly than a change in the first potential supplied from the power source when the power is turned off;
A gate switch circuit which is provided for each scanning signal line and applies the second potential to the corresponding scanning signal line when a differential voltage between the first potential and the second potential is larger than a predetermined threshold; An active matrix display device comprising: A source potential supply circuit for supplying a potential for turning on the switching elements included in the plurality of pixel formation portions to the plurality of video signal lines when the power is turned off;
The source potential supply circuit includes:
A source delay circuit that generates a fourth potential that is lower than a predetermined reference potential and changes more slowly than a third potential supplied from the power source when the power is turned off;
A source switch circuit provided for each of the video signal lines, which applies the fourth potential to a corresponding video signal line when a differential voltage between the third potential and the fourth potential is greater than a predetermined threshold; The active matrix display device according to claim 10, comprising: A common potential supply circuit for providing the common electrode with a potential for turning on switching elements included in the plurality of pixel formation portions when the power is turned off;
The common potential supply circuit is
A common delay circuit that generates a sixth potential that is lower than a predetermined reference potential and changes more slowly than a fifth potential supplied from the power source when the power is turned off;
A common switch circuit that is provided for each of the scanning signal lines and applies the sixth potential to the common electrode when a differential voltage between the fifth potential and the sixth potential is greater than a predetermined threshold value. 12. The active matrix display device according to claim 10, wherein the active matrix display device is a display device.

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