CN111354321B - Level processing circuit, gate drive circuit and display device - Google Patents
Level processing circuit, gate drive circuit and display device Download PDFInfo
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- CN111354321B CN111354321B CN202010195461.4A CN202010195461A CN111354321B CN 111354321 B CN111354321 B CN 111354321B CN 202010195461 A CN202010195461 A CN 202010195461A CN 111354321 B CN111354321 B CN 111354321B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Crystallography & Structural Chemistry (AREA)
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the invention provides a level processing circuit, a gate driving circuit and a display device, relates to the technical field of display, and can solve the problem that an LPS (Low stress liquid Crystal) cross striation phenomenon occurs in the display device when the display device is turned off in a low-temperature environment. A level processing circuit comprises a voltage detection circuit, a switch selection circuit and an XAO circuit; the voltage detection circuit is configured to: if the first voltage is greater than or equal to the second voltage, outputting a high level to the switch selection circuit; if the first voltage is less than the second voltage, outputting the low level to the switch selection circuit; the switch selection circuit comprises a first switch and a second switch which are connected in parallel, and the second switch comprises a first sub-switch and a first resistor which are connected in series; the switch selection circuit is configured to: if the voltage detection circuit outputs high level, the first switch is opened, and the high level is output to the XAO circuit; if the voltage detection circuit outputs a low level, the first sub-switch is turned on to output the low level to the XAO circuit.
Description
Technical Field
The invention relates to the technical field of display, in particular to a level processing circuit, a grid driving circuit and a display device.
Background
Currently, when testing high refresh rate, high resolution products, such as a display device, the display device is turned on and off every 3 seconds at a temperature of-5 ℃.
Under low temperature environment, parameters such as reverse turn-off time, reverse turn-off voltage and the like of parasitic diodes of the thin film transistors are changed, so that liquid crystal equivalent capacitance C of the display deviceLCAnd a storage capacitor CSThe residual charge of (2) cannot be discharged cleanly through the thin film transistor in a short time, and is gradually accumulated with the passage of time, thereby showing a phenomenon of Limit Power Sequence (LPS) (fig. 1). That is, the performance of the thin film transistor included in the sub-pixel in a low temperature environment is deteriorated, and the electron mobility is correspondingly deteriorated, so that charge residue phenomena with different degrees are generated at different positions of the display screen, and an LPS cross striation phenomenon occurs on the display screen of the display device.
And at normal environmental temperature (for example, at 25 ℃), the display device is subjected to an experiment of starting and shutdown actions every 3s, and the display device does not have the LPS cross striation phenomenon.
Disclosure of Invention
Embodiments of the present invention provide a level processing circuit, a gate driving circuit, and a display device, which can solve the problem of LPS striation of the display device when the display device is turned off in a low temperature environment.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in a first aspect, a level processing circuit is provided, which includes a voltage detection circuit, a switch selection circuit, and an XAO circuit; the voltage detection circuit is configured to: if the first voltage is greater than or equal to the second voltage, outputting a high level to the switch selection circuit; if the first voltage is less than the second voltage, outputting a low level to the switch selection circuit; the switch selection circuit comprises a first switch and a second switch which are connected in parallel, and the second switch comprises a first sub-switch and a first resistor which are connected in series; the switch selection circuit is configured to: if the voltage detection circuit outputs a high level, the first switch is opened, and the high level is output to the XAO circuit; if the voltage detection circuit outputs a low level, the first sub-switch is turned on, and the low level is output to the XAO circuit.
Optionally, the voltage detection circuit includes a first input circuit, a second input circuit, and a comparator; the first input circuit is connected with a first voltage end, a second voltage end and a first node; the second input circuit is connected with the first voltage end, the second voltage end and a second node; the comparator is connected to the first node, the second voltage terminal, a digital voltage source, and the switch selection circuit.
Optionally, the first input circuit includes a second resistor and a third resistor; the second resistor is connected with the first voltage end and the first node; the third resistor is connected with the second voltage end and the first node.
Optionally, the second input circuit includes a fourth resistor, a fifth resistor, a sixth resistor, and a voltage regulator; the fourth resistor is connected with the third node and is connected with the second node through a fourth node; the fifth resistor is connected with the third node and the second voltage end; the sixth resistor is connected with the first voltage end and the second node through the fourth node; the voltage stabilizer is connected with the fourth node and the second voltage end.
Optionally, the voltage of the voltage stabilizer is 60% to 80% of the voltage of the first voltage end.
Optionally, the level processing circuit further includes an amplifying circuit; the amplifying circuit is connected with a first signal end, the output end of the switch selection circuit, a low voltage end and the input end of the XAO circuit.
Optionally, the amplifying circuit includes a first capacitor, a second capacitor, a first transistor, and a second transistor; the first capacitor is connected with the first signal end and the grid electrode of the first transistor; a first pole of the first transistor is connected with the output end of the switch selection circuit, and a second pole of the first transistor is connected with the input end of the XAO circuit; the second capacitor is connected with the first signal end and the grid electrode of the second transistor; the first pole of the second transistor is connected with the low voltage end, and the second pole of the second transistor is connected with the input end of the XAO circuit.
In a second aspect, a gate driving circuit is provided, which includes a shift register and the level processing circuit of the first aspect; the shift register is connected with the level processing circuit to receive the clock signal processed by the level processing circuit.
In a third aspect, a display device is provided, which includes the gate driving circuit of the second aspect.
Optionally, the display device further includes a display panel, where the display panel includes a plurality of gate lines; the gate driving circuit is connected to at least one gate line.
The embodiment of the invention provides a level processing circuit, a gate driving circuit and a display device, wherein the level processing circuit comprises a voltage detection circuit, a switch selection circuit and an XAO circuit. Under the low temperature environment, the voltage detection circuit outputs low level VGL to the switch selection circuit to control the first sub-switch to be conducted, and the first sub-switch is also connected in series with a first resistor R1, so that after the display panel is turned off, the liquid crystal equivalent capacitor C in the display panelLCAnd a storage capacitor CSThe thin film transistor keeps longer discharge time to solve the problem of static electricity residue and further solve the image quality problems such as LPS cross striation.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 illustrates an LSP striation phenomenon provided by the prior art;
FIG. 2 is a circuit diagram of a level processing circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a switch selection circuit according to an embodiment of the present invention;
fig. 4 is a timing diagram of a switch selection circuit according to an embodiment of the present invention;
fig. 5 is a connection diagram of a gate driving circuit and a display panel according to an embodiment of the invention.
Reference numerals:
10-a voltage detection circuit; 11-a first input circuit; 12-a second input circuit; 13-a comparator; 20-a switch selection circuit; 1-a first switch; 2-a first sub-switch; 30-XAO circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The display device comprises an array substrate, wherein the array substrate comprises a display area and a peripheral area positioned at the periphery of the display area, and the display area comprises a plurality of sub-pixels, grid lines, data lines and the like. The sub-pixel includes a pixel circuit, and the pixel circuit may include a thin film transistor as a switching element, a pixel electrode, a common electrode, and the like. The peripheral region includes a Gate Driver on Array (GOA) circuit, and the GOA circuit includes a plurality of cascaded shift registers. Each shift register generally includes a plurality of thin film transistors and a capacitor, and an output terminal of each shift register outputs a scan signal to a gate line. For example, each shift register is connected to one or more gate lines in the display region to supply a gate scan signal to the gate lines at a predetermined timing.
The input signals of the GOA circuit include a clock signal CLK, a start signal STV (i.e., a shift trigger signal SR _ IN), a high level signal VGH, a low level signal VGL, and the like. The clock signal CLK may include a first clock signal CLK1 and a second clock signal CLK2 as needed, and the GOA circuit generates a scan signal using the received clock signal CLK. The number of clock signals input to the shift register unit is not limited to two and may be one or more, depending on the circuit configuration of the shift register unit.
In the array substrate, a plurality of gate lines and a plurality of data lines may be arranged to intersect to define a plurality of sub-pixels. The thin film transistor is used as a switching element in the sub-pixel and is respectively connected with the grid line, the data line and the pixel electrode. The thin film transistor is controlled by a grid scanning signal on the grid line, a data signal on the data line is applied to the pixel electrode, and a voltage difference is formed between the pixel electrode and the common electrode, so that the deflection of liquid crystal molecules is controlled, and display is realized.
For the LPS striation phenomenon proposed in the background art, a commonly used method at present is to add a filter capacitor through a high level VGH to slow down a discharge rate of the high level VGH when the display device is turned off.
However, the inventors have found that there are a number of disadvantages with this approach: firstly, the capacitance needs to be increased to a certain amount to achieve the effect, so that the space of a Printed Circuit Board (PCB for short) is increased, the capacitance consumption is increased, and the cost is increased more; secondly, the method of increasing the capacitance often needs to increase to a larger capacity to be effective, so that when the device is started, because the large capacitance is charged: if the AVDD and the input voltage are pulled too low, a low voltage lock (UVLO) is activated, which causes an Abnormal Display (AD) phenomenon at the time of power-on, and the AD cannot be automatically recovered.
Accordingly, the embodiment of the present invention provides a level processing circuit, as shown in fig. 2, including a voltage detection circuit 10, a switch selection circuit 20, and an XAO circuit 30.
The voltage detection circuit 10 is configured to: if the first voltage is greater than or equal to the second voltage, outputting the high level VGH to the switch selection circuit 20; if the first voltage is less than the second voltage, the low level VGL is output to the switch selection circuit 20.
The switch selection circuit 20 comprises a first switch 1 and a second switch which are connected in parallel, wherein the second switch comprises a first sub-switch 2 and a first resistor R1 which are connected in series; the switch selection circuit 20 is configured to: if the voltage detection circuit 10 outputs the high level VGH, the first switch 1 is turned on to output the high level VGH to the XAO circuit 30; if the voltage detection circuit 10 outputs a low level, the first sub-switch 2 is turned on, and outputs the low level to the XAO circuit 30.
In some embodiments, as shown in fig. 2, the voltage detection circuit 10 includes a first input circuit 11, a second input circuit 12, and a comparator 13.
The first input circuit 11 is connected to the first voltage terminal VGH, the second voltage terminal VSS, and the first node a. The first input circuit 11 includes a second resistor R2 and a third resistor R3. The second resistor R2 is connected to the first voltage terminal VGH and the first node a; the third resistor R3 is connected to the second voltage terminal VSS and the first node a.
The second input circuit 12 is connected to the first voltage terminal VGH, the second voltage terminal VSS, and the second node b. The second input circuit 12 is connected to the first voltage terminal VGH, the second voltage terminal VSS, and the second node b. The second input circuit 12 includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a regulator R7.
The fourth resistor R4 is connected to the third node c and to the second node b via a fourth node d; the fifth resistor R5 is connected to the third node c and the second voltage terminal VSS; the sixth resistor R6 is connected to the first voltage terminal VGH, and is connected to the second node b through the fourth node d; the voltage regulator U1 is connected to the fourth node d and the second voltage terminal VSS. The comparator 13 is connected to the first node a, the second node b, the second voltage terminal VSS, the digital voltage source DVDD, and the switch selection circuit 20.
On this basis, the voltage detecting circuit 10 may further include a third capacitor C1, and the third capacitor C1 is connected to the digital voltage source DVDD. The third capacitor C1 may serve as a tamper-resistant function.
The working process of the voltage detection circuit 10 is as follows: the positive input end V + of the comparator 13 receives the first voltage V1 output by the first input circuit 11, and the negative input end V-receives the second voltage V2 output by the second input circuit 12; the comparator 13 outputs a high level VGH or a low level VGL to the switch selection circuit 20 by comparing the magnitudes of the first voltage V1 and the second voltage V2.
Wherein the first voltage
Second voltage
Vref is the reference voltage of regulator U1, and the value of Vref can be 2.5 + -0.1V according to practical situations.
Here, the value of the second voltage V2 can be determined by setting the values of R4 and R5. The second voltage V2 may be a discharge voltage, which is 60% -80% times higher than the high level VGH.
Assuming that the second voltage V2 is 80% VGH, the first voltage V1 is greater than or equal to the second voltage V2, that is, the voltage is
The first voltage V1 is less than the second voltage V2, i.e. it is
After the switch selection circuit 20 receives the signal sent by the voltage detection circuit 10, the working process is as follows: according to the truth formula:
the switch selection circuit 20 outputs VGH _ G.
Here, the input terminal S of the switch selection circuit 20, the first switch 1, and the first sub-switch 2 constitute a ganged switch as shown in fig. 3, and if the voltage detection circuit 10 inputs a high level VGH to the switch selection circuit 20, the input terminal S is bonded to the first switch 1, so that the first switch 1 is turned on; if the voltage detecting circuit 10 inputs a high level VGL to the switch selecting circuit 20, the input terminal S is bonded to the first sub-switch 2, so that the first sub-switch 2 is turned on.
As shown in fig. 4, due to the first sub-switchThe switch 2 is also connected in series with a first resistor R1, and after the shutdown, the voltage of the first voltage terminal VGH connected to the first input circuit 11 and the second input circuit 12 decreases, and the voltage of the digital voltage source DVDD connected to the comparator 13 decreases. Liquid crystal equivalent capacitor C in display panelLCAnd a storage capacitor CSThe thin film transistor keeps longer discharge time to solve the problem of static electricity residue and further solve the image quality problems such as LPS cross striation.
Wherein, under low temperature environment (for example below-5 ℃), the first sub-switch 2 can be turned on, thereby prolonging the liquid crystal equivalent capacitance CLCAnd a storage capacitor CSThe discharge time of (1). As shown in fig. 4, the discharge time when the first sub-switch 2 is turned on is longer than the discharge time when the first switch 1 is turned on.
XAO the operation of the circuit 30 is: XAO circuit 30 receives the signal from switch selection circuit 20 and outputs clock signal CLK, which is used to drive the GOA circuit.
The embodiment of the invention provides a level processing circuit, which comprises a voltage detection circuit 10, a switch selection circuit 20, and a switch selection circuit XAO circuit 30. Under low temperature environment, the voltage detection circuit 10 outputs low level VGL to the switch selection circuit 20 to control the first sub-switch 2 to be turned on, and since the first sub-switch 2 is further connected in series with a first resistor R1, after the shutdown, the liquid crystal equivalent capacitor C in the display panelLCAnd a storage capacitor CSThe thin film transistor keeps longer discharge time to solve the problem of static electricity residue and further solve the image quality problems such as LPS cross striation.
Optionally, the level processing circuit further includes an amplifying circuit 40; the amplifier circuit 40 is coupled to the first signal terminal CLK-I, the output terminal LVG-H of the switch selection circuit 20, the low voltage terminal LVG-L, and the input terminal of the XAO circuit 30.
In some embodiments, the amplifying circuit 40 includes a first capacitor C2, a second capacitor C3, a first transistor Q1, a second transistor Q2; the first capacitor C2 is connected to the first signal terminal CLK-I and the gate of the first transistor Q1.
A first pole of the first transistor Q1 is connected to the output of the switch selection circuit 20 and a second pole is connected to the input of the XAO circuit 30. The second capacitor C3 is connected to the first signal terminal CLK-I and the gate of the second transistor Q2. A first pole of the second transistor Q2 is coupled to the low voltage terminal LVG-L and a second pole is coupled to an input of the XAO circuit 30.
The first pole of the first transistor Q1 and the second transistor Q2 may be a source, and the second pole may be a drain; alternatively, the first pole of the first transistor Q1 and the second pole of the second transistor Q2 may be the drain, and the second pole may be the source.
In the embodiment of the present invention, the voltage inputted to the XAO circuit 30 is amplified to a voltage suitable for the display of the display panel by the amplifying circuit 40, so as to ensure the normal display of the display panel. The embodiment of the invention also provides a GOA circuit. As shown in fig. 5, the GOA circuit includes a shift register 50 and the level processing circuit according to any of the embodiments described above. The shift register 20 includes a plurality of shift register units cascaded, each of which includes an output circuit connected to one or more gate lines of a thin film transistor in the display panel to supply a gate scan signal to the gate lines at a predetermined timing. Taking the display panel as an example of a liquid crystal display panel, the source of the thin film transistor is connected to the data line Vdata, and the drain is electrically connected to the pixel electrode.
Here, the display panel may be a liquid crystal display panel, an organic light-Emitting Diode (OLED) display panel, or the like. The OLED display panel at least comprises a switch transistor, a driving transistor and a storage capacitor.
If the display panel is an OLED display panel, the output circuit is connected with the grid electrode of the switch transistor in the display panel.
The embodiment of the present invention further provides a GOA circuit, which includes a level processing circuit, where the level processing circuit includes a voltage detection circuit 10, a switch selection circuit 20, and an XAO circuit 30. Under low temperature environment, the voltage detection circuit 10 outputs low level VGL to the switch selection circuit 20 to control the first sub-switch 2 to be turned on, and since the first sub-switch 2 is further connected in series with a first resistor R1, after the shutdown, the liquid crystal equivalent capacitor C in the display panelLCAnd a storage capacitor CSMaintaining a longer discharge through a thin film transistorMeanwhile, the problem of static electricity residue is solved, and the image quality problems such as LPS horizontal stripes are further solved.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A level processing circuit is characterized by comprising a voltage detection circuit, a switch selection circuit and an XAO circuit;
the voltage detection circuit is configured to: if the first voltage is greater than or equal to the second voltage, outputting a high level to the switch selection circuit; if the first voltage is lower than the second voltage under the condition that the temperature is lower than or equal to-5 ℃, outputting a low level to the switch selection circuit;
the switch selection circuit comprises a first switch and a second switch which are connected in parallel, and the second switch comprises a first sub-switch and a first resistor which are connected in series; the switch selection circuit is configured to: if the voltage detection circuit outputs a high level, the first switch is opened, and the high level is output to the XAO circuit; if the voltage detection circuit outputs a low level, the first sub-switch is turned on, and the low level is output to the XAO circuit.
2. Level processing circuit according to claim 1,
the voltage detection circuit comprises a first input circuit, a second input circuit and a comparator;
the first input circuit is connected with a first voltage end, a second voltage end and a first node;
the second input circuit is connected with the first voltage end, the second voltage end and a second node;
the comparator is connected to the first node, the second voltage terminal, a digital voltage source, and the switch selection circuit.
3. Level processing circuit according to claim 2,
the first input circuit comprises a second resistor and a third resistor;
the second resistor is connected with the first voltage end and the first node;
the third resistor is connected with the second voltage end and the first node.
4. Level processing circuit according to claim 2,
the second input circuit comprises a fourth resistor, a fifth resistor, a sixth resistor and a voltage stabilizer;
the fourth resistor is connected with the third node and is connected with the second node through a fourth node;
the fifth resistor is connected with the third node and the second voltage end;
the sixth resistor is connected with the first voltage end and the second node through the fourth node;
the voltage stabilizer is connected with the fourth node and the second voltage end.
5. The circuit of claim 4, wherein the voltage of the voltage regulator is 60% to 80% of the voltage of the first voltage terminal.
6. The level processing circuit according to any of claims 1-5, wherein the level processing circuit further comprises an amplifying circuit;
the amplifying circuit is connected with a first signal end, the output end of the switch selection circuit, a low voltage end and the input end of the XAO circuit.
7. The level processing circuit according to claim 6, wherein the amplifying circuit comprises a first capacitor, a second capacitor, a first transistor, a second transistor;
the first capacitor is connected with the first signal end and the grid electrode of the first transistor;
a first pole of the first transistor is connected with the output end of the switch selection circuit, and a second pole of the first transistor is connected with the input end of the XAO circuit;
the second capacitor is connected with the first signal end and the grid electrode of the second transistor;
the first pole of the second transistor is connected with the low voltage end, and the second pole of the second transistor is connected with the input end of the XAO circuit.
8. A gate driver circuit comprising a shift register, a level processing circuit according to any one of claims 1 to 7;
the shift register is connected with the level processing circuit to receive the clock signal processed by the level processing circuit.
9. A display device comprising the gate driver circuit according to claim 8.
10. The display device according to claim 9, further comprising a display panel including a plurality of gate lines;
the gate driving circuit is connected to at least one gate line.
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| CN105845069A (en) * | 2016-06-17 | 2016-08-10 | 京东方科技集团股份有限公司 | Shutdown residual shadow elimination circuit and driving method thereof and display device |
| CN106952628A (en) * | 2017-05-05 | 2017-07-14 | 惠科股份有限公司 | Ghost eliminating circuit and display device |
| CN107424577A (en) * | 2017-08-15 | 2017-12-01 | 京东方科技集团股份有限公司 | A kind of display driver circuit, display device and its driving method |
| CN107784990A (en) * | 2017-10-31 | 2018-03-09 | 京东方科技集团股份有限公司 | Charging method, electric discharge regulation circuit and the display device of liquid crystal display panel |
| CN108510932A (en) * | 2018-03-30 | 2018-09-07 | 京东方科技集团股份有限公司 | A kind of electrical level transferring chip and its control method, shutdown driving circuit |
| CN108962119A (en) * | 2018-08-01 | 2018-12-07 | 京东方科技集团股份有限公司 | Level shifter and its driving method, display device |
| CN109785788A (en) * | 2019-03-29 | 2019-05-21 | 京东方科技集团股份有限公司 | Level processing circuit, gate driving circuit and display device |
| CN110599977A (en) * | 2019-09-18 | 2019-12-20 | 福州京东方光电科技有限公司 | Shutdown ghost eliminating circuit and display device |
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