KR20060093165A - Semiconductor device having a recessed channel and method of manufacturing the same - Google Patents

Abstract

Disclosed are a semiconductor device having a recessed channel with improved electrical characteristics and a method of manufacturing the same. After forming a trench in the substrate, a gate oxide film is formed on the bottom and inner walls of the trench. After forming a characteristic improving member that surrounds the upper portion of the inner wall of the trench on the gate oxide layer, a gate electrode protruding to the upper portion of the substrate while filling the trench is formed. The characteristic improving member derived from the impurity region formed by the gradient ion implantation process greatly improves the characteristics of the semiconductor device, such as reducing the gate induced drain leakage current and improving the static recovery characteristic.

Description

Semiconductor device having a recessed channel and Method of manufacturing the same

1A and 1B are cross-sectional views illustrating a conventional method of manufacturing a transistor having a recessed channel.

2 is a cross-sectional view of a semiconductor device having a recessed channel according to the present invention.

3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recessed channel according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100: semiconductor substrate 103: first trench

105: device isolation layer 110: first layer

112: first layer pattern 120: second layer

122: second layer pattern 125: first mask pattern

127: Etched second layer pattern 128: Second mask pattern

130: photoresist pattern 140: second trench

143: first impurity region 145: gate oxide film

147: Preliminary characteristic improvement member 150: Characteristic improvement member

155: gate electrode 160: gate mask

165. 170: source / drain region 175: gate spacer

180: interlayer insulation film 185: first pad

190: Second pad

TECHNICAL FIELD The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a transistor having a recessed channel and a method of manufacturing the same.

As the semiconductor memory device is highly integrated, the size of the active region is reduced, and the channel length of the transistor formed in the active region is also reduced. In general, when the channel length of a transistor decreases, the influence of the source / drain on the electric field or potential in the channel region of the transistor becomes remarkable. This phenomenon is called a short channel effect. A transistor having a recessed channel has been developed as one of methods for maximizing the performance of devices formed on a substrate while preventing the short channel effect. For example, Korean Patent Laid-Open Publication No. 2002-0059817 discloses a transistor having a recessed channel.

1A and 1B are cross-sectional views illustrating a method of manufacturing a transistor having a conventional recessed channel disclosed in the Korean Patent Application.

Referring to FIG. 1A, a silicon nitride layer 15 and a silicon oxide layer 20 are sequentially formed on a silicon substrate 10, and then the silicon nitride layer 15 and the silicon oxide layer 20 are etched masks. The silicon substrate 10 is partially etched using the trench to form a trench 25 having a predetermined dimension in the silicon substrate 10.

Next, a polysilicon layer 30 is formed on the silicon substrate 10 to partially fill the inside of the trench 25 to form a channel region.

Referring to FIG. 1B, after the silicon nitride layer 15 and the silicon oxide layer 20 are removed from the silicon substrate 10, a sacrificial layer (not shown) is formed on the inner wall of the trench 25.

Subsequently, an ion is implanted into the silicon substrate 10 in contact with the inner wall of the trench 25 through the sacrificial layer to form a source / drain region (not shown) adjacent to the inner wall of the trench 25. .

Next, after the gate oxide film 35 is formed on the inner wall of the trench 25 and the polysilicon layer 30, a gate electrode (not shown) for filling the trench 25 on the gate oxide film 35 is formed. Form.

However, in the transistor having the recessed channel described above, the gate induced drain leakage due to direct tunneling between the gate electrode and the drain region is increased because the gate to N junction overlap region of the gate electrode is increased. Drain Leakage (GIDL) current has a problem that increases. In particular, in the case of a transistor having a recessed channel, a gate induced drain leakage (GIDL) current is mainly generated at a portion where the substrate is in contact with the gate electrode where the electric field is concentrated, as shown in 'A' of FIG. 1B. do. This gate induced drain leakage (GIDL) current causes a problem of greatly deteriorating the static recovery characteristic, which is an important characteristic of semiconductor devices such as DRAM devices having recessed channels.

It is a first object of the present invention to provide a semiconductor device having a recessed channel with improved electrical characteristics such as gate induced drain leakage current and static recovery characteristics.

It is a second object of the present invention to provide a method of manufacturing a semiconductor device which is particularly suitable for a semiconductor device having a recessed channel having improved gate induced drain leakage current and static recovery characteristics of the semiconductor device.

In order to achieve the first object of the present invention described above, according to a preferred embodiment of the present invention, a gate electrode partially embedded in a semiconductor substrate, a gate oxide film formed on the gate electrode of the embedded portion, the gate electrode is There is provided a semiconductor device including a characteristic improving member surrounding a portion in contact with a semiconductor substrate, and a source / drain region adjacent to the characteristic improving member and the gate oxide film.

In order to achieve the above-described second object of the present invention, in the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention, a trench is formed in a semiconductor substrate, and then a gate oxide film is formed on the bottom and inner walls of the trench. do. Subsequently, after forming a characteristic improving member enclosing an upper portion of the inner wall of the trench on the gate oxide layer, a gate electrode protruding above the semiconductor substrate is formed while filling the trench. Next, a source / drain region adjacent to the gate electrode is formed. Here, after forming a first mask pattern on the semiconductor substrate, the trench is formed by partially etching the semiconductor substrate using the first mask pattern as an etching mask. In the forming of the characteristic improving member, the first mask pattern is partially etched to form a second mask pattern, and the semiconductor is formed around the upper portion of the inner wall of the trench by using the second mask pattern as an ion implantation mask. Impurity regions are implanted by impurity implantation into the substrate. Subsequently, the second mask pattern is removed, a preliminary characteristic improving member is formed in the impurity region while forming a gate oxide film on the bottom and inner walls of the trench and the semiconductor substrate, and then the gate oxide film and the substrate on the semiconductor substrate. The upper part of the preliminary property improving member is removed.

According to the present invention, by forming a characteristic improving member that surrounds the gate electrode centered around the part where the gate electrode partially embedded in the substrate is in contact with the substrate, causing the gate caused by the concentration of an electric field in the part where the gate electrode is in contact with the substrate Drain leakage (GIDL) current can be significantly reduced. In addition, since the characteristic improving member is formed around the gate electrode of the buried structure, it is possible to prevent the occurrence of dielectric breakdown in the substrate around the gate electrode even when a high voltage is applied to the gate electrode. Furthermore, since the characteristic improving member is formed together during the process of forming the gate oxide film, an additional additional process for forming the characteristic improving member is not required. Therefore, electrical characteristics such as static recovery characteristics and leakage current characteristics of a semiconductor device having such a gate electrode and a characteristic improving member can be greatly improved.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited or limited by the following embodiments.

2 is a cross-sectional view of a semiconductor device having a recessed channel according to an embodiment of the present invention.

Referring to FIG. 2, the semiconductor device is adjacent to a gate electrode 155 partially filled in an active region of the semiconductor substrate 100, a gate mask 160 formed on the gate electrode 155, and a gate electrode 155. A gate spacer 175 covering the source / drain regions 165 and 170, the gate mask 160 and the gate electrode 155, and a gate oxide layer 145 surrounding the gate electrode 155 embedded in the semiconductor substrate 100. And a characteristic improving member 150 embedded in the semiconductor substrate 100 on the gate oxide layer 145 to surround a portion of the gate electrode 155 which contacts the semiconductor substrate 100. Here, the gate electrode 155, the gate mask 160, and the gate spacer 175 together form a gate structure.

An isolation layer 105 is formed on the semiconductor substrate 100 to divide the semiconductor substrate 100 into an active region and a field region. The gate electrode 155 generally has a recessed structure in which a center portion and a bottom portion are buried in the active region of the semiconductor substrate 100. Source / drain regions 165 and 170 are formed in portions of the active region adjacent to the gate electrode 155, respectively. In this case, the depth of the source / drain regions 165 and 170 is formed to be shallower than the depth of the gate electrode 155 embedded in the semiconductor substrate 100.

A gate oxide film 145 is formed on the gate electrode 155 embedded in the semiconductor substrate 100. That is, the gate oxide layer 145 is formed between the source / drain regions 165 and 170 and the gate electrode 155. Accordingly, the channel region is formed in the active region around the gate electrode 155 positioned under the source / drain regions 165 and 170. In other words, according to the gate electrode 155 having the recessed structure, the channel region is also recessed to a predetermined depth from the surface of the semiconductor substrate 100 by the depth of the gate electrode 155.

In the semiconductor substrate 100 at a portion where the gate electrode 155 is in contact with the semiconductor substrate 100, a characteristic improving member 150 is formed to surround the gate electrode 155. The characteristic improving member 150 is positioned between the upper portion of the gate oxide film 145 and the surface region of the semiconductor substrate 100 to prevent a current from leaking from the gate electrode 155. In a conventional semiconductor device having a recessed gate electrode, as described above, an electric field is concentrated at a portion where the surface of the semiconductor substrate is in contact with the gate electrode, so that a leakage current is generated from the gate electrode. On the other hand, according to the present invention, since the characteristic improving member 150 is formed to surround the gate electrode 155 in a portion in contact with the semiconductor substrate 100, the phenomenon that leakage current is generated from the gate electrode 155 is fundamentally prevented. In addition, even when a high voltage is applied to the gate electrode 155, an insulation breakdown phenomenon may be prevented from occurring around the gate electrode 155. Accordingly, the electrical characteristics of the semiconductor device can be greatly improved.

First and second pads 185 and 190 are formed on the source / drain regions 165 and 170 formed in the active region, respectively. The first and second pads 185 and 190 are formed through the interlayer insulating layer 180 formed on the gate structure.

3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recessed channel according to an embodiment of the present invention. 3A to 3H, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 3A, a first trench 103 having a first depth is used to divide the substrate 100 into an active region and a field region by using an isolation process in a semiconductor substrate 100 such as a silicon wafer. ). For example, the first trench 103 is formed by partially etching the semiconductor substrate 100 using a shallow trench element isolation (STI) process. Specifically, the first trench 103 is formed in the semiconductor substrate 100 by etching a predetermined portion of the semiconductor substrate 100 through a dry etching process using an etching gas for etching silicon. Subsequently, a first oxide film (not shown) is formed on the semiconductor substrate 100 while filling the first trench 103, and then the first oxide film is partially removed to fill the first trench 103. The separator 105 is formed. The device isolation film 105 is formed using a chemical mechanical polishing (CMP) process, an etch back process, or a process combining chemical mechanical polishing and etch back.

When the device isolation layer 105 is formed to fill the first trench 103, the active region and the field region are defined in the semiconductor substrate 100.

The mask layer 123 including the first layer 110 and the second layer 120 is formed on the semiconductor substrate 100 on which the device isolation layer 105 is formed. The first layer 110 is made of an oxide such as medium temperature oxide (MTO), and the second layer 120 is made of an oxynitride such as silicon oxynitride or a nitride such as silicon nitride. Here, the first layer 110 is formed to a relatively thin thickness than the second layer 120. The mask layer 123 may serve as an etching mask during an etching process for forming the second trenches 140 (see FIG. 3C).

Referring to FIG. 3B, a photoresist film is coated on the mask layer 123, and then the photoresist film is exposed and developed to define a region in which the second trenches 140 are to be formed on the mask layer 123. The resist pattern 130 is formed. In this case, the second trenches 140 are formed in the active region.

The first mask pattern 125 is formed on the semiconductor substrate 100 by etching the mask layer 123 using the photoresist pattern 130 as an etching mask. In more detail, the second layer 120 and the first layer 110 are sequentially etched using the photoresist pattern 130 as an etching mask, thereby forming the first layer pattern 112 on the semiconductor substrate 100. ) And a first mask pattern 125 including the second layer pattern 122. Here, the first mask pattern 125 exposes portions of the active region where the second trenches 140 are to be formed.

Referring to FIG. 3C, the photoresist pattern 130 is removed through an ashing and / or strip process, and then the semiconductor substrate 100 is partially etched using the first mask pattern 125 as an etch mask, thereby forming the active layer. Form second trenches 140 having a second depth in the region. Preferably, the second trenches 140 are etched by a dry etching process for etching silicon. Here, the second depth of the second trench 140 has a relatively smaller value than the first depth of the first trench 103. For example, the second trench 140 has a second depth of about 1,500 to 2,000 mm 3.

During the etching process of forming the second trenches 140 in the active region, the second layer pattern 127 of the first mask pattern 125 is also partially etched. Accordingly, when the second trenches 140 are formed in the active region, the second mask pattern 128 including the first layer pattern 112 and the etched second layer pattern 127 on the semiconductor substrate 100. ) Is formed. In this case, the thickness t of the second mask pattern 128 is about 1 to 1.5 times the width w of the second trench 140. That is, the ratio of the thickness t of the second mask pattern 128 to the width w of the second trench 140 is about 1: 1.0 to about 1.5. The relationship between the width w of the second trench 140 and the thickness t of the second mask pattern 128 will be described later.

Referring to FIG. 3D, a first impurity region 143 is formed by implanting a first impurity into the active region forming an upper portion of the sidewall of the second trench 140 through a first ion implantation process. Specifically, using the second mask pattern 128 as an ion implantation mask, the first impurity is implanted at an angle of about 20 to about 50 microns with respect to the semiconductor substrate 100, and the first impurity concentration in the active region is obtained. A first impurity region 143 having a portion is formed. Here, the first impurity includes nitrogen (N), phosphorus (P), arsenic (As), or fluorine (F), and is injected at an energy of about 1 to 10 keV. Therefore, the first impurity concentration of the first impurity region 143 is about 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ atoms / cm 2.

In the first ion implantation process for forming the first impurity region 143, the thickness t of the second mask pattern 128 is about 1 to 1.5 times greater than the width w of the second trench 140. The first impurity is inclinedly injected at an angle of about 20 to about 50 microns with respect to the semiconductor substrate 100 because of its magnitude. That is, by adjusting the thickness t of the second mask pattern 128, the angle at which the first impurity is injected into the active region may be adjusted. Accordingly, the first impurity region 143 has a first impurity concentration only in the active region under the first mask pattern 128 by not implanting the first impurity into the active region of the portion where the channel is to be subsequently formed. Can be formed accurately. As described later, the first impurity region 143 serves to induce the formation of the characteristic improving member 150 surrounding the upper portion of the inner wall of the second trench 140.

Referring to FIG. 3E, as described above, the first impurity region 143 adjacent to the upper portion of the second trench 140 is formed, and then the second trenches 140 are etched through the cleaning process. The edges of the silicon fences and the device isolation layer 105 and / or the substrate 100 formed at the periphery of the upper portions of the trenches 140 are removed. Here, the silicon fence is a portion of the semiconductor substrate 100 protruding in a sharp shape around the upper portion of the second trenches 140 while etching the semiconductor substrate 100 to form the second trenches 140. Say that. The cleaning process is carried out using a SC-1 (Standard Cleaning-1) solution. When the cleaning process is performed using the SC-1 solution, the etched second layer pattern 127 of the second mask pattern 128 is removed and the first layer pattern 112 is also partially removed.

After the first layer pattern 112 remaining on the semiconductor substrate 100 is completely removed through an etching process, a gate oxide layer 145 is formed on the active region using a thermal oxidation process or a chemical vapor deposition process. The gate oxide layer 145 is formed on the bottom and inner walls of the second trenches 140 and the surface of the active region. At this time, the first impurity region 143 doped with the first impurity is oxidized faster than other portions of the substrate 100 to form a preliminary characteristic improving member 147 thicker than the gate oxide layer 145.

According to an embodiment of the present invention, the first impurity region 143 doped with the first impurity is formed while the semiconductor substrate 100 is oxidized using the thermal oxidation process to form the gate oxide layer 145 in the active region. ) Is oxidized at a faster rate than other portions of the substrate 100 containing only silicon, so that the preliminary characteristic improving member 147 having a thickness thicker than the gate oxide layer 145 is formed on the inner walls of the second trenches 140. Is formed. In this case, the first impurity region 143 induces formation of the preliminary characteristic improving member 147.

According to another embodiment of the present invention, the gate oxide film 145 is first formed on the active region without forming the first impurity region 143, and then a chemical vapor deposition process, a high density plasma chemical vapor deposition process, and a plasma are formed. The preliminary characteristic improving member 147 may be formed on the inner wall of the second trenches 140 through an enhanced chemical vapor deposition process or an atomic layer deposition process. In this case, the gate insulating layer 145 and the preliminary characteristic improving member 147 may be made of a metal oxide such as silicon oxide, silicon oxynitride or tantalum oxide, titanium oxide, aluminum oxide or hafnium oxide.

Referring to FIG. 3F, the gate oxide layer 145 formed on the active region except for the gate oxide layer 145 positioned on the inner wall and the bottom of the second trenches 140 is removed. In this case, the gate oxide film 145 is partially removed using a wet etching process, a dry etching process, a chemical mechanical polishing process, or an etch back process.

While the gate oxide layer 145 on the surface of the active region is removed, the upper part of the preliminary characteristic improving member 147 is partially removed, thereby completing the characteristic improving member 150 surrounding the upper sidewalls of the second trenches 140. do.

Referring to FIG. 3G, a gate conductive layer and a gate mask layer are sequentially formed on the semiconductor substrate 100 while filling the second trenches 140, and then using the photolithography process, the gate mask layer and the gate conductive layer are formed. By sequentially etching the film, the gate electrode 155 having the lower portion embedded in the second trench 140 is formed, and the gate mask 160 is formed on the gate electrode 155. The gate electrode 155 is made of a conductive material such as doped polysilicon, conductive metal nitride or metal. In addition, the gate electrode 155 may have a polyside structure including the conductive material and the metal silicide. On the other hand, the gate mask 160 is formed using a nitride such as silicon nitride or an oxynitride such as silicon oxynitride.

According to another exemplary embodiment, the gate mask layer is first patterned to form a gate mask 160 on the gate conductive layer, and then the gate conductive layer is etched using the gate mask 160 as an etching mask. As a result, the gate electrode 155 partially embedded in the second trench 140 may be formed.

Referring to FIG. 3H, the semiconductor substrate 100 exposed between the gate electrodes 155 may have a second impurity concentration through a second ion implantation process using the gate electrode 155 and the gate mask 160 as an ion implantation mask. By implanting the second impurity and performing a heat treatment process, source / drain regions 165 and 170 which are second impurity regions are formed. Here, the second impurity concentration of the source / drain regions 165 and 170 is higher than the first impurity concentration of the first impurity region 143. For example, the source / drain regions 165 and 170 which are the second impurity regions have a second impurity concentration of about 1.0 × 10 ^{15 to} 1.0 × 10 ¹⁷ atoms / cm 2.

After forming an insulating film on the semiconductor substrate 100 while covering the gate mask 160, the insulating film is etched to cover the gate mask 160 and the gate electrode 155 to cover the second and third impurity regions 165. A gate spacer 175 exposing 170 is formed. The gate spacer 175 is formed by an anisotropic etching process using a nitride such as silicon nitride.

An interlayer insulating layer 180 is formed to cover the exposed second and third impurity regions 165 and 170 and the gate spacer 175. The interlayer insulating layer 180 is made of oxides such as TEOS, PE-TEOS, USG, SOG, HDP-CVD oxide, and BPSG to PSG. The interlayer insulating layer 180 is formed using a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, or a high density plasma chemical vapor deposition process.

By partially etching the interlayer insulating layer 180 through a photolithography process, contact holes exposing the second and third impurity regions 170 are formed, and then conductive is formed on the interlayer insulating layer 180 while filling the contact holes. To form a film. The conductive film is formed using a metal, doped polysilicon or conductive metal nitride.

The conductive film is partially removed through a chemical mechanical polishing process, an etch back process, or a combination of chemical mechanical polishing and etch back to form first and second pads 185 and 190 filling the contact hole. The first and second pads 185 and 190 are in contact with the source / drain regions 165 and 170, respectively. In this case, the first and second pads 185 and 190 are formed while being self-aligned with respect to the gate spacer 175.

According to the present invention, by forming a characteristic improving member that surrounds the gate electrode centered around the part where the gate electrode partially embedded in the substrate is in contact with the substrate, causing the gate caused by the concentration of an electric field in the part where the gate electrode is in contact with the substrate Drain leakage (GIDL) current can be significantly reduced.

In addition, since the characteristic improving member is formed around the gate electrode of the buried structure, it is possible to prevent the occurrence of dielectric breakdown in the substrate around the gate electrode even when a high voltage is applied to the gate electrode.

Furthermore, since the characteristic improving member is formed together during the process of forming the gate oxide film, an additional additional process for forming the characteristic improving member is not required.

Therefore, electrical characteristics such as static refresh characteristics and leakage current characteristics of a semiconductor device having such a gate electrode and a characteristic improving member can be greatly improved.

As described above, the present invention has been described with reference to the preferred embodiments, but those skilled in the art can variously modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that it can be changed.

Claims (14)

A gate electrode partially embedded in the semiconductor substrate; A gate oxide film formed on the gate electrode of the buried portion; A characteristic improving member surrounding the portion where the gate electrode contacts the semiconductor substrate; And And a source / drain region adjacent to the characteristic improving member and the gate oxide film. The semiconductor device according to claim 1, wherein said characteristic improving member comprises an oxide. The semiconductor device according to claim 2, wherein said characteristic improving member and said gate oxide film contain the same oxide. The semiconductor device according to claim 2, wherein the characteristic improving member is formed from silicon doped with impurities. The semiconductor device according to claim 4, wherein the impurity comprises nitrogen, phosphorus, arsenic or fluorine. The semiconductor device according to claim 1, wherein said characteristic improving member has a thickness thicker than said gate oxide film. Forming a trench in the semiconductor substrate; Forming a gate oxide layer on the bottom and inner walls of the trench; Forming a characteristic improving member surrounding the upper portion of the inner wall of the trench on the gate oxide layer; Forming a gate electrode protruding above the semiconductor substrate while filling the trench; And Forming a source / drain region adjacent the gate electrode. The method of claim 7, wherein forming the trench, Forming a first mask pattern on the semiconductor substrate; And And partially etching the semiconductor substrate using the first mask pattern as an etching mask. The method of claim 8, wherein the forming of the characteristic improving member comprises: Partially etching the first mask pattern to form a second mask pattern; Using the second mask pattern as an ion implantation mask to form an impurity region by inclining ions into the semiconductor substrate around the upper portion of the inner wall of the trench; Removing the second mask pattern; Forming a preliminary characteristic improving member in the impurity region while forming a gate oxide film on the bottom and inner walls of the trench and the semiconductor substrate; And And removing an upper portion of the gate oxide film and the preliminary characteristic improving member on the semiconductor substrate. 10. The method of claim 9, wherein the inclination ion implantation angle of the impurity is determined according to a ratio of the thickness of the second mask pattern and the width of the trench. The method of manufacturing a semiconductor device according to claim 10, wherein the ratio of the thickness of the second mask pattern to the width of the trench is 1: 1.0 to 1.5. The method for manufacturing a semiconductor device according to claim 10, wherein the inclination ion implantation angle of the impurity is 20 to 50 degrees with respect to the semiconductor substrate. 10. The method of claim 9, wherein the gate oxide film and the property improving member are formed by a thermal oxidation process. The method for manufacturing a semiconductor device according to claim 9, wherein the concentration of the impurity is 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ atoms / cm 2.

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