KR20060077157A - Cell of nonvolatile memory device and method for manufacturing the same, and method for manufacturing semiconductor device using the same - Google Patents

Abstract

According to the present invention, a cell operating margin of a memory device is increased by preventing program efficiency from being reduced due to a buzz beak phenomenon at both sides of a tunnel oxide layer, and thereby, a cell of a nonvolatile memory device capable of preventing a device malfunction. It relates to a manufacturing method. To this end, in the present invention, a substrate, a control gate in which a predetermined portion is spaced apart from each other by a predetermined distance and a groove formed in a longitudinal direction, a first dielectric layer formed on each of the control gate, and the groove in the groove direction. A second dielectric film formed on each sidewall of the first dielectric film and the control gate, a tunnel oxide film formed on the substrate exposed between the second dielectric film, the first and second dielectric films so as to fill the groove; A cell of a nonvolatile memory device including a connected floating gate and a source / drain region formed in the substrate exposed to one side of the control gate is provided.

Nonvolatile Memory Devices, EEPROMs, Logic Devices, Buzz Beek, Tunnel Oxides

Description

A cell of a nonvolatile memory device and a method of manufacturing the same, and a method of manufacturing a semiconductor device using the same TECHNICAL FIELD             

1 is a cross-sectional view showing a cell formed by a method of manufacturing a nonvolatile memory device according to the prior art.

2 is a cross-sectional view illustrating a cell of a nonvolatile memory device according to a preferred embodiment of the present invention.

3A to 3N are cross-sectional views illustrating a cell manufacturing method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110 semiconductor substrate 111 device isolation film

112, 112a: gate insulating film 113: first polysilicon film

113a: control gates 114, 116, 120, 123, 129: oxide film

115, 121: nitride film 127: tunnel oxide film

128: second polysilicon film 128a: floating gate

130: hard mask 132: photoresist pattern

133: gate electrode 135: LDD region

137: DDD region 138a, 138b: spacer

140a, 140b: source / drain regions

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell of a nonvolatile memory device (NVM), a method of manufacturing the same, and a method of manufacturing a semiconductor device using the same, and in particular, an electrically pyrasable programmable read-only that is implemented in a chip together with a logic device. Memory, EEPROM) cell and a method of manufacturing the same, and a method of manufacturing a semiconductor device using the same.

The semiconductor memory device may be classified into a volatile memory device and a nonvolatile memory device. Volatile memory devices lose their data when their power supplies are interrupted, such as DRAM (Dynamic Random Access Memory) devices and static RAM (SRAM) devices. Nonvolatile memory devices include memory devices that retain data of the memory device even when a power supply is cut off, such as EEPROM devices and flash devices.

In general, cells of nonvolatile memory devices such as EEPROM devices and flash memory devices have a stacked gate structure that is advantageous for high integration. The stacked gate structure includes a tunnel oxide film, a floating gate, a dielectric film, and a control gate stacked on a semiconductor substrate.

Program operation in such a nonvolatile memory device is performed by F-N tunneling (Fowler-nordheim tunneling) method and hot electron injection (hot electron injection) method. The F-N tunneling method is a method in which a program operation is performed by applying a high electric field to a gate insulating film to inject electrons into a floating gate from a semiconductor substrate. The hot electron injection method is a method in which a hot electron generated in a channel region near a drain is injected into a floating gate to perform a program operation. Meanwhile, an erase operation of the nonvolatile memory device is performed by releasing electrons injected into the floating gate into the semiconductor substrate or the source through a program operation.

Hereinafter, a cell of a conventional nonvolatile memory device and a method of manufacturing the same will be described with reference to FIG. 1.

As illustrated in FIG. 1, a shallow trench isolation (STI) process is performed to form the device isolation layer 11 in a field region of the substrate 10. Then, a gate electrode composed of the tunnel oxide film 12, the floating gate 13, the dielectric film 14, and the control gate 15 is formed in an active region defined by the device isolation film 11. Then, an LDD (Lightly Doped Drain) ion implantation process is performed to form the LDD region 16 on the substrate 10. Thereafter, spacers 17 are formed on both sidewalls of the gate electrode, and a source / drain ion implantation process is performed to form source / drain regions 18 on the substrate 10.

However, in the cell structure and manufacturing method of the nonvolatile memory device according to the related art described above, a bird's beak phenomenon in which both sides of the tunnel oxide film 12 swells as shown in FIG. 19 is observed. Occurs. The buzz beak phenomenon spreads from both sides of the tunnel oxide film 12 to the center portion. As a result, the central portion of the tunnel oxide film 12 is grown thick. This phenomenon occurs because of the process of forming the dielectric film 14 having the structure of ONO (Oxide / Nitride / Oxide), in particular, the floating gate 13 during a high temperature (over 800 ° C.) thermal oxidation process for forming an oxide film as a lower layer. It is known that oxygen penetrates along both sidewalls.

As described above, when a buzz beak phenomenon occurs at both sides of the tunnel oxide layer 12, a cell operation margin is monitored by reducing the program efficiency by preventing the introduction of hot electrons injected from the channel region into the floating gate 13 during the program operation. Or cause a malfunction of the device. In particular, as the size of the cell decreases, the main cause of deterioration of cell characteristics is acting.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and prevents the program efficiency from being reduced by the buzz beak phenomenon at both sides of the tunnel oxide film, thereby increasing the cell operating margin of the memory device. Accordingly, an object of the present invention is to provide a cell of a nonvolatile memory device capable of preventing a malfunction of the device and a method of manufacturing the same.

Another object of the present invention is to provide a method of manufacturing a semiconductor device implemented in a chip together with a logic device by using the cell manufacturing method of the nonvolatile memory device.

According to an aspect of the present invention, there is provided a substrate, a control gate in which grooves are formed in a length direction with predetermined portions spaced apart from each other by a predetermined distance on the substrate, and each formed on the control gate. A first dielectric film, a second dielectric film formed on each sidewall of the first dielectric film and the control gate in the groove direction, a tunnel oxide film formed on the substrate exposed between the second dielectric film, and the groove embedded A cell of a nonvolatile memory device may include a floating gate connected to the first and second dielectric layers and a source / drain region formed on the substrate exposed to one side of the control gate.

In addition, the present invention according to another aspect for achieving the above object, the step of sequentially forming an insulating film, a first polysilicon film and a first dielectric film on the substrate, the first dielectric film, the first polysilicon Sequentially etching the film and the insulating layer to form a contact hole exposing a portion of the substrate; forming a second dielectric layer on an inner wall of the contact hole; and etching the second dielectric layer to etch the contact hole. Exposing the substrate through the substrate; forming a tunnel oxide layer on the substrate exposed through the contact hole; depositing a second polysilicon layer to fill the contact hole; and depositing the second polysilicon layer. Etching the first dielectric layer, the first polysilicon layer, and the insulating layer to form a gate electrode, and performing a source / drain ion implantation process The method provides a cell manufacturing method of a nonvolatile memory device including forming a source / drain region on the substrate exposed to both sides of the gate electrode.

According to another aspect of the present invention, there is provided a substrate including a cell region and a logic element region, and sequentially forming an insulating film, a first polysilicon film, and a first dielectric film on the substrate. Forming a contact hole for sequentially etching the first dielectric layer, the first polysilicon layer, and the insulating layer to expose a portion of the substrate; and forming a contact hole on the inner sidewall of the contact hole. Forming a dielectric film, etching the second dielectric film to expose the substrate through the contact hole, forming a tunnel oxide film on the substrate exposed through the contact hole, and filling the contact hole. Depositing a second polysilicon film, forming a hard mask on the second polysilicon film, the logic element region and the cell Etching the hard mask so that a part of the inverse is opened, etching the second polysilicon layer and the first dielectric layer by performing an etching process using the hard mask, and the first region of the logic element region. Forming a gate mask on the polysilicon layer, and performing an etching process using the hard mask and the gate mask to simultaneously form first and second gate electrodes in the cell region and the logic element region, respectively. And forming first and second source / drain regions on the substrate exposed to both sides of the first and second gate electrodes, respectively.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

2 is a cross-sectional view illustrating a cell of a nonvolatile memory device according to a preferred embodiment of the present invention.

Referring to FIG. 2, a cell of a nonvolatile memory device according to an exemplary embodiment of the present invention may include a control gate 113a having a groove recessed in a longitudinal direction so that a portion of the nonvolatile memory device is spaced at a predetermined distance from the semiconductor substrate 110. The first dielectric film 125a formed on the control gate 113a and the second dielectric film 125a formed on the sidewalls of the first dielectric film 125a and the control gate 113a in a direction in which a portion of the control gate 113a is spaced apart from each other. The semiconductor exposed to the side of the control gate 113a and the floating gate 128a connected to the first and second dielectric films 125a and 125b so that the dielectric film 125b and the grooves of the control gate 113a are filled. Source / drain regions 140a formed in the substrate 110. In addition, a tunnel oxide film 127 is formed between the floating gate 128a and the semiconductor substrate 110. In addition, the control gate 113a is integrally formed to be separated from the semiconductor substrate 110 through the gate insulating layer 112a.

Operation characteristics of the cell of the nonvolatile memory device having such a structure will be described.

First, in the program or write operation, a bias condition is a pumping high voltage (Vpp, 16V) in the control gate 113a and a floating, 0V, and substrate 110 in the source / drain region 140a, respectively. ) Is applied 0V. When a bias voltage of approximately 16V is applied to the control gate 113a, the potential of the floating gate 128a is proportional to the capacitance of the first and second dielectric films 125a and 125b, that is, proportional to the coupling ratio. To rise. The coupling ratio is approximately 80 to 85% and when a bias voltage of 16V is applied to the control gate 113a, approximately 13V is induced to the floating gate 128a. When the potential of the floating gate 128a rises, electrons are tunneled through the tunnel oxide film 127 and injected into the floating gate 128a, thereby increasing the threshold voltage of the cell transistor to about 4V. .

In the erase operation, the bias conditions are 0V in the control gate 113a, pumping voltages Vpp and 14V in the substrate 110, and floating and pumping voltages Vpp and 14V in the source / drain region 140a, respectively. ) Is applied. Electrons injected into the floating gate 128a by the pumping voltage Vpp applied to the substrate 110a are tunneled through the tunnel oxide film 127 and are emitted to the substrate 110. As a result, the threshold voltage of the cell transistor is reduced to approximately 1.0V.

During read or verify operation, the bias condition is the control gate 113a functioning as the gate electrode, the power supply voltage Vcc lower than the pumping voltage, 0V and 1V to the source / drain region 140a and the substrate 110, respectively. Apply 0V. In this state, when the cell is programmed and the threshold voltage is increased, no current flows between the source / drain regions 140a, so the cell is off-cell. The current flows into the ON-cell.

Hereinafter, a method of manufacturing a cell of a nonvolatile memory device according to an exemplary embodiment of the present invention shown in FIG. 1 will be described with reference to FIGS. 3A to 3N. Here, a method of manufacturing a semiconductor device in which a transistor of a cell and a logic device according to an exemplary embodiment of the present invention are simultaneously implemented will be described. Here, the region 'A' illustrated in FIGS. 3A to 3N is a region where a cell is formed, and the region 'B' is a region where a logic transistor is formed.

As shown in FIG. 3A, a well region (not shown) is formed in a predetermined region inside the semiconductor substrate 110 by performing a well ion implantation process and an ion implantation process for adjusting the threshold voltage.

Subsequently, a shallow trench isolation (STI) process is performed to form an isolation layer 111 that separates the cell region A and the logic region B. Referring to FIG. Of course, the isolation layer 111 also defines an active region and a field region.

Next, an oxide film 112 serving as a gate insulating film 112b (see FIG. 3N) of the logic transistor is formed on the substrate 110. At this time, the oxide film 112 is formed by a thermal oxidation process.

Subsequently, a polysilicon film 113 (hereinafter referred to as a first polysilicon film) that functions as a control gate 113a and a gate 113b of a logic transistor (see FIG. 3N) is deposited on the oxide film 112. At this time, the polysilicon film 113 is formed of a doped silicon film. For example, in the case of p-type, Si ₂ H ₆ and PH ₃ gas are deposited using a low pressure chemical vapor deposition (LPCVD) method.

Subsequently, a buffer oxide film 114 that functions as a lower layer of the first dielectric film 125a (see FIG. 3N) is formed on the polysilicon film 113. At this time, the buffer oxide film 114 is formed by a thermal oxidation process. Or it forms by CVD method.

Subsequently, a pad nitride film 115 that functions as an intermediate layer of the first dielectric film 125a is deposited on the buffer oxide film 114. In this case, the pad nitride layer 115 is deposited by Chemical Vapor Deposition (CVD), Plasma Enhanced CVD (PECVD) or Atmospheric Pressure CVD (APCVD).

Next, an oxide film 116 is formed on the pad nitride film 115 to function as an upper layer of the first dielectric film 125a. At this time, the oxide film 116 is deposited by a CVD method.

In the above, the buffer oxide film 114, the pad nitride film 115, and the oxide film 116 function as the first dielectric film 125a, while preventing the first polysilicon film 113 from being damaged through a subsequent process. It also plays a role.

Subsequently, as shown in FIG. 3B, after the photoresist is applied on the oxide film 116, an exposure and development process using a photomask is sequentially performed to form a photoresist pattern (not shown).

Subsequently, an etching process 117 using the photoresist pattern is performed to form a contact hole 118 through which a portion of the cell region A is exposed in the semiconductor substrate 110.

Subsequently, a strip process is performed to remove the photoresist pattern.

Subsequently, as illustrated in FIG. 3C, an oxidation process 119 is performed to form the second dielectric films 125b and 125 on the inner wall of the contact hole 118 and the upper surface of the semiconductor substrate 110 of the exposed cell region A. An oxide film 120, which is a lower layer of FIG. 3N, is formed. At this time, the oxidation process 119 is carried out at a temperature of 800 ℃ to 900 ℃ in a thermal oxidation process.

Subsequently, as illustrated in FIG. 3D, a nitride film 121 serving as an intermediate layer of the second dielectric film 125b is deposited on the entire structure where the oxide film 120 is formed. In this case, the nitride film 121 is deposited by CVD, PECVD, or APCVD.

Subsequently, as illustrated in FIG. 3E, the etching process 122 is performed by a blanket or etch back method so that the nitride film 121 is left only on the inner wall of the contact hole 118.

Subsequently, as illustrated in FIG. 3F, an oxide film 123, which is an upper layer of the second dielectric film 125b, is deposited along the stepped portion of the entire structure including the nitride film 121. At this time, the oxide film 123 is deposited by a CVD method.

Subsequently, as illustrated in FIG. 3G, the etching process 124 is performed by an etch back method to etch the oxide film 123. As a result, the oxide film 123 remains on the sidewall of the nitride film 121 in the contact hole 118, and the cell region A is exposed through the contact hole 118. Of course, the oxide film 116 is also exposed.

Subsequently, as illustrated in FIG. 3H, the cell region A exposed through the contact hole 118 undergoes a thermal oxidation process on the substrate 110 to form a tunnel oxide film 127 for the cell.

Subsequently, a polysilicon film 128 (hereinafter referred to as a second polysilicon film) for the floating gate 128a is deposited on the entire structure to fill the contact hole 118. In this case, the second polysilicon film 128 is formed of a doped silicon film. For example, in the case of p-type, it is deposited by LPCVD using Si ₂ H ₆ and PH ₃ gas.

Subsequently, a buffer oxide film 129 is deposited on the second polysilicon film 128. At this time, the buffer oxide film 129 is deposited by CVD.

Next, the nitride film 130 for a hard mask is deposited on the buffer oxide film 129. In this case, the nitride film 130 is deposited by CVD, PECVD, or APCVD.

Subsequently, as shown in FIG. 3I, after the photoresist is coated on the nitride film 130, a photoresist pattern (not shown) is formed by performing an exposure and development process using a photomask.

Subsequently, an etching process using the photoresist pattern is performed to etch the nitride film 30 first.

Subsequently, a strip process is performed to remove the photoresist pattern.

Subsequently, an etching process 131 using an etched nitride film 30, that is, a hard mask, is performed to expose the upper portion of the first polysilicon film 113 to the buffer oxide film 129, the second polysilicon film 128, The first dielectric film 125a is sequentially etched. Thus, the floating gate 128a is defined.

Subsequently, after the photoresist is applied over the entire structure, an exposure and development process using a photo mask is sequentially performed to form a photoresist pattern 132 that closes only a region where a gate of the logic element region B is to be formed.

Subsequently, as illustrated in FIG. 3K, an etching process using the hard mask 130 and the photoresist pattern 132 is performed to form the gate electrode 133 for the logic transistor in the logic element region B. Referring to FIG. The control gate 113a is defined in the cell region A.

Subsequently, as shown in FIG. 3L, an LDD (Lightly Doped Drain) ion implantation process 134 is performed in the logic element region B to expose the LDD region (or the LDD region) to the substrate 110. 135).

Subsequently, a DDD (Doubled Diffused Drain) ion implantation process 136 is performed in the cell region A to form the DDD region 137 on the substrate 110 exposed to both sides of the control gate 113a. The DDD region 137 increases the breakdown voltage when a high voltage is applied to the drain region.

Subsequently, as shown in FIG. 3M, an insulating film for spacers is deposited on the entire structure including the DDD region 137, and then an etch back process is performed to control the gate 113a, the first dielectric layer 125a, and the floating layer. The spacer 138a covering both side walls of the gate 128a is formed. At the same time. In the logic device region B, spacers 138b are formed to cover both sidewalls of the gate electrode 133. Here, the spacers 138a and 138b are formed in an oxide / nitride stacked structure.

Next, as illustrated in FIG. 3N, the source / drain ion implantation process 139 is performed to form the source / drain region 140a in the DDD region 137. At the same time, a source / drain region 140b deeper than the LDD region 135 is formed in the logic element region B. FIG.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the tunnel oxide film of the cell is formed after the dielectric film is formed, thereby preventing the buzz beak phenomenon of the tunnel oxide film caused by the high temperature applied during the dielectric film forming process, and thereby the program efficiency due to the buzz beak phenomenon. This can be prevented from being reduced. As a result, a cell operation margin of the memory device may be increased to prevent malfunction of the device.

In addition, in the process of manufacturing a semiconductor device that simultaneously implements a cell and a logic transistor, as shown in FIG. 3J, the gate electrode of the cell and the gate electrode of the logic transistor are simultaneously defined using a hard mask and a photoresist pattern. Can simplify the manufacturing process.

Claims (21)

Board; A control gate in which a predetermined portion is spaced apart from each other at a predetermined distance on the substrate to form a groove in a longitudinal direction; First dielectric layers formed on the control gate, respectively; A second dielectric film formed on each sidewall of the first dielectric film and the control gate in the groove direction; A tunnel oxide film formed on the substrate exposed between the second dielectric films; A floating gate connected to the first and second dielectric layers to fill the groove; And Source / drain regions formed on the substrate exposed to one side of the control gate; A cell of a nonvolatile memory device comprising a. The method of claim 1, And the first dielectric layer is formed between the floating gate and the control gate. The method according to claim 1 or 2, And the first and second dielectric layers are formed in an ONO structure. The method according to claim 1 or 2, And the control gate is separated through the substrate and the insulating layer. The method of claim 1, And the source / drain region is formed in a DDD region formed in the substrate. The method of claim 1, And a spacer formed on one sidewall of the floating gate, the first dielectric layer, and the control gate. Sequentially forming an insulating film, a first polysilicon film, and a first dielectric film on the substrate; Sequentially etching the first dielectric layer, the first polysilicon layer, and the insulating layer to form a contact hole exposing a portion of the substrate; Forming a second dielectric layer on an inner wall of the contact hole; Etching the second dielectric layer to expose the substrate through the contact hole; Forming a tunnel oxide layer on the substrate exposed through the contact hole; Depositing a second polysilicon layer to fill the contact hole; Etching the second polysilicon layer, the first dielectric layer, the first polysilicon layer, and the insulating layer to form a gate electrode; And Performing a source / drain ion implantation process to form source / drain regions on the substrate exposed to both sides of the gate electrode; Cell manufacturing method of a nonvolatile memory device comprising a. The method of claim 7, wherein And the first and second dielectric layers are formed in an ONO structure. The method of claim 7, wherein And forming a DDD region on the substrate exposed to both sides of the gate electrode before forming the source / drain region. The method of claim 8, And forming a spacer on both sidewalls of the gate electrode after forming the DDD region. The method of claim 7, wherein the second dielectric film forming step, Performing a thermal oxidation process on an inner wall of the contact hole to form a first oxide film; Depositing a nitride film along a step of an entire structure including the first oxide film, and then leaving the insulating film on sidewalls of the first oxide film through a first etching process; And Depositing a second oxide film along a step of the entire structure including the nitride film and performing a second etching process to leave the second oxide film on sidewalls of the nitride film; Cell manufacturing method of a nonvolatile memory device comprising. The method of claim 11, The first and second etching process is a cell manufacturing method of a non-volatile memory device performed by the etch back process. The method of claim 7, wherein the gate electrode forming step, Sequentially depositing a buffer oxide film and a hard mask on the second polysilicon film; Etching the hard mask; And Etching the second polysilicon layer, the first dielectric layer, the first polysilicon layer, and the insulating layer by performing an etching process using an etched hard mask; Cell manufacturing method of a nonvolatile memory device comprising a. Providing a substrate defined by a cell region and a logic element region; Sequentially forming an insulating film, a first polysilicon film, and a first dielectric film on the substrate; Sequentially etching the first dielectric layer, the first polysilicon layer, and the insulating layer to form a contact hole exposing a portion of the substrate; Forming a second dielectric layer on an inner wall of the contact hole; Etching the second dielectric layer to expose the substrate through the contact hole; Forming a tunnel oxide layer on the substrate exposed through the contact hole; Depositing a second polysilicon layer to fill the contact hole; Forming a hard mask on the second polysilicon film; Etching the hard mask to open portions of the logic device region and the cell region; Etching the second polysilicon layer and the first dielectric layer by performing an etching process using the hard mask; Forming a gate mask on the first polysilicon film in the logic device region; Performing an etching process using the hard mask and the gate mask to simultaneously form first and second gate electrodes in the cell region and the logic element region, respectively; And Forming first and second source / drain regions on the substrate exposed to both sides of the first and second gate electrodes, respectively; Method of manufacturing a semiconductor device comprising a. The method of claim 14, And forming an LDD region on the substrate exposed to both sides of the second gate electrode before forming the second source / drain region in the logic device region. The method of claim 15, And forming spacers on both sidewalls of the second gate electrode after the LDD region is formed. The method of claim 14, Forming a DDD region in the substrate exposed to both sides of the first gate electrode before forming the first source / drain region in the cell region. The method of claim 17, And forming spacers on both sidewalls of the first gate electrode after forming the DDD region. The method of claim 14, And forming a buffer oxide film on the second polysilicon film before depositing the hard mask. The method of claim 14, And the first and second dielectric films are formed in an ONO structure. The method of claim 14, And the second gate electrode comprises the insulating film and the first polysilicon film.

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