KR20060076369A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20060076369A KR20060076369A KR1020040114763A KR20040114763A KR20060076369A KR 20060076369 A KR20060076369 A KR 20060076369A KR 1020040114763 A KR1020040114763 A KR 1020040114763A KR 20040114763 A KR20040114763 A KR 20040114763A KR 20060076369 A KR20060076369 A KR 20060076369A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000002955 isolation Methods 0.000 claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000002019 doping agent Substances 0.000 claims abstract description 5
- 230000007423 decrease Effects 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 문턱전압 감소를 방지할 수 있는 리세스 채널을 갖는 반도체 소자의 제조방법에 관한 것이다. 본 발명은, 반도체 기판 내에 액티브 영역을 한정하는 소자분리막을 형성하는 단계; 상기 소자분리막이 형성된 기판 내에 문턱전압 조절 이온주입을 수행하는 단계; 상기 기판의 액티브 영역 및 소자분리막 일부를 식각하여 단차를 형성하는 단계; 상기 단차부를 포함한 기판 액티브 영역 상에 게이트를 형성하는 단계; 및 상기 게이트 아래의 기판 부분 내에 소실된 도펀트를 보상하기 위해 추가 이온주입을 수행하는 단계;를 포함한다.The present invention relates to a method for manufacturing a semiconductor device having a recess channel capable of preventing a decrease in threshold voltage. The present invention provides a method for forming a semiconductor device, comprising: forming an isolation layer in a semiconductor substrate to define an active region; Performing threshold voltage control ion implantation into the substrate on which the device isolation layer is formed; Etching a portion of the active region and the device isolation layer of the substrate to form a step; Forming a gate on a substrate active region including the stepped portion; And performing additional ion implantation to compensate for dopants lost in the portion of the substrate under the gate.
Description
도 1a 내지 도 1g는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10: 기판 11: 소자분리막10: substrate 11: device isolation film
12: 스크린 산화막 13: 감광막 패턴12: screen oxide film 13: photoresist pattern
14: 게이트 산화막 15: 폴리실리콘막14
16: 텅스텐 실리사이드막 17: 하드마스크 질화막16: tungsten silicide film 17: hard mask nitride film
18: 감광막 패턴 19: 게이트18: photoresist pattern 19: gate
20: 감광막 패턴 21: 추가 이온주입 영역20: photoresist pattern 21: additional ion implantation region
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 문턱전압 감소를 방지할 수 있는 리세스 채널을 갖는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a recess channel capable of preventing a threshold voltage decrease.
반도체 메모리 소자의 고집적화가 급격히 진행됨에 따라, 기존의 평면형 트 랜지스터 구조에서는 셀 지역의 문턱전압 마진 및 리프레쉬 시간 감소로 상당한 어려움을 겪고 있다. 이에, 반도체 메모리 소자의 고집적화에 부합하는 문턱전압을 확보하면서 리프레쉬 특성을 확보하기 위한 다양한 연구들이 활발하게 진행되고 있다.As high integration of semiconductor memory devices proceeds rapidly, the conventional planar transistor structure is experiencing significant difficulties due to reduction of threshold voltage margin and refresh time in the cell region. Accordingly, various studies have been actively conducted to secure refresh characteristics while securing threshold voltages corresponding to high integration of semiconductor memory devices.
이러한 노력의 하나로 최근 STAR(Step-gated asymmetry recess) 셀 구조가 제안되었다. STAR 셀은 액티브 영역의 일부를 리세스시켜 상기 액티브 영역이 단차지도록 만들고, 이렇게 단차진 액티브 영역에 게이트를 형성하여 모스펫(MOSFET) 소자에서의 유효 채널 길이(effective channel length)를 증가시켜 준 구조로서, 단채널효과를 줄여주어 낮은 문턱전압 도우즈(Vt dose)로도 원하는 정도의 문턱전압을 얻을 수 있으며, 아울러, 모스펫 소자에 걸리는 전계를 낮출 수 있어서, 데이터를 갱신하는 리프레쉬 시간을 기존의 평면형 셀 구조에 비해 3배 이상 개선시킬 수 있다.As one of these efforts, a step-gated asymmetry recess (STAR) cell structure has recently been proposed. The STAR cell is a structure in which a portion of the active region is recessed so that the active region is stepped, and a gate is formed in the stepped active region to increase the effective channel length in the MOSFET device. In addition, by reducing the short channel effect, a desired threshold voltage can be obtained even at a low threshold voltage dose (Vt dose), and the electric field applied to the MOSFET element can be reduced, thereby refreshing the refresh time for updating data. It can be improved by three times or more compared to the structure.
특히, 이와 같은 STAR 셀은 기존 공정에 간단한 공정을 추가하거나 변경하여 구현할 수 있으므로, 그 적용이 매우 용이해서 현재로선 반도체 메모리 소자의 고집적화에 따른 문턱전압 마진 및 리프레쉬 시간의 감소 문제를 해결할 수 있는 매우 유용한 방법으로 대두되고 있다.In particular, such a STAR cell can be implemented by adding or changing a simple process to an existing process, and thus is very easy to apply, and can solve the problem of reducing the threshold voltage margin and refresh time caused by high integration of semiconductor memory devices. It is emerging as a useful way.
한편, 종래에는 STAR 셀을 형성함에 있어서, 우선, 기판 내에 소자분리막을 형성하고, 이어서, 문턱전압 조절 이온주입을 실시한 다음, 기판을 리세스시키고 있다. On the other hand, in forming a STAR cell, a device isolation film is first formed in a substrate, and then threshold voltage controlled ion implantation is performed, and then the substrate is recessed.
그런데, 기판을 리세스 시킬때 이미 주입된 문턱전압 조절 이온이 손실되어 문턱전압이 250∼300mV 까지 감소하게 된다. 문턱전압이 감소하면 셀 영역의 펀치 특성이 취약해져서 원하는 소자특성을 얻을 수 없게 된다.However, when the substrate is recessed, the threshold voltage control ions implanted therein are lost and the threshold voltage is reduced to 250 to 300 mV. When the threshold voltage decreases, the punch characteristics of the cell region become weak, so that the desired device characteristics cannot be obtained.
따라서, 본 발명은 상기한 바와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 문턱전압 감소를 방지할 수 있는 리세스 채널을 갖는 반도체 소자의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device having a recess channel capable of preventing a threshold voltage from being reduced.
상기 목적을 달성하기 위한 본 발명은, 반도체 기판 내에 액티브 영역을 한정하는 소자분리막을 형성하는 단계; 상기 소자분리막이 형성된 기판 내에 문턱전압 조절 이온주입을 수행하는 단계; 상기 기판의 액티브 영역 및 소자분리막 일부를 식각하여 단차를 형성하는 단계; 상기 단차부를 포함한 기판 액티브 영역 상에 게이트를 형성하는 단계; 및 상기 게이트 아래의 기판 부분 내에 소실된 도펀트를 보상하기 위해 추가 이온주입을 수행하는 단계;를 포함한다.The present invention for achieving the above object comprises the steps of forming a device isolation film defining an active region in a semiconductor substrate; Performing threshold voltage control ion implantation into the substrate on which the device isolation layer is formed; Etching a portion of the active region and the device isolation layer of the substrate to form a step; Forming a gate on a substrate active region including the stepped portion; And performing additional ion implantation to compensate for dopants lost in the portion of the substrate under the gate.
상기 기판의 액티브 영역 및 소자분리막을 일부 식각하는 단계는 100∼1000Å 두께만큼 식각하여 수행한다.Part of etching the active region and the device isolation layer of the substrate is performed by etching 100 ~ 1000Å thickness.
상기 리세스 채널 영역의 기판 내에 추가 이온주입을 수행하는 단계는 B, BF 및 BF2로 구성된 그룹에서 선택되는 어느 하나를 소스로 사용하여 수행한다.Performing additional ion implantation into the substrate of the recess channel region is performed using any one selected from the group consisting of B, BF and BF2 as a source.
상기 추가 이온주입은 1.0E13∼1.7E13의 도우즈 및 10∼80KeV의 에너지로 수행한다.The further implantation is carried out with a dose of 1.0E13-1.7E13 and an energy of 10-80 KeV.
(실시예) (Example)
이하, 첨부한 도면을 참고하여 본 발명의 바람직한 실시예를 상술하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a를 참조하면, 반도체 기판(10) 내에 액티브 영역을 한정하는 소자분리막(11)을 형성한다. 상기 소자분리막(11)이 형성된 기판(10) 상에 스크린 산화막(12)을 형성하고 문턱전압 조절 이온주입을 수행한다.Referring to FIG. 1A, an
도 1b를 참조하면, 상기 기판 결과물 상에 감광막을 도포하고 노광 및 현상공정을 통해 리세스 시킬 영역을 노출시키는 감광막 패턴(13)을 형성한다.Referring to FIG. 1B, a photoresist film is coated on the substrate resultant, and a
도 1c를 참조하면, 노출된 기판의 액티브 영역 및 소자분리막을 100∼1000Å 두께만큼 식각하여 단차를 형성한 다음 스크린 산화막을 제거하고 LET(Light etch treatment) 처리한다.Referring to FIG. 1C, the active region and the device isolation layer of the exposed substrate are etched by a thickness of 100 to 1000 Å to form a step, and then the screen oxide layer is removed and subjected to LET (Light etch treatment).
도 1d를 참조하면, 기판 상에 게이트 산화막(14), 폴리실리콘막(15), 텅스텐 실리사이드막(16) 및 하드마스크 질화막(17)을 차례로 형성한다. 그런 다음, 하드마스크 질화막(17) 상에 감광막을 도포하고 노광 및 현상 공정을 통해 게이트 영역을 한정하는 감광막 패턴(18)을 형성한다. Referring to FIG. 1D, a
도 1e를 참조하면, 감광막 패턴(18)을 마스크로 이용하여 하드마스크 질화막(17), 텅스텐 실리사이드막(16), 폴리실리콘막(15)을 식각하여 단차부를 포함한 기판 액티브 영역 상에 게이트(19)를 형성한다. 이어서, 감광막 패턴(18)을 제거한다.Referring to FIG. 1E, the hard
1f를 참조하면, 기판 리세스시 소실된 도펀트를 보상하기 위해 게이트(19) 상에 리세스 채널 영역을 노출시키는 감광막 패턴(20)을 형성한 다음 기판 내에 B, BF 또는 BF2를 추가 이온주입한다. 이때, 추가 이온주입은 1.0E13∼1.7E13의 도우즈 및 10∼80KeV의 에너지로 수행한다.Referring to 1f, a
도 1g를 참조하면, 감광막 패턴을 제거하고, 소오스/드레인 영역(미도시)을 형성한다. Referring to FIG. 1G, the photoresist pattern is removed and a source / drain region (not shown) is formed.
이와 같이, 기판 리세스시 소실된 도펀트를 보상하기 위해 리세스 채널 영역에 추가로 불순물을 이온주입함으로써, 기판 액티브 영역을 리세스시킬때 손실된 문턱전압 조절용 이온을 보상해준다.In this manner, by implanting additional impurities into the recess channel region to compensate for the dopants lost during the substrate recess, the threshold voltage control ions lost when the substrate active region is recessed are compensated for.
이후, 도시하지는 않았으나, 소오스/드레인 영역 형성 공정을 포함한 공지된 일련의 후속 공정들을 차례로 진행하여 본 발명에 따른 반도체 소자의 제조를 완성한다.Thereafter, although not shown, a series of well-known subsequent processes including a source / drain region forming process are sequentially performed to complete the manufacture of the semiconductor device according to the present invention.
본 발명을 특정의 바람직한 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니고 이하의 특허청구의 범위에 의해 마련되는 본 고안의 정신이나 분야를 일탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변화될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자는 용이하게 알 수 있다.While the present invention has been illustrated and described with reference to certain preferred embodiments, the invention is not limited thereto and the invention may be practiced without departing from the spirit or scope of the invention as defined by the following claims. It will be readily apparent to one of ordinary skill in the art that various modifications and variations can be made.
이상에서와 같이, 본 발명은, 리세스 채널 영역에 추가로 불순물을 이온주입하여 기판을 리세스 시킬 때 손실된 문턱전압 조절 이온을 보상해 줌으로써, 문턱전압이 감소하는 것을 방지하여 소자 특성을 향상시킬 수 있다.As described above, the present invention compensates the threshold voltage control ions lost when the substrate is recessed by adding impurities to the recess channel region, thereby preventing the threshold voltage from being reduced, thereby improving device characteristics. You can.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020040114763A KR20060076369A (en) | 2004-12-29 | 2004-12-29 | Method for manufacturing semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100677770B1 (en) * | 2005-01-14 | 2007-02-02 | 주식회사 하이닉스반도체 | Semiconductor device with stack active region and method for manufacturing the same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100677770B1 (en) * | 2005-01-14 | 2007-02-02 | 주식회사 하이닉스반도체 | Semiconductor device with stack active region and method for manufacturing the same |
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