KR20060070935A - Embedded chip print circuit board and method for fabricating the same - Google Patents

Abstract

The present invention forms a circuit layer comprising a general circuit, and then forms a hole in the raw material consisting of a cured resin (resin) only and the uncured resin on both sides and a protective film for protecting it, The present invention relates to a batch laminated chip-embedded printed circuit board and a method of manufacturing the same, which are filled with electroconductive inks and are formed by heating and pressing at a time by forming a central layer after removing the protective film.

A printed circuit board according to the present invention includes a center layer formed of a via filled with conductive ink and having a chip connected to the via hole; And a circuit layer stacked on both surfaces of the center layer and having a circuit pattern and via holes electrically connected directly to the chip of the center layer through the via holes.

Printed circuit board, batch lamination, circuit layer, center layer, conductive ink, chip

Description

Embedded chip printed circuit board and method for fabricating the same {Embedded chip print circuit board and method for fabricating the same}

1A to 1F are cross-sectional views of a first embodiment showing the flow of a conventional method for manufacturing a chip embedded printed circuit board.

2A to 2D are cross-sectional views of a second embodiment showing the flow of a conventional method for manufacturing a chip embedded printed circuit board.

Fig. 3A is a longitudinal sectional front view of the third embodiment which schematically shows a state when a conventional chip embedded printed circuit board is stacked.

3B to 3F are cross-sectional views showing the flow of the core forming step of 3a.

4 is a cross-sectional view of a printed circuit board manufactured using a method of manufacturing a chip embedded printed circuit board according to an exemplary embodiment of the present invention.

FIG. 5 is a partially enlarged view of portions indicated by dotted lines of FIG. 4.

6 is a flowchart illustrating a method of manufacturing a chip embedded printed circuit board according to the present invention.

7A to 7H are cross-sectional views illustrating a flow of a circuit layer forming step according to a first embodiment of the present invention.

8A to 8F are cross-sectional views showing the flow of the center layer forming step according to the first embodiment of the present invention.

9A to 9D are cross-sectional views showing the flow of the batch lamination step according to the first embodiment of the present invention.

10A to 10H are cross-sectional views illustrating a flow of a circuit layer forming step according to a second embodiment of the present invention.

11A to 11F are cross-sectional views illustrating the flow of the center layer forming step according to the second embodiment of the present invention.

12A to 12C are cross-sectional views showing the flow of the batch lamination step according to the second embodiment of the present invention.

The present invention relates to a chip-embedded printed circuit board and a method of manufacturing the same, and more particularly, after forming a circuit layer including a general circuit, a raw material composed only of a cured resin, and an uncured resin on both sides thereof. The raw material to which the protective film is applied is not vertically processed and then plated, instead of using electroconductive ink therein, and plugged into the raw material and CCL (Copper clad laminates). A chip embedded printed circuit board and a method for manufacturing the same according to a batch lamination in which an inner layer core is formed, and heated and pressurized at a time by combining raw materials connected in a vertical direction.

In order to meet the demand of miniaturization and high functionalization of electronic products according to the development of the electronic industry, the technology of the electronic industry has been developed in the direction of inserting resistors, capacitors, integrated circuits (ICs), and the like into a substrate.

Until now, most of the PCBs have a general discrete chip resistor or a discrete chip capacitor mounted on the surface of the printed circuit board. However, recently, a printed circuit board incorporating a chip such as a resistor or a capacitor is installed. Is being developed.

The chip embedded printed circuit board technology replaces the role of the existing chip resistors and chip capacitors by inserting a chip such as a resistor or a capacitor into the outer or inner layer of the substrate by using a new material (material) and process.

In other words, a chip-embedded printed circuit board is formed by embedding a chip, such as a capacitor, inside or outside the substrate itself, and if the chip is integrated as part of the printed circuit board, regardless of the size of the substrate itself. "Chip embedded" and such a substrate is called an embedded chip PCB.

The most important feature of such a chip-embedded printed circuit board is that it does not need to be mounted on the substrate surface because the chip is inherently provided as part of the printed circuit board.

On the other hand, the chip-embedded printed circuit board technology to date can be largely classified into three methods, which will be described in detail below.

First, there is a method of implementing a polymer thick film type capacitor by applying a polymer capacitor paste and thermally curing, that is, drying the capacitor. This method produces a built-in capacitor by applying a polymer capacitor paste to an inner layer of a printed circuit board, and then printing and drying the copper paste to form an electrode after drying it.

Secondly, a ceramic filled photo-dielectric resin is coated on a printed circuit board to realize an embedded discrete type capacitor. Holds. In this method, after the photosensitive resin containing ceramic powder is coated on a substrate, copper foils are laminated to form respective upper and lower electrodes, and then circuit patterns are formed and the photosensitive resin is etched. To implement individual capacitors.

Third, a capacitor is implemented by inserting a separate dielectric layer having a capacitance characteristic in an inner layer of the printed circuit board to replace the decoupling capacitor mounted on the surface of the printed circuit board. Saga holds related patented technology. This method implements a power distributed decoupling capacitor by inserting a dielectric layer consisting of a power electrode and a ground electrode into an inner layer of a printed circuit board.

On the other hand, the speed of parts continues to increase in order to satisfy various functions and excellent performance of electronic products, and in order to improve the speed of parts, the bonding method of the packet also includes lead frames and wire bonding. (Wire Bonding), pin type (Bonding) bonding (Bonding) method is changing from a small ball type bonding (Ball Type Bonding) method, flip-chip bonding (Flip-Chip Bonding) method.

 Currently, in the case of a high speed product employing flip-chip bonding, a clock operates at a speed of 2 GHz or more in the case of a CPU or a graphic chip set.

In the case of such a CPU or a chipset, a short signal rising time, more current is required, and signal lines with an IC, a flip chip package, and a main board are required to operate at a high speed. It is designed to keep the gap short.

 However, as the component speed increases, voltage fluctuations occur in the power supply wiring, and eventually high frequency noise called SSN (Simultaneous Switching Noise) or Delta-I (ΔI) is generated.

These high frequency noises (SSNs) can cause delays or logic faults in the system, resulting in poor system performance and poor system reliability.

To reduce these SSNs, it is most effective to reduce the inductance of the power supply wiring when the current required for the device operation and switching speed cannot be changed, and decoupling to reduce the power line voltage fluctuations of the power supply wiring. Capacitor).

Decoupling Chip Capacitors are installed in the power supply wiring to directly supply the current required for switching the circuit, shielding the inductance of the power supply wiring to significantly reduce the voltage drop effect and reduce the SSN. .

1A to 1F are cross-sectional views of a first embodiment showing the flow of a conventional method for manufacturing a chip embedded printed circuit board, which is disclosed in Japanese Patent Laid-Open No. 2004-7006.

As shown in FIG. 1A, after the cavity 3 is processed in the insulating layer 1, a through hole 2 is formed, and then conductive ink is filled into the through hole 2.

As shown in FIG. 1B, a circuit 4 including a predetermined pattern is formed on the protective film 6 through a general circuit forming step, and as shown in FIG. 1C, on the circuit 4 including a predetermined pattern. The electrical element 5 is mounted on it.

Subsequently, as shown in FIG. 1D, the surface of the conductive hole filled with conductive ink 2 is bonded to the circuit 4 including a predetermined pattern, and the protective film 6 is bonded as shown in FIG. 1E. Remove

Next, as shown in FIG. 1F, after the circuit layers 7 and 8 including the circuit 9 including the predetermined pattern and the via hole 11 filled with the conductive ink are formed, both surfaces of the central layer 1 are formed. The circuit layers 7 and 8 are laminated.

2A to 2D are cross-sectional views of a second embodiment showing the flow of a conventional method for manufacturing a chip embedded printed circuit board, which is disclosed in Japanese Patent Laid-Open No. 2004-7006.

As shown in FIG. 2A, a circuit layer 20 including a circuit 22 and a conductive hole 21 formed in a predetermined pattern is formed. As shown in FIG. 2B, the electric element 23 is mounted on the circuit 22 formed in a predetermined pattern.

Thereafter, as shown in FIG. 2C, after the cavity is processed in the center layer 25, a predetermined circuit pattern 26 and a through hole 27 are formed and stacked on the circuit layer 20, and in FIG. 2D. As described above, a circuit layer 20 including a circuit 22 and a conductive hole 21 formed in a predetermined pattern is formed and stacked on the center layer 25.

In the prior art according to the first embodiment and the second embodiment described above, there is a problem in that a large amount of space is occupied between the electric element and the insulating layer in the center layer.

In addition, in the prior art according to the first embodiment and the second embodiment, there is a problem in that the space between the chip and the copper foil is large so that the effect of heat radiation cannot be obtained.

In addition, the prior art according to the second embodiment has a problem that the process takes a long time by laminating using a build-up method when laminating.

Next, FIG. 3A is a longitudinal sectional front view of a third embodiment which schematically shows a state of a conventional chip-embedded printed circuit board upon lamination, and FIGS. 3B to 3F are cross-sectional views showing the flow of the core forming process of 3A. No. 2004-153084.

As shown in FIG. 3A, the lower circuit layer is formed of a film 8 including a circuit 3 and a heat dissipation pattern 6 formed in a predetermined pattern. Here, the conductive ink 9 is filled on the heat radiation pattern 6.

Next, after processing the cavity in the film 8, the center layer forms and laminates the circuit 3 and the through-hole 9 formed in a predetermined pattern. Here, the film 8 prepares the number of layers suitable for the thickness of the electrical element 5.

Finally, the upper circuit layer forms a film 8 including the circuit 3 and the conductive hole 9 formed in a predetermined pattern, and then collectively arranges the circuit layer on the center layer into which the electric element 5 is inserted. Laminated by.

As shown in FIG. 3B, the core forming step of each layer first deposits a copper layer 10 on the film 8.

Next, as shown in FIG. 3C, the copper layer 10 on the upper portion of the film 8 forms a circuit 3 through a general circuit forming step, and a protective film 11 is applied to the lower portion of the film 8.

Thereafter, as illustrated in FIG. 3D, the through hole 8a is formed in the film 8 and the protective film 11 corresponding to the circuit 3 on the upper portion, and as shown in FIG. 3E, the through hole 8a is formed. Filled with a conductive ink (9).

Finally, as shown in Figure 3f, the protective film 11 is removed.

In the prior art according to the third embodiment described above, when interlayer sliding occurs in the process of bonding via holes filled with conductive inks to chips when stacking them collectively, the positional alignment between the layers cannot be precisely corrected. There was this.

In addition, by radiating heat using a heat radiation pattern, there is a problem in that a circuit is not formed at a portion having a heat radiation pattern, thereby being restricted when forming a high density circuit.

 The technical problem of the present invention for solving the above problems is a large amount of space between the electrical element and the insulating layer in the center layer occupies a lot of space, and when forming the via hole must be formed through the through-hole, such as a laser drill for a long process time When stacked and collectively stacked, the via holes filled with conductive ink are bonded to the chip, so that the positional alignment between the layers cannot be precisely formed. The present invention provides a chip embedded printed circuit board and a method of manufacturing the same, which solve the problem of limitations in forming a high density circuit.

In order to solve the above technical problem, the chip-embedded printed circuit board according to the present invention is formed of a via filled with a conductive ink, the center layer containing a chip connected to the via hole; And a circuit layer stacked on both surfaces of the center layer and having a circuit pattern and via holes electrically connected directly to the chip of the center layer through the via holes.

In addition, the center layer of the chip embedded printed circuit board according to the present invention includes a cured resin layer and an uncured resin layer, wherein the chip is characterized in that inserted into the cured resin layer.

In order to solve the above technical problem, a method for manufacturing a chip embedded printed circuit board according to the present invention includes a plurality of via holes filled with an electrically conductive ink, forming a chip embedded core layer; Forming a circuit layer on which circuit patterns and via holes are formed; Pre-laminating the circuit layer on both sides of the center layer; And heat-pressurizing the central layer and the circuit layer in a vacuum to directly connect the chip to the circuit pattern through the plurality of via holes.

In addition, in the method for manufacturing a chip embedded printed circuit board according to the present invention, the forming of the chip-embedded central layer may include forming a cavity in the cured resin layer; Inserting a chip into the cavity; Applying an uncured resin layer and a protective film on both sides of the substrate; Forming a plurality of via holes in the uncured resin layer and the protective film; Filling conductive vias into the via holes; Removing the protective film; characterized in that it comprises a.

Hereinafter, a method of manufacturing a chip embedded printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a cross-sectional view of a chip embedded printed circuit board according to an exemplary embodiment of the present invention, and FIG. 5 is a partially enlarged view of portions indicated by dotted lines of FIG. 4.

As shown in FIG. 4, the chip-embedded printed circuit board according to the present invention is formed of via holes B and C filled with the conductive ink 1100 and connected to the via holes B and C. Circuit patterns stacked on both surfaces of the center layer 1000 and the center layer 1000, and directly connected to the chips 2000 and 3000 of the center layer 1000 through via holes B and C. 103 and a circuit layer 100 having via holes B and C formed therein.

The central layer 1000 includes a cured resin layer 1010 and an uncured resin layer 1020, and the chips 2000 and 3000 are inserted into the cured resin 1010.

Here, the circuit 103 and the through hole A of the circuit layer 100 are formed through a general forming step, and when inserted into the cavity of the cured resin 1010 of the chips 2000 and 3000 in the central layer 1000, The thickness of the chips 2000 and 3000 should be adjusted to match the thickness of the cured resin 1010.

In addition, the margin between the chips 2000 and 3000 and the cured resin 1010 is filled with the uncured resin 1020 so that there is no margin between the chips 2000 and 3000, the cured resin 1010, and the circuit layer 103. .

As illustrated in FIG. 5, the chips 2000 and 3000 inserted into the cavity of the cured resin 1010 are formed in direct contact with the circuit pattern 103 through the via holes B filled with the conductive ink 1100.

In other words, since the electrical connection is directly to the chip, the length of the circuit 103 is short. This improves the positional alignment of the circuit patterns 103 filled with the chips 2000 and 3000, the cured resin 1010, the uncured resin 1020, and the conductive ink 1100.

In the chips 2000 and 3000 illustrated in FIG. 5, external electrodes may be positioned at left and right sides or above and below, and may be embedded in the cavity of the cured resin 1010. Here, the chips 2000 and 3000 illustrated in FIG. 5 illustrate chips formed with external electrodes on the upper and left and right sides. When the external electrodes of the chip are located on the upper and lower sides, the via holes B must also be formed on the lower side of the chip. do.

In addition, since the chip is electrically connected to the direct circuit, the length of the circuit is short. This keeps the impedance low at high frequencies.

6 is a flowchart illustrating a method of manufacturing a chip embedded printed circuit board according to the present invention.

As shown in FIG. 6, the method for manufacturing a chip embedded printed circuit board according to the first exemplary embodiment of the present invention includes a circuit layer forming step (S110), a center layer forming step (S120), and a circuit layer and a center layer. Lamination step (S130) is made.

Here, the circuit layer forming step (S110) and the center layer forming step (S120) may be performed sequentially, but in order to shorten the overall process time, it is preferable to simultaneously perform the parallel processing.

Here, the circuit layer forming step (S110) is a process of preparing a disk, which is a copper clad laminated board coated with a copper foil layer on both sides of the insulating resin layer, to form a via hole using a CNC drill or a laser drill for circuit connection of the upper and lower copper foil layers. And forming a copper plating layer in the upper and lower copper foil layers of the disc and the inside of the via hole for electrical connection of the formed via hole, and forming a predetermined circuit pattern through a photolithography process.

In addition, the center layer forming step (S120) is a process of forming a cavity into which the device is to be inserted into the disc made of a cured resin, the chip is embedded in the cavity into which the device will be inserted and the uncured resin and the protective film on both sides of the disc made of the cured resin Process of coating through hole, forming a through hole and processing a blind via hole using a laser to expose the electrode surface of the chip, and cleaning the electrode surface inside the blind via hole, and then applying conductive ink to the formed via hole. Filling process, the process of removing the electrically conductive ink protruding from the surface of the protective film, and the process of removing the protective film on the upper and lower surfaces.

Finally, the batch stacking step (S130) consists of a step of preliminary lay-up by placing the circuit layers on both sides of the center layer, and then stacking them in a batch.

7A to 7H are cross-sectional views illustrating a flow of a circuit layer forming step according to a first embodiment of the present invention.

First, referring to the circuit layer forming step (S110) of the first embodiment according to the present invention, as shown in FIG. 7A, the original plate 100, which is a copper foil laminated plate on which both surfaces of the insulating resin layer 101 are coated, is coated. Prepare.

Here, the copper clad laminate used as the original plate, which is a copper clad laminate coated with the copper foil layer 102 on both sides of the insulating resin layer 101, may be a glass / epoxy copper clad laminate, a heat resistant resin copper clad laminate, a paper / phenolic copper clad laminate, or a high frequency wave. A molten copper laminate, a flexible copper laminate, a composite copper laminate and the like can be used. However, in the manufacture of the chip embedded printed circuit board according to the first embodiment of the present invention, it is preferable to use a glass / epoxy copper clad laminate using glass fiber and epoxy resin or a heat-resistant resin copper clad laminate using glass fiber and BT resin as a disc. Do. In FIG. 7A, an original plate, which is a copper clad laminate plate having a copper foil layer 102 coated on both surfaces of an insulating resin layer 101 having a two-layer structure, is shown. However, a predetermined circuit pattern and a via hole are formed in an inner layer depending on the purpose or purpose of use. The disc which has multilayered structures, such as 4 layers, 6 layers, and 8 layers, can also be used.

Next, as shown in Figure 7b, for the circuit connection of the upper and lower copper foil layer 102 of the original plate 100, which is a copper foil laminated plate coated with the copper foil layer 102 on both sides of the insulating resin layer 101, a CNC drill or a laser drill To form a via hole (A).

Subsequently, as shown in FIG. 7C, in order to electrically connect the via holes A formed by using a CNC drill or a laser drill, the original plate 100 is a copper foil laminated plate on which copper foil layers 102 are coated on both sides of the insulating resin layer 101. The copper plating layer 103 is formed in the inside of the via hole A formed using the upper and lower copper foil layers 102 and the CNC drill or the laser drill. At this time, the inside of the via hole A formed using a CNC drill or a laser drill is filled with copper plating. In this case, since the inner wall of the via hole A formed using a CNC drill or a laser drill includes an insulating resin layer 101, cleaning the inside of the hole and electroless copper plating are performed first, followed by electrolytic copper plating having good physical properties, and then copper plating layer. It is preferable to form (103).

Next, as shown in FIG. 7D, the dry film 201 is applied to one surface of the copper plating layer 103 formed of electroless copper plating and electrolytic copper plating.

As shown in FIG. 7E, the artwork film 301 having a predetermined pattern printed thereon is brought into close contact with the dry film 201 and then irradiated with ultraviolet rays. At this time, the black portion 310 on which the predetermined pattern of the artwork film is printed does not transmit ultraviolet rays, and the non-printed portion 320 transmits the ultraviolet rays, so that the predetermined pattern is printed below the artwork film 301. The dry film 201 is cured.

Subsequently, as shown in FIG. 7F, the artwork film 301 on which the predetermined pattern is printed is removed, and then immersed in a developing solution such as an aqueous solution of sodium carbonate (Na ₂ CO ₃ ) or potassium carbonate (K ₂ CO ₃ ). To form an etching resist pattern.

Next, as in FIG. 7G, the dry film 201 is used as an etching resist, and the original plate 100 is immersed in the etching liquid, whereby the copper foil of the remaining portion except for the portion corresponding to the predetermined pattern of the dry film 201 is used. The layer 102 and the copper plating layer 103 formed of electroless copper plating and electrolytic copper plating are removed.

Finally, as shown in FIG. 7H, the dry film 201 coated on the copper plating layer 103 formed of the electroless copper plating and the electrolytic copper plating was subjected to a stripping solution containing sodium hydroxide (NaOH), potassium hydroxide (KOH), or the like. When used and removed, the circuit layer according to the invention is formed.

7D to 7H described above, although the dry film 201 is used as the etching resist, a liquid photosensitive material may be used as the etching resist.

In this case, the liquid photosensitive material exposed to ultraviolet light is applied onto the copper plating layer 103 formed of electroless copper plating and electrolytic copper plating, and then dried. Next, the predetermined pattern is formed on the photosensitive material by exposing and developing the photosensitive material using the artwork film 301 in which the predetermined pattern was formed. Next, by using the photosensitive material in which the predetermined pattern was formed as an etching resist, and spraying the etching solution on the original plate 100, the copper foil layer 102 and the electroless portions of the remaining portions except for the portion corresponding to the predetermined pattern of the photosensitive material. The copper plating layer 103 formed of copper plating and electrolytic copper plating is removed. Thereafter, the photosensitive material is removed. The method of coating the photosensitive material in the liquid state may include a dip coating method, a roll coating method, an electro-deposition method, and the like.

Since the method using the liquid photosensitive material can be applied thinner than the dry film 201, there is an advantage that a finer circuit pattern can be formed. If there is irregularities on the surface of the disc 100, there is also an advantage that can form a uniform surface by filling it.

8A to 8F are cross-sectional views showing the flow of the center layer forming step according to the first embodiment of the present invention.

Looking at the center layer forming step (S120), as shown in Figure 8a, to form a cavity to enter the chip in the disk 1000 made of a cured resin 1010.

Here, as the cured resin, it is preferable to use an epoxy resin, a polyimide resin, a BT resin, a phenol resin, or the like.

In addition, when forming a cavity, it is preferable to form using a punch or a mechanical drill.

Next, as shown in FIG. 8B, the chips 2000 and 3000 are inserted into the cavity, and the uncured resin 1020 and the protective film 1030 are applied to upper and lower portions of the disc 1000 on which the cavity is formed.

Here, the left chip illustrates the use of the active element 2000, and the right chip illustrates the use of the passive element 3000 including the electrode 3010 on both sides, and the thickness of the chip is adapted to the cured resin 1010. It is desirable to adjust.

In addition, when the chips 2000 and 3000 are inserted, the margin between the devices 2000 and 3000 and the cured resin 1010 is filled with the uncured resin 1020. This eliminates the margin between the chips 2000 and 3000 and the cured resin so that the device is not tilted.

In addition, the protective film 1030 is preferably used to remove the uncured resin and clean material when peeling off the protective film for the batch lamination.

Subsequently, as shown in FIG. 8C, the through hole C is formed, and the blind via hole B is processed to expose the surface of the chip in the chip area using a laser.

Where necessary, an additional hole (not shown) that will not be filled with conductive ink may be formed to allow air that may be present between the chip and the cured resin 1010 to escape during the vacuum heating and pressing process. Can be. These extra holes (not shown) are independent of electrical conduction and are later filled with uncured resin 1020.

In addition, after the blind via hole B is formed by laser processing, the desmear process of removing the smear attached to the inner wall of the hole by melting the resin due to heat generated when the blind via hole B is further performed is performed. It is desirable to.

Next, as shown in FIG. 8D, the conductive ink 1100 is filled in the blind via hole B formed so that the surface of the chip is exposed using the conductive hole C and the laser.

As shown in FIG. 8E, the electrically conductive ink 1100 protruding from the surface of the protective film 1030 is removed using a buffing or the like.

Finally, as shown in FIG. 8F, the protective film 1030 on the upper and lower surfaces is removed.

9A to 9D are cross-sectional views showing the flow of the batch lamination step according to the first embodiment of the present invention.

Looking at the batch stacking step (S130), as shown in Figure 9a, the upper and lower circuit layer formed by the method shown in Figs. 7a to 7h with respect to the center layer formed in the method shown in Figs. 8a to 8f. Preliminary lay-up (lay-up).

In order to accurately match the via holes of the center layer and the upper and lower circuit layers, it is preferable to perform a preliminary layup using a rivet method or a pin matching method.

The riveting method is to prepare a center layer and the upper and lower circuit layers, and then form a hole in each target guide, which is a reference point, insert a rivet into the hole, and match the center layer and the upper and lower circuit layers.

On the other hand, in the pin matching method, a guide hole, which is a reference hole between the center layer and the upper and lower circuit layers, is formed at the same position, and then a pin is inserted into each guide hole to stack several layers. It is a method of accurately matching the layers.

Next, as illustrated in FIG. 9B, when the upper circuit layer, the center layer, and the lower circuit layer, which are sequentially preliminarily laid up from the top, are sequentially stacked by vacuum heating and pressing, a chip embedded printed circuit board is completed.

Here, the chip and the circuit pattern are directly connected through a plurality of via holes. Since this is a direct electrical connection to the chip, the circuit length is shortened, resulting in low impedance at high frequencies.

Thereafter, as shown in FIG. 9C, a circuit 113 is formed in the outermost layer.

The circuit 113 of the outermost layer is formed through a general circuit forming step.

Next, as shown in FIG. 9D, the solder 110 is applied to both sides of the substrate in the circuit 113 of the outermost layer, and exposed and developed.

Here, after applying the solder 110, the first drying is performed so that the ink film applied during the operation is not damaged. The solder 110 is green and is made of a heat resistant resin that is sufficiently resistant to the melting temperature of the solder.

In addition, a method of applying the solder 110 may include a screen printing method, a roller coating method, a curtain coating method, a spray coating method, and the like.

10A to 10H are cross-sectional views showing the flow of the circuit layer forming step according to the second embodiment of the present invention.

Looking at the circuit layer forming step (S110) of the second embodiment according to the present invention, as shown in Figure 10a, to prepare a disk 400 which is a copper foil laminated plate coated with a copper foil layer 402 on both sides of the insulating resin layer 401. .

Here, the copper-clad laminate used as the original plate 400, which is a copper-clad laminate coated with a copper foil layer 402 on both sides of the insulating resin layer 401, in the manufacture of a chip embedded printed circuit board according to the second embodiment of the present invention, Glass / epoxy copper clad laminate using epoxy resin and epoxy resin or a heat-resistant resin copper clad laminate using glass fiber and BT resin as a disc 400 which is a copper clad laminated board coated with copper foil layer 402 on both sides of insulating resin layer 401. desirable.

In FIG. 10A, although the original plate 400, which is a copper clad laminate plate on which the copper foil layer 402 is coated on both sides of the insulating resin layer 401 having a two-layer structure, is shown, a predetermined circuit pattern and It is also possible to use a disc having a multilayer structure such as four layers, six layers, and eight layers in which via holes are formed.

Next, as shown in FIG. 10B, a CNC drill or a laser drill for circuit connection of the upper and lower copper foil layers 402 of the original plate 400, which is a copper foil laminated plate on which the copper foil layer 402 is coated on both surfaces of the insulating resin layer 401. To form a via hole (D) using.

And, as shown in Figure 10c, for the electrical connection of the via hole (D) formed using a CNC drill or a laser drill, the original plate 400 is a copper foil laminated plate coated with a copper foil layer 402 on both sides of the insulating resin layer 401 The inside of the hole and the copper plating layer 403 are formed inside the via hole D formed using the upper and lower copper foil layers 402 and the CNC drill or the laser drill. At this time, the inside of the via hole D is filled with copper plating.

Next, as shown in FIG. 10D, the dry film 501 is coated on the copper plating layer 403 formed of electroless copper plating and electrolytic copper plating.

Thereafter, as shown in FIG. 10E, the artwork film 601 on which the predetermined circuit pattern is printed is brought into close contact with the dry film 501, and then ultraviolet rays are irradiated. In this case, the black portion 610 on which the predetermined pattern of the artwork film 601 is printed does not transmit ultraviolet rays, and the portion 620 of the non-printed portion 620 transmits ultraviolet rays so that the predetermined circuit pattern is printed on the artwork film ( 601 to cure the dry film 501 under.

Then, as shown in FIG. 10F, by removing the artwork film 601 on which a predetermined circuit pattern is printed, and then immersing it in a developing solution such as an aqueous solution of sodium carbonate (Na ₂ CO ₃ ) or potassium carbonate (K ₂ CO ₃ ), A predetermined etching resist pattern is formed.

Subsequently, as in FIG. 10G, the dry film 501 is used as an etching resist, and the original film 400 is immersed in the etching liquid, whereby the copper foil of the remaining portion except for the portion corresponding to the predetermined pattern of the dry film 501 is obtained. The layer 402 and the copper plating layer 403 are removed.

Finally, as shown in FIG. 10H, when the dry film 501 coated on the copper plating layer 403 is removed using a stripping solution containing sodium hydroxide (NaOH), potassium hydroxide (KOH), or the like, Accordingly a circuit layer is formed.

10D to 10H described above, although the dry film 501 is used as the etching resist, a liquid photosensitive material may be used as the etching resist.

11A to 11F are cross-sectional views illustrating the flow of the center layer forming step according to the second embodiment of the present invention.

Looking at the center layer forming step (S120), as shown in Figure 11a, to form a cavity for the chips (5000, 6000) to enter in the disk (4000) made of a cured resin 4010.

Next, as shown in FIG. 11B, the chips 5000 and 6000 are inserted into the cavity, and the uncured resin 4020 and the protective film 4030 are laminated on the upper and lower portions of the disc 4000, respectively.

Here, the protective film 4030 preferably uses a coverlay to protect and insulate the exposed surface of the circuit.

As shown in FIG. 11C, the through hole F is formed, and the blind via hole E is processed in the chip area to expose the surface of the chip.

If necessary, an additional hole not filled with conductive ink may be formed so that air which may exist between the chips 5000 and 6000 and the cured resin 4010 may be released during the vacuum heating and pressing process. . These extra holes are independent of electrical conduction and are later filled with uncured resin 4020.

Next, as shown in FIG. 11D, the conductive via 4F is filled after the cleaning process is performed in the blind via hole E formed to expose the surface of the chip using the conductive hole F and the laser.

Thereafter, as shown in FIG. 11E, the electrically conductive ink 4100 protruding from the surface of the protective film 4030 is removed using a buffing or the like.

Thereafter, as shown in FIG. 11F, the protective film 4030 on the upper and lower surfaces is removed.

12A to 12C are cross-sectional views showing the flow of the batch lamination step according to the second embodiment of the present invention.

Referring to the batch stacking step (S130), as shown in FIG. 12A, the circuit layer formed by the method illustrated in FIGS. 10A to 10H is centered around the center layer formed by the method illustrated in FIGS. 11A to 11F. I lay up a spare on both sides.

In order to accurately match the via holes of the center layer and the upper and lower circuit layers, it is preferable to perform a preliminary layup using a riveting method or a pin matching method.

Next, as illustrated in FIG. 12B, when the upper circuit layer, the center layer, and the lower circuit layer which are preliminarily laid up from the top are sequentially stacked by vacuum heating and pressing, a chip embedded printed circuit board is completed.

Thereafter, as shown in FIG. 12C, the solder 410 is applied to both surfaces of the substrate in the upper and lower outer circuits, and exposed and developed.

Here, after the solder 410 is applied, initial drying is performed so that the ink film applied during the operation is not damaged. The solder 410 is green and is made of a heat resistant resin that is sufficiently resistant to the melting temperature of the solder.

In the method for manufacturing a chip embedded printed circuit board according to the present invention, the first embodiment forms an external circuit after a batch lamination step, and the second embodiment forms a external circuit after forming an external circuit. This is advantageous in the case of the second embodiment, in which the circuit forming process is not necessary in the batch stacking step S130.

Although the present invention has been described above, this is only one embodiment, and it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. . However, it will be confirmed through the claims that such changes and modifications fall within the scope of the present invention.

As described above, according to the present invention, when the conductive ink is directly filled in the substrate into which the chip is inserted, there is an effect of preventing misalignment due to interlaminar tilting.

In addition, according to the present invention, it is a batch lamination method, there is an effect that can greatly shorten the manufacturing time.

In addition, according to the present invention, since no solder is used for the electrical connection, noise is reduced.                     

In addition, according to the present invention there is an effect that can be connected via both in the up and down direction when the electrode is above and below the chip.

In addition, according to the present invention, since the chip and the circuit pattern are directly connected to each other through a plurality of via holes, the circuit length is shortened, thereby reducing the impedance at high frequencies.

Claims (9)

A center layer formed of a via filled with a conductive ink and having a chip connected to the via hole; And And a circuit layer stacked on both sides of the center layer and having a circuit pattern and a via hole electrically connected directly to the chip of the center layer through the via holes. 2. The method of claim 2, The central layer includes a cured resin layer and an uncured resin layer, wherein the chip is embedded in the cured resin layer, characterized in that the chip embedded printed circuit board. A plurality of via holes filled with electrically conductive ink, the chip comprising: forming a center layer in which chips are embedded; Forming a circuit layer on which circuit patterns and via holes are formed; Pre-laminating the circuit layer on both sides of the center layer; And And pressing the center layer and the circuit layer to directly connect the chip to the circuit pattern through the plurality of via holes. The method of claim 3, wherein The step of forming the core layer in which the chip is embedded, Forming a cavity in the cured resin layer; Inserting a chip into the cavity; Applying an uncured resin layer and a protective film on both sides of the substrate; Forming a plurality of via holes in the uncured resin layer and the protective film; Filling conductive vias into the via holes; And Removing the protective film; Chip embedded printed circuit board manufacturing method comprising a. The method of claim 4, wherein Filling the conductive ink, A method of manufacturing a chip embedded printed circuit board, the method comprising: polishing a conductive ink protruding from the outside. The method of claim 4, wherein Filling the conductive ink, And filling conductive ink into only the via holes other than the via holes, which function to discharge air during the pressurizing, among the plurality of via holes. The method of claim 3, wherein Forming the circuit layer, Forming a via hole; And Forming a circuit pattern on one surface; chip embedded printed circuit board manufacturing method comprising a. The method of claim 7, wherein The method of manufacturing a chip embedded printed circuit board further comprising the step of forming a circuit pattern of the outermost layer. The method of claim 3, wherein Forming the circuit layer, the chip embedded printed circuit board manufacturing method comprising the step of forming a circuit layer on both sides of the via hole.

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