JP3846209B2 - Multilayer printed wiring board manufacturing method and multilayer printed wiring board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
According to the present invention, through holes are formed in insulating substrates having conductive foils formed on upper and lower surfaces, and inner conductive plating layers are formed in the through holes and upper and lower conductive foils. In a multilayer printed wiring board in which IVH (Interstitial Via Hole) is formed by electrically connecting conductive foils and filling an insulating resin in a hole in which an inner conductive plating layer is formed in a through hole, The present invention relates to a method for manufacturing a multilayer printed wiring board and a multilayer printed wiring board for alleviating thermal stress generated in IVH during high-temperature soldering to the multilayer printed wiring board.
[0002]
[Prior art]
In recent years, with the miniaturization of electronic equipment, multilayer printed wiring boards designed to be multilayered have been used to realize high-density component mounting on printed wiring boards (printed wiring boards) applied to electronic equipment. It has been. At this time, the multilayer printed wiring board is also called a build-up board. In particular, this type of multilayer printed wiring board is frequently used in portable electronic devices.
[0003]
6A and 6B are a top view and a longitudinal sectional view schematically showing a conventional multilayer printed wiring board.
[0004]
In the conventional multilayer printed wiring board 1A shown in FIGS. 6A and 6B, the insulating substrate 2 using glass epoxy resin as the core material is made of conductive copper foil or the like on the upper and lower surfaces 2a and 2b. The conductive foils 3 and 3 are respectively formed, and when the upper surface 2a and / or the lower surface 2b side of the insulating substrate 2 is multilayered, the insulating substrate 2 and the conductive foils 3 and 3 are used by using a drill or the like. A through hole 2c is formed through the through hole. Then, inner conductive plating layers 4 and 4 are formed by copper plating or the like in the through hole 2c of the insulating substrate 2 and on the conductive foils 3 and 3, and the upper and lower conductive foils 3 and 3 are electrically connected to each other. After that, an IVH (Interstitial Via Hole) 6 is formed by filling the hole 4a in which the inner conductive plating layer 4 is formed in the through hole 2c with an epoxy resin 5 having an insulating property for filling the hole. A well-known through hole (not shown) for the IVH 6 described above forms an inner conductive plating layer 4 in the through hole 2c of the insulating substrate 2 to electrically connect the upper and lower conductive foils 3 and 3 to each other. The hole 4a is not filled with the epoxy resin 5 while being connected to.
[0005]
Further, after the IVH 6 is formed, the conductive foils 3 and 3 formed on the upper and lower surfaces 2a and 2b of the insulating substrate 2 and the inner conductive plating layers 4 and 4 formed by laminating on the conductive foils 3 and 3 are formed. Are subjected to a masking process and an etching process to form a predetermined circuit pattern to form conductive circuit patterns (3A, 4A), (3B, 4B), and these conductive circuit patterns (3A, 4A), (3B , 4B) and the insulating layers 7 and 7 are formed on the upper and lower sides of the IVH 6 and cured, and the conductive circuit patterns (3A, 4A), (3B, 4B), the bottomed holes 7a and 7b are drilled, and then the outer conductive plating layer (or the copper plating or the like is roughened by roughening the insulating layers 7 and 7 and the bottomed holes 7a and 7b. Inner layer conductive plating layer) 8, 8 formed, outer Conductive masking and etching are performed so that the conductive plating layers (or inner conductive plating layers) 8 and 8 have a predetermined circuit pattern to form conductive circuit patterns 8A and 8B on the insulating layers 7 and 7, respectively. Thus, a multilayered conventional multilayer printed wiring board 1A is configured.
[0006]
In the case where the inner conductive plating layers 8 and 8 are formed on the insulating layers 7 and 7 and in the bottomed holes 7a and 7b, the conventional multi-layering is repeated by repeating the multi-layering in the same manner. A printed wiring board 1A is configured.
[0007]
[Problems to be solved by the invention]
By the way, in consideration of recent environmental problems, there is a tendency to remove lead from the solder component for bonding, and as a result, the melting point of the solder rises, which is higher than that of the conventional multilayer printed wiring board 1A formed with IVH6. The attachment is done.
[0008]
Further, in the conventional multilayer printed wiring board 1A, insulating layers 7 and 7 for insulating layers between the upper and lower sides of the IVH 6 are formed. The IVH 6 is surrounded by different materials, and the insulating substrate 2 The finite element method by the present inventors is that thermal stress is generated in the IVH 6 due to the difference in thermal expansion coefficient between the inner conductive plating layer 4 formed in the through hole 2c and the epoxy resin 5 filled in the hole 4a. As a result of analysis by using it, it became clear.
[0009]
Specifically, as shown in FIGS. 6A and 6B, a large conductive circuit pattern 8A1 for grounding or shielding is formed at a position facing the insulating layer 7 above the IVH 6, for example. In such a case, delamination or cracks occur between the insulating layer 7 and the conductive circuit pattern 8A1 due to the thermal stress generated in the IVH 6 during high-temperature soldering, and the function of the multilayer printed wiring board 1A is lost. Problems arise. At this time, according to preliminary experiments by the present inventors, it was found that delamination and cracks are likely to occur when the conductive circuit pattern 8A1 having a large rectangular shape or circular shape has an area of 25 mm ² or more.
[0010]
Therefore, as an example of a method for solving the problems caused by the thermal stress of IVH6 during high temperature soldering to the conventional multilayer printed wiring board 1A, the same components (for example, copper as the inner conductive plating layer 4) are formed when forming IVH6. There is a method of reducing the generation of thermal stress by making the thermal conductivity substantially equal using the paste filling material, but in this case, the cost of the filling material itself is high, and in the case of copper paste or the like from IVH6 The protruding excess copper paste cannot be polished flat. As another example of a method for solving the problem at the time of high-temperature soldering, it is sufficient that a conductive circuit pattern having a large area is not formed on the insulating layer 7 at a position facing the IVH 6. When designing a conductive circuit pattern, there is a problem that the position of the conductive circuit pattern is restricted.
[0011]
[Means for Solving the Problems]
The present invention has been made in view of the above problems, and the first invention includes a step of forming a through hole in an insulating substrate in which conductive foils are formed on upper and lower surfaces, respectively.
Forming an inner conductive plating layer in the through hole and on the upper and lower conductive foils to electrically connect the upper and lower conductive foils;
A step of baking (drying) the insulating substrate after forming the inner conductive plating layer;
After baking the insulating substrate, filling the hole in which the inner conductive plating layer is formed in the through hole with an insulating resin to form an IVH (Interstitial Via Hole);
Polishing an excess of the insulating resin protruding from the IVH on the side of the upper and lower surfaces of the insulating substrate that is multi-layered, and flattening the ends of the IVH;
A step of forming an insulating layer on the side of the upper and lower surfaces of the insulating substrate to be multilayered;
Forming a conductive circuit pattern on the insulating layer, and forming a vent conductive pattern having a stress relaxation vent at a position facing the IVH on the insulating layer. It is a manufacturing method of the multilayer printed wiring board characterized.
[0012]
According to a second aspect of the present invention, through holes are formed in an insulating substrate having conductive foils formed on upper and lower surfaces, and inner conductive plating layers are formed in the through holes and on the upper and lower conductive foils. The upper and lower conductive foils are electrically connected to each other, and an IVH (Interstitial Via Hole) is formed by filling an insulating resin in the hole in which the inner conductive plating layer is formed in the through hole. In the multilayer printed wiring board in which an insulating layer is formed on the surface to be multilayered among the upper and lower surfaces of the insulating substrate, and a conductive circuit pattern is formed on the insulating layer.
The multilayer printed wiring board is characterized in that a vent conductive pattern having a stress relaxation vent (hole) is formed on the insulating layer at a position facing the IVH.
[0013]
The third invention is the multilayer printed wiring board of the second invention described above,
The vent conductive pattern has an area of 25 mm ² or more, and the deviation amount of the center position of the vent (hole) is within 0.8 mm with respect to the center position of the through hole. The diameter of the hole) is 1/3 d or more with respect to the diameter d of the through hole.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of a method for manufacturing a multilayer printed wiring board and a multilayer printed wiring board according to the present invention will be described in detail below with reference to FIGS.
[0015]
FIG. 1 is a process diagram (No. 1) for explaining a manufacturing method of a multilayer printed wiring board according to the present invention in the order of processes;
FIG. 2 is a process diagram (No. 2) for explaining the manufacturing method of the multilayer printed wiring board according to the present invention in the order of processes,
3 (a) and 3 (b) are a top view, a longitudinal sectional view schematically showing a multilayer printed wiring board according to the present invention,
FIG. 4 is a diagram showing a result of analysis using a finite element method in order to compare the multilayer printed wiring board according to the present invention with a conventional multilayer printed wiring board. FIG. (B) is a diagram showing the distortion analysis results,
FIG. 5 is a diagram showing evaluation contents for IVH and results corresponding to the evaluation contents in the multilayer printed wiring board according to the present invention.
[0016]
For convenience of explanation, the same constituent members as those shown in the conventional example will be described with the same reference numerals, and the constituent members different from the conventional examples will be given new reference numerals. To do.
[0017]
First, the manufacturing method of the multilayer printed wiring board 1B according to the present invention will be described in the order of steps with reference to FIGS.
[0018]
As shown in FIG. 1A, conductive foils 3 and 3 are formed using conductive copper foils on the upper and lower surfaces 2a and 2b of the insulating substrate 2 using glass epoxy resin as a core material, respectively. A through hole 2c having a diameter of about 0.3 mm is drilled through the insulating substrate 2 and the conductive foils 3 and 3 using a drill or the like.
[0019]
Next, as shown in FIG. 1B, an inner conductive plating layer 4 is formed by copper plating or the like in the through hole 2c of the insulating substrate 2 and on the upper and lower conductive foils 3 and 3, The conductive foils 3 and 3 are electrically connected. At this time, the inner conductive plating layers 4 and 4 laminated on the upper and lower conductive foils 3 and 3 are integrated with the conductive foils 3 and 3.
[0020]
Thereafter, in order to fill the hole 4a in which the inner conductive plating layer 4 is formed in the through hole 2c of the insulating substrate 2, for example, 80 or more of the curing temperature of the insulating resin (for example, epoxy resin) for filling the hole. Baking (drying) is performed at a temperature of ° C to 180 ° C. By this baking, outgas from the insulating substrate 2 generated at the hole-filling curing temperature and moisture present in the hole 4a in which the inner conductive plating layer 4 is formed in the through hole 2c of the insulating substrate 2 are removed.
[0021]
Next, as shown in FIG. 1C, the lower surface 2 b side of the insulating substrate 2 is placed on the receiving table U, and the layer conductive plating layer 4 is formed in the through hole 2 c of the insulating substrate 2. A mask material M having an opening only in the vicinity of the hole 4a is placed on the inner conductive plating layer 4 laminated on the conductive foil 3b on the upper surface 2a side of the insulating substrate 2, and using a squeegee SK by a screen printing method. An insulating substrate is formed by filling an insulating epoxy resin (insulating resin) 5 for filling a hole in the hole 4a in which the inner conductive plating layer 4 is formed, and curing the epoxy resin 5 at a predetermined curing temperature. The hardened epoxy resin 5 is embedded in the hole 4a in which the inner conductive plating layer 4 is formed in the two through holes 2c to form an IVH (Interstitial Via Hole) 6. Here, since the insulating substrate 2 is baked in advance, bubbles are not generated when the epoxy resin 5 is cured.
[0022]
Next, as shown in FIG. 1D, the upper and lower end portions of the IVH 6 are polished by buffing B, B (or belt sander) with the excess epoxy resin 5 for filling the hole protruding from the IVH 6. The surface is flattened until the surface of the inner conductive plating layers 4 and 4 laminated on the conductive foils 3 and 3 is substantially the same.
[0023]
Next, as shown in FIG. 1E, on the inner conductive plating layers 4 and 4 laminated on the conductive foils 3 and 3, a dry film having openings other than a predetermined circuit pattern portion (see FIG. The portion opened through the photomask is exposed with ultraviolet light, and then the exposed portion is etched with cupric chloride etchant, so that the upper and lower surfaces 2a and 2b of the insulating substrate 2 are exposed. Conductive circuit patterns (3A, 4A) and (3B, 4B) are formed. At this time, the inner conductive plating layer 4 formed in the through hole 2c of the insulating substrate 2 is connected to the conductive circuit patterns (3A, 4A), (3B, 4B).
[0024]
Next, as shown in FIG. 2A, epoxy is formed on the conductive circuit patterns (3A, 4A), (3B, 4B) formed on the upper and lower surfaces 2a, 2b of the insulating substrate 2 and on the upper and lower sides of IVH6. The insulating layers 7 and 7 are formed by using an interlayer insulating resin mainly composed of a resin, and the upper and lower insulating layers 7 and 7 are cured at a predetermined curing temperature. Thereafter, the bottomed holes 7a and 7b are formed from above the insulating layers 7 and 7 using a carbon dioxide laser or the like until reaching the conductive circuit patterns (3A, 4A) and (3B, 4B).
[0025]
Next, as shown in FIG. 2B, the surface of the insulating layers 7 and 7 and the inside of the bottomed holes 7a and 7b are roughened using permanganic acid or the like, and an outer conductive plating layer is formed by copper plating or the like. (Or inner conductive plating layer) 8 and 8 are formed. When the outer conductive plating layers 8 and 8 are formed, the outer conductive plating layers 8 and 8 are not multilayered without forming an insulating layer thereon. When the layers 8 and 8 are formed, an insulating layer is further formed thereon to further increase the number of layers.
[0026]
Next, as shown in FIG. 2C, a dry film (not shown) having openings other than a predetermined circuit pattern portion on the outer conductive plating layers (or inner conductive plating layers) 8 and 8 is opened. ) Is exposed to ultraviolet rays through the photomask, and then the exposed portions are etched with a cupric chloride etchant, whereby the conductive circuit pattern 8A is formed on the upper and lower insulating layers 7 and 7. , 8B are formed, and conductive patterns 8C, 8D for venting having vents (Vent... Holes) V, V for stress relaxation at positions facing the upper and lower sides of IVH 6 on insulating layers 7, 7 are conductive circuits. It is formed simultaneously with the patterns 8A and 8B. At this time, it is necessary to make the center positions of the stress relaxation vents (holes) V, V 1 substantially coincide with the center position of the IVH 6 (= the center position of the through hole 2c) as will be described later.
[0027]
At this time, when the outer conductive plating layers 8 and 8 are formed, the conductive circuit patterns 8A and 8B and the vent conductive patterns 8C and 8D are exposed to the outside, while the inner conductive plating layers In the case of forming 8, 8, insulating layers 9, 9 are further formed on the conductive circuit patterns 8A, 8B and the vent conductive patterns 8C, 8D as shown in FIG. By doing so, more layers can be achieved.
[0028]
In the above manufacturing method, the upper and lower surfaces 2a and 2b of the insulating substrate 2 have been described as being multi-layered. However, only one of the upper and lower surfaces 2a and 2b with the IVH 6 formed in the insulating substrate 2 is described. In this case, the excess epoxy resin protruding from the IVH 6 is polished and flattened on the surface to be multilayered, and the multilayered surface of the upper and lower surfaces 2a and 2b of the insulating substrate 2 is laminated. A conductive circuit pattern (8A, 8B) is formed on the insulating layer 7 by coating the insulating layer 7 only on the side, and at the same time, a stress relaxation vent (on the position facing the IVH 6 on the insulating layer 7) A vent conductive pattern (8C, 8D) having a hole V may be formed.
[0029]
Next, as shown in FIG. 3, in the multilayer printed wiring board 1B according to the present invention manufactured as described above, the conductive foils 3 and 3 are formed on the upper and lower surfaces 2a and 2b, respectively. The through hole 2c is formed, and the inner conductive plating layer 4 is formed in the through hole 2c and on the upper and lower conductive foils 3 and 3 to electrically connect the upper and lower conductive foils 3 and 3 to each other. At the same time, an IVH (Interstitial Via Hole) 6 is formed by filling a hole 4a in which the inner conductive plating layer 4 is formed in the through hole 2c of the insulating substrate 2 with a poxy resin (insulating resin) 5; An insulating layer 7 is formed only on the upper and lower surfaces 2a and 2b of the insulating substrate 2 so as to form a multilayer, and conductive circuit patterns (8A and 8B) are formed on the insulating layer 7. 7 having a vent (hole) V for stress relaxation at a position opposite to IVH 6 on 7. The conductive pattern (8C, 8D) is formed.
[0030]
At this time, the vent conductive pattern (8C, 8D) can also function as the conductive circuit pattern (8A, 8B), and the area of the vent conductive pattern (8C, 8D) is grounded as described later. In the case where it is formed widely for use as a shield or shield, a stress relaxation vent (hole) V is formed here to relieve the thermal stress generated in the IVH 6 during high-temperature soldering.
[0031]
Here, in order to compare the multilayer printed wiring board 1B according to the present invention with the conventional multilayer printed wiring board 1A (FIG. 6), in FIGS. 4 (a) and 4 (b), the inside of the through hole 2c of the insulating substrate 2 is shown. In a state where IVH6 is formed on the insulating layer 7 formed on the upper surface 2a side of the insulating substrate 2 on the side of the present invention shown on the upper side, a vent (hole) V for stress relaxation is provided at a position facing the IVH6. On the other hand, the conductive pattern 8B is formed at a position facing the IVH 6 on the insulating layer 7 formed on the lower surface 2b side of the insulating substrate 2 in the conventional side shown below. In this state, a thermal stress analysis at 250 ° C. was performed using a general-purpose finite element program “ANSYS”.
[0032]
At this time, the diameter of the through hole 2c of the insulating substrate 2 is φ0.3 mm, the diameter of the vent (hole) V is also φ0.3 mm, and the center position of the IVH 6 formed in the through hole 2c and the vent (hole) V While matching the center position, the areas of the vent conductive pattern 8C and the conductive circuit pattern 8B were both set to 1 mm ² , and stress analysis and strain analysis were performed by the finite element method.
[0033]
First, from the result of stress analysis by the finite element method shown in FIG. 4A, the present invention side forms a vent (hole) V for stress relaxation in the conductive pattern 8C for vent, and this vent (hole). Thermal stress generated in IVH6 during high-temperature soldering is relieved by V, so that almost no stress is generated in the portion facing the upper portion of IVH6, whereas in the conventional example, thermal stress generated in IVH6 during high-temperature soldering Is transmitted to the insulating layer 7 and the conductive circuit pattern 8B, it is clear that stress is generated in the conductive circuit pattern 8B facing the lower part of the IVH 6.
[0034]
Next, from the result of strain analysis by the finite element method shown in FIG. 4B, although a slight strain is generated in the insulating layer 7 facing the upper portion of the IVH 6 on the present invention side, the IVH 6 is on the conventional example side. It is clear that a large strain is generated in the insulating layer 7 facing the lower part of the substrate.
[0035]
Here, when forming the vent conductive patterns 8C and 8D having the above-described stress relaxation vents (holes) V and V, according to the preliminary experiments by the present inventors as described in the prior art. When the area of the large conductive circuit pattern 8A1 (FIG. 6) is 25 mm ² or more, delamination or cracks are likely to occur. Therefore, the area of the vent conductive patterns 8C and 8D is 25 mm ² or more. As shown in FIGS. 5A and 5B, the deviation δ of the center position of the vent (hole) with respect to the center position of IVH6 is set to be directly above IVH6 (0 mm), 0.5 mm, 0.8 mm, It was found that delamination and cracks do not occur when the deviation amount δ is set within 0.8 mm when shaken at 1.0 mm. In addition, the hole diameter of the vent (hole) V is the same as the hole diameter d of the through hole 2c with respect to the hole diameter d (= 0.3 mm) of the through hole 2c formed in the insulating substrate 2 to form IVH6. No delamination or cracks are generated by setting the hole diameter of the vent (hole) V to be 1 / 3d or more with respect to the hole diameter d of the through hole 2c when shaken to 1 / 2d, 1 / 3d, and 1 / 5d. There was found.
[0036]
Thereby, in the manufacturing method of the multilayer printed wiring board 1B and the multilayer printed wiring board 1B according to the present invention, the upper and lower conductive foils 3, 3 respectively formed on the upper and lower surfaces 2a, 2b of the insulating substrate 2 are joined. Even if the IVH 6 is formed in the insulating substrate 2, a stress relaxation vent is formed at a position facing the IVH 6 on the insulating layer 7 formed on the upper and lower surfaces 2 a and 2 b of the insulating substrate 2. Since the vent conductive pattern (8C, 8D) having (holes) V is formed, there is no delamination or cracking due to thermal stress generated in IVH6 during high temperature soldering, so the quality of the multilayer printed wiring board 1B And reliability can be improved.
[0037]
【The invention's effect】
According to the method for manufacturing a multilayer printed wiring board and the multilayer printed wiring board according to the present invention described in detail above, IVH for bonding the conductive foils formed respectively on the upper and lower surfaces of the insulating substrate is formed in the insulating substrate. However, by forming a conductive pattern for vent having a vent (hole) for stress relaxation at a position facing IVH on the insulating layer formed on the multilayered surface side of the upper and lower surfaces of the insulating substrate. In addition, since delamination and cracks due to thermal stress generated in IVH do not occur at the time of high temperature soldering, the quality and reliability of the multilayer printed wiring board can be improved.
[Brief description of the drawings]
FIG. 1 is a process diagram (part 1) for explaining a manufacturing method of a multilayer printed wiring board according to the present invention in the order of steps;
FIG. 2 is a process diagram (part 2) for explaining the method of manufacturing the multilayer printed wiring board according to the present invention in the order of steps;
3A and 3B are a top view and a longitudinal sectional view schematically showing a multilayer printed wiring board according to the present invention.
FIG. 4 is a diagram showing a result of analysis using a finite element method in order to compare a multilayer printed wiring board according to the present invention with a conventional multilayer printed wiring board, and FIG. (B) is the figure which showed the distortion analysis result.
FIG. 5 is a diagram showing evaluation contents for IVH and results corresponding to the evaluation contents in the multilayer printed wiring board according to the present invention.
FIGS. 6A and 6B are a top view and a longitudinal sectional view schematically showing a conventional multilayer printed wiring board, respectively.
[Explanation of symbols]
1 ... multilayer printed wiring board according to the present invention,
2 ... Insulating substrate, 2a, 2b ... Upper and lower surfaces, 2c ... Through hole,
3 ... conductive foil, 3A, 3B ... conductive circuit pattern,
4 ... inner conductive plating layer, 4a ... hole, 4A, 4B ... conductive circuit pattern,
5. Insulating resin (epoxy resin),
6… IVH (Interstitial Via Hole),
7: Insulating layer,
8: inner conductive plating layer, 8A, 8B ... conductive circuit pattern,
8C, 8D ... conductive pattern for venting,
V ... Vent (Vent ... hole).

Claims (3)

A step of forming a through hole in an insulating substrate formed with conductive foils on the upper and lower surfaces, and
Forming an inner conductive plating layer in the through hole and on the upper and lower conductive foils to electrically connect the upper and lower conductive foils;
A step of baking (drying) the insulating substrate after forming the inner conductive plating layer;
After baking the insulating substrate, filling the hole in which the inner conductive plating layer is formed in the through hole with an insulating resin to form an IVH (Interstitial Via Hole);
Polishing an excess of the insulating resin protruding from the IVH on the side of the upper and lower surfaces of the insulating substrate that is multi-layered, and flattening the ends of the IVH;
A step of forming an insulating layer on the side of the upper and lower surfaces of the insulating substrate to be multilayered;
Forming a conductive circuit pattern on the insulating layer, and forming a vent conductive pattern having a stress relaxation vent at a position facing the IVH on the insulating layer. A manufacturing method of a multilayer printed wiring board characterized by the above. A through hole is formed in an insulating substrate having conductive foils formed on the upper and lower surfaces, and inner conductive plating layers are formed in the through hole and on the upper and lower conductive foils to form the upper and lower conductive layers. The foils are electrically connected to each other, and an IVH (Interstitial Via Hole) is formed by filling an insulating resin in the hole in which the inner conductive plating layer is formed in the through hole. In a multilayer printed wiring board in which an insulating layer is formed on the side of the upper and lower surfaces to be multilayered, and a conductive circuit pattern is formed on the insulating layer,
A multilayer printed wiring board, wherein a vent conductive pattern having a stress relaxation vent (hole) is formed at a position facing the IVH on the insulating layer. In the multilayer printed wiring board according to claim 2,
The vent conductive pattern has an area of 25 mm ² or more, and the deviation amount of the center position of the vent (hole) is within 0.8 mm with respect to the center position of the through hole. The multilayer printed wiring board is characterized in that the diameter of the hole) is 1 / 3d or more with respect to the diameter d of the through hole.

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