KR20060061457A - Methods for forming inter-metal dielectrics of semiconductor devices - Google Patents

Methods for forming inter-metal dielectrics of semiconductor devices Download PDF

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KR20060061457A
KR20060061457A KR1020040100203A KR20040100203A KR20060061457A KR 20060061457 A KR20060061457 A KR 20060061457A KR 1020040100203 A KR1020040100203 A KR 1020040100203A KR 20040100203 A KR20040100203 A KR 20040100203A KR 20060061457 A KR20060061457 A KR 20060061457A
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film
forming
interlayer insulating
insulating film
fsg
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Korean (ko)
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신주한
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Abstract

본 발명은 반도체소자의 층간절연막 형성방법에 관한 것으로, 금속배선의 층간절연막의 증착 공정시 또는 증착 공정후 유발되는 파티클에 의한 소자의 특성 열화를 방지할 수 있도록 하기 위하여, The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, in order to prevent deterioration of device characteristics due to particles caused during or after the deposition process of the interlayer insulating film of a metal wiring,

제1금속배선이 구비되는 반도체기판 상부에 층간절연막인 FSG 막을 형성하고 상기 FSG 막을 플라즈마 식각 및 CMP 하여 상기 FSG 막 증착 공정시 또는 증착 공정시 유발되는 파티클을 제거한 다음, 후속 공정으로 비아콘택플러그를 형성하여 예정된 특성을 제공하는 금속배선을 형성할 수 있도록 함으로써 반도체소자의 특성 및 신뢰성을 향상시킬 수 있도록 하는 기술이다. A FSG film, which is an interlayer insulating film, is formed on the semiconductor substrate provided with the first metal wiring, and the FSG film is plasma-etched and CMP to remove particles caused during the FSG film deposition process or the deposition process, and then the via contact plug is removed in a subsequent process. It is a technology that can improve the characteristics and reliability of the semiconductor device by forming a metal wiring to provide a predetermined characteristic by forming.

Description

반도체소자의 층간절연막 형성방법{Methods for forming inter-metal dielectrics of semiconductor devices}Method for forming inter-metal dielectrics of semiconductor devices

도 1a 내지 도 1f 는 종래기술의 실시예에 따른 반도체소자의 층간절연막 형성방법을 도시한 단면도.1A to 1F are cross-sectional views illustrating a method for forming an interlayer insulating film of a semiconductor device according to an embodiment of the prior art.

도 2 내지 도 4 는 상기 종래기술의 실시예에 따라 형성된 반도체소자를 도시한 평면 사진.2 to 4 are planar photographs showing a semiconductor device formed according to the embodiment of the prior art.

도 5a 내지 도 5c 는 본 발명의 실시예에 따른 반도체소자의 층간절연막 형성방법을 도시한 단면도.5A to 5C are cross-sectional views illustrating a method for forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

11,41 : 제1금속배선 13,43 : FSG 막11,41 first metal wiring 13,43 FSG membrane

15 : 파티클 17 : TEOS 막15: Particle 17: TEOS film

19 : 요부 21 : 비아콘택홀19: main part 21: via contact hole

23 : 식각장벽층 25 : 텅스텐층23 etching layer 25 tungsten layer

27 : 비아 콘택플러그 45 : 제1파티클27: via contact plug 45: the first particle

47 : 제2파티클47: second particle

본 발명은 반도체소자의 층간절연막 형성방법에 관한 것으로, 특히 금속배선 간의 층간절연막을 형성하는 경우 유발되는 파티클에 의한 소자의 특성 열화를 방지할 수 있도록 하는 기술이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, and in particular, to prevent deterioration of device characteristics due to particles caused when forming an interlayer insulating film between metal wirings.

일반적으로 반도체소자의 금속배선 형성방법은 금속배선 사이의 층간절연막으로 FSG ( fluoro silica glass ) 막으로 형성한다. In general, a metal wiring forming method of a semiconductor device is formed of a fluoro silica glass (FSG) film as an interlayer insulating film between metal wirings.

도 1a 내지 도 1f 는 종래기술에 따른 반도체소자의 층간절연막 형성방법을 도시한 단면도이다.1A to 1F are cross-sectional views illustrating a method for forming an interlayer insulating film of a semiconductor device according to the prior art.

도 1a를 참조하면, 반도체기판(미도시) 상에 하부절연층(미도시)을 형성한다. Referring to FIG. 1A, a lower insulating layer (not shown) is formed on a semiconductor substrate (not shown).

그 다음, 상기 반도체기판에 접속되는 제1금속배선(11)을 형성한다. Then, the first metal wiring 11 connected to the semiconductor substrate is formed.

이때, 상기 제1금속배선(11)은 Ti/Al/Ti/TiN 적층구조나 Ti/TiN/Al/Ti/TiN 적층구조로 형성한다. In this case, the first metal wiring 11 is formed of a Ti / Al / Ti / TiN stacked structure or a Ti / TiN / Al / Ti / TiN stacked structure.

여기서, 상기 Al 은 저항이 낮은 금속으로 전기 신호를 전달하는 역할을 하고, Al 하부의 Ti 는 상기 Al 과 주변구조물과의 접착력을 증가시키는 역할을 하며, TiN 은 후속 패터닝 공정시 반사방지막으로 사용한 것이다. Here, Al serves to transmit an electrical signal to a metal having low resistance, and Ti under Al serves to increase adhesion between the Al and the surrounding structure, and TiN is used as an antireflection film in a subsequent patterning process. .

그 다음, 전체표면상부에 제1층간절연막인 FSG 막(13)을 HDP CVD ( high density plasma chemical vapor deposition ) 방법으로 형성한다. 이때, 상기 FSG 막(13)은 다른 박막에 비하여 많은 파티클 ( particle )(15)을 유발시킨다. Then, the FSG film 13, which is the first interlayer insulating film, is formed on the entire surface by HDP CVD (high density plasma chemical vapor deposition). At this time, the FSG film 13 causes more particles 15 than other thin films.

즉, 상기 FSG 막(13)의 증착 공정시 또는 증착 공정후 많은 파티클(15)이 유 발된다. That is, many particles 15 are induced during or after the deposition of the FSG film 13.

도 1b를 참조하면, 상기 FSG 막(13) 상부에 제2층간절연막인 TEOS ( tetra ethyl ortho silicate ) 막(17)을 증착한다. Referring to FIG. 1B, a TEOS (tetra ethyl ortho silicate) film 17, which is a second interlayer insulating film, is deposited on the FSG film 13.

이때, 상기 TEOS 막(17)은 상기 FSG 막(13) 상부의 파티클(15)을 모두 도포하는 구조로 형성된다. In this case, the TEOS film 17 is formed in a structure in which all the particles 15 on the FSG film 13 are coated.

도 1c를 참조하면, 상기 제2층간절연막인 TEOS 막(17)을 CMP ( chemical mechanical polishing ) 하여 평탄화시킨다. 이때, 상기 파티클(15)이 노출되어 상기 FSG 막(13) 상부로부터 이탈하여 상기 FSG 막(13)을 노출시키는 요부(19)가 형성되며, 상기 CMP 공정시 스크래치에 의한 요부가 형성된다. 여기서, 상기 스크래치는 상기 FSG 막(13) 상에 위치한 작은 파티클이 제거되며 형성된 것이다. Referring to FIG. 1C, the TEOS film 17, which is the second interlayer insulating film, is planarized by chemical mechanical polishing (CMP). In this case, the particles 15 are exposed to form a recess 19 to leave the FSG film 13 from the top to expose the FSG film 13, the recess is formed by the scratch during the CMP process. Here, the scratch is formed by removing small particles located on the FSG film 13.

도 1d를 참조하면, 비아 콘택마스크(미도시)를 이용한 사진식각공정으로 상기 층간절연막들(17,13)을 식각하여 상기 제1금속배선(11)을 노출시키는 비아 콘택홀(21)을 형성한다. Referring to FIG. 1D, a via contact hole 21 exposing the first metal wiring 11 is formed by etching the interlayer insulating layers 17 and 13 by a photolithography process using a via contact mask (not shown). do.

상기 비아 콘택홀(21)을 포함한 전체표면상부에 소정두께의 식각장벽층(23)을 증착한다. An etch barrier layer 23 having a predetermined thickness is deposited on the entire surface including the via contact hole 21.

도 1e 및 도 1f 를 참조하면, 상기 비아콘택홀(21)을 매립하는 텅스텐층(25)을 전체표면상부에 증착하고 이를 평탄화식각하여 상기 비아콘택홀(21)을 매립하는 텅스텐층으로 금속배선 콘택플러그(27)를 형성한다. Referring to FIGS. 1E and 1F, a tungsten layer 25 filling the via contact hole 21 is deposited on the entire surface of the tungsten layer and planarized and etched to form a tungsten layer filling the via contact hole 21. The contact plug 27 is formed.

이때, 상기 텅스텐층(25)은 상기 요부(19) 역시 매립한다. In this case, the tungsten layer 25 also embeds the recess 19.

상기 요부(19)를 매립하는 텅스텐층(25)은 후속 공정으로 형성되는 금속배선 간의 브릿지 ( bridge ) 를 유발시키는 원인이 된다. The tungsten layer 25 filling the recess 19 causes a bridge between the metal wires formed in a subsequent process.

도 2 는 상기 도 1a 의 공정으로 FSG 막(13)을 증착한 후의 평면 사진으로서, 파티클이 유발된 것을 도시한다. FIG. 2 is a planar photograph after the FSG film 13 is deposited by the process of FIG. 1A, showing that particles are induced.

도 3 은 상기 도 1f 의 공정으로 상기 요부(도 1c의 19)를 매립하는 텅스텐층(도 1f의 25)을 도시한 평면 사진이다. FIG. 3 is a planar photograph showing a tungsten layer (25 in FIG. 1F) filling the recess (19 in FIG. 1C) by the process of FIG. 1F.

도 4 는 상기 도 1f 의 공정후에 제2금속배선(미도시)을 패터닝한 것을 도시한 평면 사진으로서, 요부(도 1c의 19)를 매립하는 텅스텐층(도 1f의 25)으로 인하여 브릿지가 유발된 것을 도시한 것이다. FIG. 4 is a plan view showing the patterning of the second metal wiring (not shown) after the process of FIG. 1F. The bridge is caused by the tungsten layer (25 of FIG. 1F) filling the recess (19 of FIG. 1C). It is shown.

이상에서 설명한 바와 같이 종래기술에 따른 반도체소자의 층간절연막 형성방법은, 금속배선 간의 층간절연막인 FSG 막과 TEOS 막의 적층구조 형성공정으로 인하여 금속배선 간의 브릿지가 유발될 수 있어 반도체소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다. As described above, in the method of forming an interlayer insulating film of a semiconductor device according to the prior art, a bridge between metal wirings may be caused by a process of forming a laminated structure of an FSG film and a TEOS film, which is an interlayer insulating film between metal wirings, and thus, characteristics and reliability of the semiconductor device. There is a problem in that it is difficult to reduce the resulting high integration of the semiconductor device.

본 발명은 상기한 종래기술에 따른 문제점을 해결하기 위하여, 금속배선 간의 층간절연막을 FSG 막의 단일층으로 형성하여 파티클로 인한 브릿지 현상을 방지할 수 있도록 하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 층간절연막 형성방법을 제공하는데 그 목적이 있다. In order to solve the problems according to the related art, the interlayer insulating film between metal wirings can be formed as a single layer of the FSG film to prevent bridge phenomenon caused by particles, thereby improving the characteristics and reliability of the semiconductor device. It is an object of the present invention to provide a method for forming an interlayer insulating film of a semiconductor device.

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 층간절연막 형성방법은, In order to achieve the above object, an interlayer insulating film forming method of a semiconductor device according to the present invention,                     

제1금속배선이 구비되는 반도체기판 상부에 층간절연막인 FSG 막을 형성하는 공정과,Forming an FSG film, which is an interlayer insulating film, on the semiconductor substrate provided with the first metal wiring;

상기 FSG 막을 플라즈마 식각 및 CMP 하여 상기 FSG 막 증착 공정시 또는 증착 공정시 유발되는 파티클을 제거하는 공정과,Plasma etching and CMP the FSG film to remove particles caused during the FSG film deposition process or during the deposition process;

후속 공정으로, 비아콘택플러그를 형성하는 공정을 포함하는 것과,In a subsequent step, including the step of forming the via contact plug,

상기 FSG 막은 13000 ～ 25000 Å 두께로 형성하는 것과,The FSG film is formed to a thickness of 13000 ~ 25000 mm 3,

상기 플라즈마 식각공정은 CHF3/CF4/Ar/N2/O2 의 가스를 이용하거나 CxFy/O2/Ar/N2 의 가스를 이용하여 실시하는 것을 특징으로 한다. ( 단, CxFy 의 x 및 y 는 자연수 ) The plasma etching process may be performed using a gas of CHF 3 / CF 4 / Ar / N 2 / O 2 or using a gas of CxFy / O 2 / Ar / N 2. (Where x and y of CxFy are natural numbers)

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 5a 내지 도 5c 는 본 발명의 실시예에 따른 반도체소자의 층간절연막 형성방법을 도시한 단면도이다. 5A through 5C are cross-sectional views illustrating a method for forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

도 5a를 참조하면, 반도체기판(미도시) 상에 하부절연층(미도시)을 형성한다. Referring to FIG. 5A, a lower insulating layer (not shown) is formed on a semiconductor substrate (not shown).

그 다음, 상기 반도체기판에 접속되는 제1금속배선(41)을 형성한다. Next, a first metal wiring 41 connected to the semiconductor substrate is formed.

이때, 상기 제1금속배선(41)은 Ti/Al/Ti/TiN 적층구조나 Ti/TiN/Al/Ti/TiN 적층구조로 형성한다. In this case, the first metal wiring 41 is formed of a Ti / Al / Ti / TiN stacked structure or a Ti / TiN / Al / Ti / TiN stacked structure.

여기서, 상기 Al 은 저항이 낮은 금속으로 전기 신호를 전달하는 역할을 하고, Al 하부의 Ti 는 상기 Al 과 주변구조물과의 접착력을 증가시키는 역할을 하며, TiN 은 후속 패터닝 공정시 반사방지막으로 사용한 것이다. Here, Al serves to transmit an electrical signal to a metal having low resistance, and Ti under Al serves to increase adhesion between the Al and the surrounding structure, and TiN is used as an antireflection film in a subsequent patterning process. .                     

그 다음, 전체표면상부에 층간절연막인 FSG 막(43)을 HDP CVD 방법으로 형성한다. 이때, 상기 FSG 막(43)은 다른 박막에 비하여 많은 제1 및 제2 파티클(45,47)을 유발시킨다. 여기서, 상기 제1 및 제2 파티클(45,47)은 FSG 막(43)의 증착 공정시 또는 증착 공정후 다량 유발된다. Then, an FSG film 43, which is an interlayer insulating film, is formed on the entire surface by the HDP CVD method. At this time, the FSG film 43 causes more first and second particles 45 and 47 than other thin films. Here, the first and second particles 45 and 47 are caused in a large amount during the deposition process of the FSG film 43 or after the deposition process.

상기 FSG 막(43)은 13000 ～ 25000 Å 두께로 형성한 것이다. The FSG film 43 is formed to have a thickness of 13000 to 25000 mm 3.

도 5b를 참조하면, 상기 FSG 막(43)을 플라즈마 식각하여 상기 FSG 막(43)의 표면 및 내부의 제1 및 제2 파티클(45,47)을 제거한다. 여기서, 상기 플라즈마 식각공정은 상기 FSG 막(47) 표면에 형성된 파티클이 주로 제거된다. Referring to FIG. 5B, the FSG film 43 is plasma etched to remove the first and second particles 45 and 47 from the surface and the inside of the FSG film 43. Here, in the plasma etching process, particles formed on the surface of the FSG film 47 are mainly removed.

이때, 상기 플라즈마 식각공정은 CHF3/CF4/Ar/N2/O2 의 가스를 이용하거나 CxFy/O2/Ar/N2 의 가스를 이용하여 실시한다. 여기서, CxFy 의 x 및 y 는 자연수이다. In this case, the plasma etching process is performed using a gas of CHF 3 / CF 4 / Ar / N 2 / O 2 or using a gas of CxFy / O 2 / Ar / N 2. Here, x and y of CxFy are natural numbers.

도 5c를 참조하면, 상기 FSG 막(43)을 평탄화식각한다. 이때, 상기 평탄화 식각공정은 CMP 공정으로 실시한다. Referring to FIG. 5C, the FSG film 43 is planarized etched. In this case, the planarization etching process is performed by a CMP process.

후속 공정으로, 제1금속배선(41)에 콘택되는 제2금속배선(미도시)을 형성한다. In a subsequent process, a second metal wiring (not shown) is formed to contact the first metal wiring 41.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 층간절연막 형성방법은, 금속배선 간의 층간절연막을 FSG 막 및 TEOS 막의 적층구조에서 FSG 막의 단일층으로 형성하여 공정을 단순화시키고 그에 따른 생산 단가를 절감시키며 파티클에 의한 브릿지 현상을 방지할 수 있어 반도체소자의 특성 및 신뢰성을 향상시키 는 효과를 제공한다. As described above, the method for forming an interlayer insulating film of a semiconductor device according to the present invention is to form an interlayer insulating film between metal wirings as a single layer of an FSG film in a lamination structure of an FSG film and a TEOS film, thereby simplifying a process and reducing a production cost accordingly. Bridge phenomenon caused by particles can be prevented to provide an effect of improving the characteristics and reliability of the semiconductor device.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (3)

제1금속배선이 구비되는 반도체기판 상부에 층간절연막인 FSG 막을 형성하는 공정과,Forming an FSG film, which is an interlayer insulating film, on the semiconductor substrate provided with the first metal wiring; 상기 FSG 막을 플라즈마 식각 및 CMP 하여 상기 FSG 막 증착 공정시 또는 증착 공정시 유발되는 파티클을 제거하는 공정과,Plasma etching and CMP the FSG film to remove particles caused during the FSG film deposition process or during the deposition process; 후속 공정으로, 비아콘택플러그를 형성하는 공정을 포함하는 반도체소자의 층간절연막 형성방법.A method of forming an interlayer insulating film of a semiconductor device, which comprises a subsequent step, forming a via contact plug. 제 1 항에 있어서, The method of claim 1, 상기 FSG 막은 13000 ～ 25000 Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 층간절연막 형성방법.Wherein the FSG film is formed to a thickness of 13000 to 25000 Å. 제 1 항에 있어서, The method of claim 1, 상기 플라즈마 식각공정은 CHF3/CF4/Ar/N2/O2 의 가스를 이용하거나 CxFy/O2/Ar/N2 의 가스를 이용하여 실시하는 것을 특징으로 하는 반도체소자의 층간절연막 형성방법. ( 단, CxFy 의 x 및 y 는 자연수 ) The plasma etching process is performed using a gas of CHF3 / CF4 / Ar / N2 / O2 or CxFy / O2 / Ar / N2 gas of the insulating film forming method of a semiconductor device. (Where x and y of CxFy are natural numbers)
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