KR20060060207A - Method for filling gap in semiconductor device - Google Patents

Method for filling gap in semiconductor device Download PDF

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KR20060060207A
KR20060060207A KR1020040099125A KR20040099125A KR20060060207A KR 20060060207 A KR20060060207 A KR 20060060207A KR 1020040099125 A KR1020040099125 A KR 1020040099125A KR 20040099125 A KR20040099125 A KR 20040099125A KR 20060060207 A KR20060060207 A KR 20060060207A
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oxide film
cvd oxide
film
substrate
polysilicon
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KR1020040099125A
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Korean (ko)
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김봉수
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주식회사 하이닉스반도체
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Publication of KR20060060207A publication Critical patent/KR20060060207A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

본 발명은 단차비(aspect ratio)가 큰 영역을 보이드의 발생없이 CVD 산화막으로 완전 매립시키기 위한 반도체 소자의 매립방법을 개시하며, 개시된 본 발명의 매립방법은, 단차비가 큰 영역을 갖는 기판 전면 상에 제1 CVD 산화막을 증착하는 단계; 상기 제1 CVD 산화막 상에 단차비가 큰 영역을 완전 매립하도록 폴리실리콘막을 증착하는 단계; 상기 폴리실리콘막 상에 제2 CVD 산화막을 증착하는 단계; 및 상기 기판 결과물에 대해 산화 공정을 진행하여 폴리실리콘막을 산화막으로 변환시키는 단계;를 포함한다.The present invention discloses a method of embedding a semiconductor device for completely filling a region having a large aspect ratio with a CVD oxide film without generation of voids. Depositing a first CVD oxide film on the substrate; Depositing a polysilicon film so as to completely fill a region having a high step ratio on the first CVD oxide film; Depositing a second CVD oxide film on the polysilicon film; And converting the polysilicon film into an oxide film by performing an oxidation process on the substrate resultant.

Description

반도체 소자의 매립방법{Method for filling gap in semiconductor device}Method for filling gap in semiconductor device

도 1 내지 도 6은 본 발명의 실시예에 따른 STI 형성방법을 나타낸 공정 단면도.1 to 6 is a cross-sectional view showing a method of forming an STI according to an embodiment of the present invention.

도 7 및 8은 본 발명의 실시예에 따른 층간절연막 형성방법을 나타낸 공정 단면도.7 and 8 are cross-sectional views illustrating a method of forming an interlayer insulating film according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

11: 기판 12: 패드산화막11: substrate 12: pad oxide film

13: 패드질화막 14: 질화막13: pad nitride film 14: nitride film

15: 제 1 CVD 산화막 16: 폴리실리콘 15: first CVD oxide film 16: polysilicon

17: 제 2 CVD 산화막17: second CVD oxide film

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히, 단차비(aspect ratio)가 큰 영역을 보이드의 발생없이 CVD 산화막으로 완전 매립시키기 위한 반도체 소자의 매립방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for embedding a semiconductor device for completely filling a region having a large aspect ratio with a CVD oxide film without generation of voids.

반도체 소자의 디자인 룰이 점점 축소되면서, 반도체 공정중 좁은 패턴 사이 의 매립이 큰 문제로 대두되고 있다. 이것은, PETEOS, USG, TEOS 산화막과 같은 스텝 커버리지가 불량한 CVD 산화막으로는 매립을 보이드 없이 수행하는 것이 어려워졌기 때문이다. 또한, 차세대 고집적 소자에서 워드라인, 비트라인과 같은 전도라인 사이의 매립을 위해 사용되는 층간절연막은 하부층의 리프팅을 방지하기 위해 저온 증착 특성이 요구되며, 높은 단차비를 가지는 패턴 사이에서 우수한 매립 특성이 요구되고 있다.As the design rules of semiconductor devices are gradually reduced, the filling of narrow patterns between semiconductor processes has become a big problem. This is because it is difficult to perform buried without voids with CVD oxide films having poor step coverage such as PETEOS, USG, and TEOS oxide films. In addition, interlayer insulating films used for embedding between conductive lines such as word lines and bit lines in the next generation of highly integrated devices require low temperature deposition characteristics to prevent lifting of lower layers, and excellent embedding characteristics between patterns having high step ratios. This is required.

이에, 저온 증착 특성 및 매립 특성을 동시에 만족시킬 수 있는 고밀도 플라즈마 산화막이 고집적 소자의 층간절연막으로 각광 받고 있다. 고밀도 플라즈마 산화막은 증착과 식각이 동시에 진행되기 때문에 한번의 증착으로 기존의 증착/식각/증착 공정을 대체하여 우수한 매립 특성을 보이게 된다.Accordingly, a high density plasma oxide film capable of satisfying low temperature deposition characteristics and buried characteristics at the same time has been spotlighted as an interlayer insulating film of a highly integrated device. Since the high-density plasma oxide film is deposited and etched at the same time, it shows excellent landfill characteristics by replacing the existing deposition / etch / deposition process with one deposition.

그러나, 0.13 ㎛ 디자인 룰 이상의 고집적 소자 제조시에는 고밀도 플라즈마 산화막으로도 매립하기 어려운 좁은 패턴 간극이 나타나고 있다. 물론, 좁은 패턴 간극을 매립하기 위하여 식각비를 늘이면 매립특성은 향상될 수 있지만, 이 경우에는 이미 형성된 하부 패턴에 손상을 가하여 여러가지 문제를 유발하게 된다. 또한, 고밀도 플라즈마 산화막은 새로운 공정장비를 필요로 하므로, 비용측면에서 불리함이 있다.However, when fabricating highly integrated devices having a design rule of 0.13 µm or more, a narrow pattern gap is difficult to be embedded even with a high density plasma oxide film. Of course, when the etch ratio is increased to fill the narrow pattern gap, the buried characteristics can be improved, but in this case, damage to the already formed lower pattern causes various problems. In addition, since the high density plasma oxide film requires new process equipment, there is a disadvantage in terms of cost.

따라서, 본 발명은 상기한 바와 같은 종래기술의 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 기존의 장비를 그대로 사용하면서 보이드의 발생 없이 높은 단차비를 갖는 영역을 완전 매립을 할 수 있는 반도체 소자의 매립방법 을 제공함에 있다.Therefore, the present invention was created to solve the problems of the prior art as described above, an object of the present invention is to completely fill the region having a high step ratio without the generation of voids while using the existing equipment as it is The present invention provides a method for embedding a semiconductor device.

상기 목적을 달성하기 위해, 본 발명의 일면에 따라, 단차비(aspect ratio)가 큰 영역을 보이드의 발생없이 CVD 산화막으로 완전 매립시키기 위한 반도체 소자의 매립방법이 제공되고: 이 방법은, 단차비가 큰 영역을 갖는 기판 전면 상에 제1 CVD 산화막을 증착하는 단계; 상기 제1 CVD 산화막 상에 단차비가 큰 영역을 완전 매립하도록 폴리실리콘막을 증착하는 단계; 상기 폴리실리콘막 상에 제2 CVD 산화막을 증착하는 단계; 및 상기 기판 결과물에 대해 산화 공정을 진행하여 폴리실리콘막을 산화막으로 변환시키는 단계;를 포함한다.In order to achieve the above object, according to one aspect of the present invention, a method of embedding a semiconductor device for completely filling a region having a large aspect ratio with a CVD oxide film without generation of voids is provided. Depositing a first CVD oxide film on the entire surface of the substrate having a large area; Depositing a polysilicon film so as to completely fill a region having a high step ratio on the first CVD oxide film; Depositing a second CVD oxide film on the polysilicon film; And converting the polysilicon film into an oxide film by performing an oxidation process on the substrate resultant.

본 발명의 다른 일면에 따라, 상기 기판 결과물에 대한 산화 공정은 700∼1000℃의 온도로 수행한다.According to another aspect of the invention, the oxidation process for the substrate product is carried out at a temperature of 700 ~ 1000 ℃.

(실시예)(Example)

이하, 첨부된 도면을 참고하여 본 발명의 바람직한 실시예를 상술하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 설명하면, 본 발명은 폴리실리콘이 산화할 때 부피가 팽창하는 특성을 이용하여 보이드의 발생없이 높은 단차비를 갖는 영역의 완전 매립을 달성한다. 즉, 단차비가 큰 영역을 매립하는 공정에서 CVD 산화막 사이에 폴리실리콘막을 증착하고 기판에 산화공정을 실시하면, 폴리실리콘이 산화되면서 부피가 팽창하여 보이드를 제거하므로 매립특성을 향상시킬 수 있다.First, describing the technical principle of the present invention, the present invention utilizes the characteristic that the volume expands when the polysilicon is oxidized to achieve complete filling of a region having a high step ratio without generation of voids. That is, when the polysilicon film is deposited between the CVD oxide films and the oxidation process is performed on the substrate in the process of filling the region having a large step ratio, the buried characteristics may be improved because the volume is expanded while the polysilicon is oxidized.

본 발명의 매립방법은 단차비가 큰 영역을 갖는 기판 전면 상에 제1 CVD 산 화막을 증착하는 단계; 상기 제1 CVD 산화막 상에 단차비가 큰 영역을 완전 매립하도록 폴리실리콘막을 증착하는 단계; 상기 폴리실리콘막 상에 제2 CVD 산화막을 증착하는 단계; 및 상기 기판 결과물에 대해 산화 공정을 진행하여 폴리실리콘막을 산화막으로 변환시키는 단계;를 포함하며, 상기 기판 결과물에 대한 산화 공정은 700∼1000℃의 온도로 수행한다.The buried method of the present invention comprises the steps of depositing a first CVD oxide film on the entire surface of the substrate having a large step ratio; Depositing a polysilicon film so as to completely fill a region having a high step ratio on the first CVD oxide film; Depositing a second CVD oxide film on the polysilicon film; And converting the polysilicon film into an oxide film by performing an oxidation process on the substrate product, wherein the oxidation process of the substrate product is performed at a temperature of 700 to 1000 ° C.

본 발명은 소자분리막 형성시 보이드 없이 트렌치를 매립하는 공정 및 반도체 소자의 고집적화에 따라 문제가 되는 게이트간 절연막을 형성하는 공정에 사용될 수 있다.The present invention can be used in the process of filling the trench without voids in forming the device isolation film and in the process of forming the inter-gate insulating film which is problematic due to the high integration of the semiconductor device.

도 1 내지 도 6은 본 발명의 실시예에 따른 반도체 소자의 STI 형성방법을 나타낸 공정 단면도이다.1 to 6 are cross-sectional views illustrating a method of forming an STI of a semiconductor device according to an embodiment of the present invention.

도 1을 참조하면, 액티브 영역 및 필드 영역을 갖는 반도체 기판(11) 상에 패드 산화막(12)과 패드 질화막(13)을 형성한다.Referring to FIG. 1, a pad oxide film 12 and a pad nitride film 13 are formed on a semiconductor substrate 11 having an active region and a field region.

도 2를 참조하면, 기판 필드 영역을 노출시키는 감광막 패턴(미도시)을 이용해서 패드질화막(13)을 식각한 후, 식각된 패드질화막(13)을 식각장벽으로 하여 패드산화막(12)과 그 아래의 기판(11)을 식각하여 트렌치를 형성한다.Referring to FIG. 2, after the pad nitride layer 13 is etched using a photoresist pattern (not shown) exposing the substrate field region, the pad oxide layer 12 and the pad oxide layer 13 are etched as an etch barrier. The lower substrate 11 is etched to form trenches.

도 3을 참조하면, 기판(11)의 산화를 방지하기 위해 트렌치를 포함한 기판 전면 상에 질화막(14)을 증착한다. 이어서, 질화막(14) 상에 제 1 CVD 산화막(15)을 증착하고, 제 1 CVD 산화막(15) 상에 트렌치를 완전 매립하도록 폴리실리콘막(16)을 증착한다. 그런 다음, 폴리실리콘막(16) 상에 제 2 CVD 산화막(17)을 증착한다. Referring to FIG. 3, the nitride film 14 is deposited on the entire surface of the substrate including the trench to prevent oxidation of the substrate 11. Subsequently, a first CVD oxide film 15 is deposited on the nitride film 14, and a polysilicon film 16 is deposited so as to completely fill the trench on the first CVD oxide film 15. Then, a second CVD oxide film 17 is deposited on the polysilicon film 16.                     

도 4를 참조하면, 기판 결과물에 대해 산화공정을 진행하여 제 1 CVD 산화막(15), 폴리실리콘막(16), 제 2 CVD 산화막(17)을 산화시킨다. 산화 공정은 700∼1000℃의 온도에서 진행한다. 여기서, 제 1 및 제 2 CVD 산화막(15,17) 사이의 폴리실리콘(16)이 산화되면서 부피가 증가하여 보이드를 제거함으로써 매립특성이 향상된다.Referring to FIG. 4, an oxidation process is performed on the substrate resultant to oxidize the first CVD oxide film 15, the polysilicon film 16, and the second CVD oxide film 17. The oxidation process proceeds at a temperature of 700 to 1000 ° C. Here, the embedding characteristics are improved by removing the voids by increasing the volume as the polysilicon 16 between the first and second CVD oxide films 15 and 17 is oxidized.

도 5 및 6을 참조하면, CMP를 진행하여 산화막(18)을 격리시킨 다음, 질화막(14)을 제거하여 STI를 완성한다.5 and 6, the CMP is performed to isolate the oxide film 18, and then the nitride film 14 is removed to complete the STI.

도 7 및 도 8은 본 발명의 기술적 원리를 이용한 반도체 소자의 층간절연막 형성방법을 설명하기 위한 공정 단면도이다.7 and 8 are cross-sectional views illustrating a method of forming an interlayer insulating film of a semiconductor device using the technical principles of the present invention.

도 7을 참조하면, 소자분리막(22)이 형성되고, 게이트(23) 및 소오스/드레인 영역(미도시)을 포함하는 트랜지스터가 형성된 반도체 기판(21) 상에 게이트(23)를 포함한 기판 전면을 덮도록 실리콘 질화막(24)을 증착한다. 실리콘 질화막은 후속 산화공정시 기판의 산화를 방지하기 위한 것이다. 이어서, 실리콘 질화막(24) 상에 제 1 CVD 산화막(25)을 증착하고, 제 1 CVD 산화막(25) 상에 게이트(23) 사이를 완전 매립하도록 폴리실리콘막(26)을 증착한다. 그런다음, 폴리실리콘막(26) 상에 제 2 CVD 산화막(27)을 증착한다.Referring to FIG. 7, an entire surface of a substrate including a gate 23 is formed on a semiconductor substrate 21 on which a device isolation layer 22 is formed and a transistor including a gate 23 and a source / drain region (not shown) is formed. A silicon nitride film 24 is deposited to cover. The silicon nitride film is intended to prevent oxidation of the substrate during the subsequent oxidation process. Subsequently, a first CVD oxide film 25 is deposited on the silicon nitride film 24, and a polysilicon film 26 is deposited on the first CVD oxide film 25 so as to completely fill the gaps between the gates 23. Then, a second CVD oxide film 27 is deposited on the polysilicon film 26.

도 8을 참조하면, 기판 결과물에 대해 산화공정을 진행하여 제 1 CVD 산화막(25), 폴리실리콘막(26) 및 제 2 CVD 산화막(27)을 산화시킨다. 산화공정은 700∼1000℃의 온도에서 진행하며, 폴리실리콘이 산화되면서 부피가 팽창하여 보이드를 제거할 수 있다.Referring to FIG. 8, an oxidation process is performed on the substrate resultant to oxidize the first CVD oxide film 25, the polysilicon film 26, and the second CVD oxide film 27. The oxidation process is carried out at a temperature of 700 ~ 1000 ℃, the volume is expanded as the polysilicon is oxidized to remove the voids.

본 발명의 상기한 바와 같은 구성에 따라, CVD 산화막 사이에 폴리실리콘을 증착하고 폴리실리콘을 산화시켜 부피를 팽창시킴으로써, 단차비가 높은 영역을 보이드 없이 완전매립할 수 있으며, 이에 따라, 본 발명은 소자특성을 향상시킬 수 있다.According to the configuration as described above of the present invention, by depositing polysilicon between the CVD oxide film and oxidizing the polysilicon to expand the volume, a region having a high step ratio can be completely buried without voids. Properties can be improved.

본 발명을 특정의 바람직한 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니고 이하의 특허청구의 범위에 의해 마련되는 본 발명의 정신이나 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변화될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자는 용이하게 알 수 있다.While the invention has been shown and described with respect to certain preferred embodiments thereof, the invention is not so limited and it is intended that the invention be limited without departing from the spirit or field of the invention as set forth in the following claims It will be readily apparent to one of ordinary skill in the art that various modifications and variations can be made.

Claims (2)

단차비(aspect ratio)가 큰 영역을 보이드의 발생없이 CVD 산화막으로 완전 매립시키기 위한 반도체 소자의 매립방법으로서, A method of embedding a semiconductor device for completely filling a region having a large aspect ratio with a CVD oxide film without generation of voids, 단차비가 큰 영역을 갖는 기판 전면 상에 제1 CVD 산화막을 증착하는 단계; Depositing a first CVD oxide film on the entire surface of the substrate having a region having a high step ratio; 상기 제1 CVD 산화막 상에 단차비가 큰 영역을 완전 매립하도록 폴리실리콘막을 증착하는 단계; Depositing a polysilicon film so as to completely fill a region having a high step ratio on the first CVD oxide film; 상기 폴리실리콘막 상에 제2 CVD 산화막을 증착하는 단계; 및 Depositing a second CVD oxide film on the polysilicon film; And 상기 기판 결과물에 대해 산화 공정을 진행하여 폴리실리콘막을 산화막으로 변환시키는 단계;를 포함하는 것을 특징으로 하는 반도체 소자의 매립방법.And converting the polysilicon film into an oxide film by performing an oxidation process on the resultant of the substrate. 제 1 항에 있어서,The method of claim 1, 상기 기판 결과물에 대한 산화 공정은 700∼1000℃의 온도로 수행하는 것을 특징으로 하는 반도체 소자의 매립방법.The method of embedding a semiconductor device, characterized in that the oxidation process for the substrate product is carried out at a temperature of 700 ~ 1000 ℃.
KR1020040099125A 2004-11-30 2004-11-30 Method for filling gap in semiconductor device KR20060060207A (en)

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