KR20060042361A - Method for manufacturing dual gate transistor - Google Patents

Method for manufacturing dual gate transistor Download PDF

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KR20060042361A
KR20060042361A KR1020040091005A KR20040091005A KR20060042361A KR 20060042361 A KR20060042361 A KR 20060042361A KR 1020040091005 A KR1020040091005 A KR 1020040091005A KR 20040091005 A KR20040091005 A KR 20040091005A KR 20060042361 A KR20060042361 A KR 20060042361A
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film
forming
gate
conductive film
region
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KR1020040091005A
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Korean (ko)
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남상혁
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement

Abstract

본 발명은 다양한 성능의 트랜지스터를 함께 집적화할 수 있는 듀얼 게이트 트랜지스터 제조 방법을 제공하기 위한 것으로, 이를 위한 반도체 소자 제조 방법은 반도체 기판 상부에 패드막을 형성하는 단계; 제 1영역의 상기 패드막을 제거하고 드러난 기판 상에 제 1게이트 유전체를 형성하는 단계; 결과물의 전면에 제 1전도막을 형성하는 단계; 소자분리 마스크 및 식각 공정으로 트렌치를 형성하는 단계; 결과물 상에 소자분리용 절연막을 증착하고 제 2영역의 상기 패드막이 드러나도록 CMP 하는 단계; 제 2영역의 패드막을 제거하고 제 2게이트 유전체를 형성하는 단계; 결과물 상에 제 2전도막을 증착하고 상기 제 2전도막이 드러나도록 CMP하는 단계; 및 게이트 마스크 및 식각 공정으로 상기 제 1 및 제 2영역에 각각 게이트 패턴을 형성하는 단계를 포함한다.
The present invention provides a method of manufacturing a dual gate transistor capable of integrating transistors of various performances together. The method of manufacturing a semiconductor device includes: forming a pad layer on a semiconductor substrate; Removing the pad layer in the first region and forming a first gate dielectric on the exposed substrate; Forming a first conductive film on the entire surface of the resultant product; Forming a trench by an isolation mask and an etching process; Depositing an insulating film for device isolation on a resultant material and CMP to expose the pad film of a second region; Removing the pad film of the second region and forming a second gate dielectric; Depositing a second conductive film on the resultant and CMP to expose the second conductive film; And forming a gate pattern in the first and second regions, respectively, by a gate mask and an etching process.

게이트 패턴, 게이트산화막, 게이트 유전체 Gate pattern, gate oxide, gate dielectric

Description

듀얼 게이트 트랜지스터 제조 방법{METHOD FOR MANUFACTURING DUAL GATE TRANSISTOR} METHOOD FOR MANUFACTURING DUAL GATE TRANSISTOR             

도 1은 통상적인 듀얼 게이트 트랜지스터의 구조를 나타낸 공정 단면도,1 is a process cross-sectional view showing a structure of a conventional dual gate transistor;

도 2a 내지 도 2i는 본 발명의 실시예에 따른 듀얼 게이트 트랜지스터 제조 방법을 도시한 공정 단면도.
2A to 2I are cross-sectional views illustrating a method of manufacturing a dual gate transistor according to an exemplary embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

20 : 제 1게이트 유전체 21 : 반도체 기판 20: first gate dielectric 21: semiconductor substrate

22 : 완충 산화막 23 : 질화막 22: buffer oxide film 23: nitride film

24 : 제 1전도막 25 : 소자분리마스크24: first conductive film 25: device isolation mask

26 : 소자분리절연막 27 : 제 2게이트 유전체26 device isolation layer 27 second gate dielectric

28 : 제 2전도막 29 : 제 3전도막28: second conductive film 29: third conductive film

A : 제 1영역 B : 제 2영역  A: first area B: second area

C : 트렌치
C: trench

본 발명은 트랜지스터 제조 기술에 관한 것으로, 특히 듀얼 게이트 트랜지스터(dual gate transistor) 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to transistor manufacturing technology, and more particularly to a method of manufacturing a dual gate transistor.

종래 듀얼 게이트전극은 반도체 기판 상에 동일한 게이트절연막, 동일한 게이트전극을 형성하여 만들어진다. 따라서 셀영역 및 주변회로영역에 동일한 게이트전극을 갖는다.The conventional dual gate electrode is made by forming the same gate insulating film and the same gate electrode on a semiconductor substrate. Therefore, the same gate electrode is provided in the cell region and the peripheral circuit region.

도 1은 통상적인 듀얼 게이트 트랜지스터의 구조를 도시한 공정 단면도이다.1 is a process sectional view showing the structure of a conventional dual gate transistor.

도 1에 도시된 바와 같이, 소자분리영역(12)이 형성된 반도체 기판(11) 상에 게이트절연막(13), 게이트 전극용 폴리실리콘막(14)을 차례로 형성한다. 그리고 마스크 패턴(도시생략)을 폴리실리콘막(14)에 N 타입 또는 P 타입 이온주입을 하여, NMOS에는 N형 폴리실리콘, PMOS에는 P형 폴리실리콘으로 게이트 전극이 만들어진다.As shown in FIG. 1, a gate insulating film 13 and a polysilicon film 14 for a gate electrode are sequentially formed on the semiconductor substrate 11 on which the device isolation region 12 is formed. The mask pattern (not shown) is implanted with N type or P type ion into the polysilicon film 14, and a gate electrode is made of N type polysilicon for NMOS and P type polysilicon for PMOS.

그러나, 상술한 종래 기술에 따라 게이트 전극을 형성하면, N 타입의 게이트전극을 형성할 때, 문턱전압 조절이 힘들고, 주변회로영역 상의 게이트전극의 선폭을 줄이는 것이 어렵다.However, when the gate electrode is formed according to the above-described conventional technique, when the N type gate electrode is formed, it is difficult to adjust the threshold voltage and reduce the line width of the gate electrode on the peripheral circuit region.

또한, 상술한 것처럼 종래 기술을 이용하여 셀영역 및 주변회로영역에 형성되는 듀얼 게이트 트랜지스터는 실리콘 웨이퍼상에서 동일한 물질을 가지고 제작하기 때문에 다양한 성능의 트랜지스터 제조에 있어서 제약이 있다.
In addition, as described above, since the dual gate transistor formed in the cell region and the peripheral circuit region using the conventional technology is manufactured with the same material on the silicon wafer, there are limitations in manufacturing transistors having various performances.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 다양한 성능의 트랜지스터를 함께 집적화할 수 있는 듀얼 게이트 트랜지스터 제조 방법을 제공하는 데 그 목적이 있다.
The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a dual gate transistor capable of integrating transistors of various performances together.

상기 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 반도체 기판 상부에 패드막을 형성하는 단계, 제 1영역의 상기 패드막을 제거하고 드러난 기판 상에 제 1게이트 유전체를 형성하는 단계, 결과물의 전면에 제 1전도막을 형성하는 단계, 소자분리 마스크 및 식각 공정으로 트렌치를 형성하는 단계, 결과물 상에 소자분리용 절연막을 증착하고 제 2영역의 상기 패드막이 드러나도록 CMP 하는 단계, 제 2영역의 패드막을 제거하고 제 2게이트 유전체를 형성하는 단계, 결과물 상에 제 2전도막을 증착하고 상기 제 2전도막이 드러나도록 CMP하는 단계, 및 게이트 마스크 및 식각 공정으로 상기 제 1 및 제 2영역에 각각 게이트 패턴을 형성하는 단계를 포함한다.
A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a pad film on the semiconductor substrate, removing the pad film of the first region and forming a first gate dielectric on the exposed substrate, the front surface of the result Forming a first conductive film in the trench, forming a trench by an isolation mask and an etching process, depositing an isolation film for the isolation of the device on the resultant material, and performing a CMP to expose the pad film in the second region, the pad of the second region Removing the film and forming a second gate dielectric; depositing a second conductive film on the resultant; CMP to expose the second conductive film; and gate patterns in the first and second regions, respectively, by a gate mask and an etching process. Forming a step.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2i는 본 발명의 일실시예에 따른 듀얼 게이트 트랜지스터 제 조 방법을 도시한 공정 단면도이다. 2A to 2I are cross-sectional views illustrating a method of manufacturing a dual gate transistor according to an exemplary embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체 기판(21) 상에 완충 산화막(22), 질화막(23)을 차례로 적층한다. As shown in FIG. 2A, a buffer oxide film 22 and a nitride film 23 are sequentially stacked on the semiconductor substrate 21.

이어서, 도 2b에 도시된 바와 같이, 마스크 및 식각 공정으로 제 1트랜지스터 형성될 영역의 질화막(23) 및 완충 산화막(22)을 제거한다. 이어서, 결과물의 전면에 제 1게이트 산화막(20)과 게이트로 사용할 제 1전도막(24)을 형성한다. 이 때, 사용되는 제 1전도막(24) 물질은 N-type 폴리실리콘막 또는 P-type 폴리실리콘막을 사용할 수 있다.Subsequently, as shown in FIG. 2B, the nitride film 23 and the buffer oxide film 22 in the region where the first transistor is to be formed are removed by a mask and an etching process. Subsequently, a first gate oxide film 20 and a first conductive film 24 to be used as a gate are formed on the entire surface of the resultant product. In this case, the first conductive film 24 used may be an N-type polysilicon film or a P-type polysilicon film.

이어서, 도 2c에 도시된 바와 같이, 제 1전도막(24)상에 소자분리마스크(25)를 이용하여 소자분리영역의 제 1전도막(24a), 질화막(23b) 및 제 1게이트 유전체(20a)를 식각하고, 기판(21)까지 일부 두께 식각하여 트렌치(C)를 형성한다. Subsequently, as illustrated in FIG. 2C, the device isolation mask 25 is used on the first conductive film 24 to form the first conductive film 24a, the nitride film 23b and the first gate dielectric of the device isolation region. 20a) is etched, and a portion of the substrate 21 is etched to form the trench C.

이어서, 도 2d에 도시된 바와 같이, 반도체 기판(21) 전면에 소자분리절연막(26)을 증착하고, 질화막(23b)이 드러날 때까지 화학기계적연마(Cemical Mechanical Polishing; 이하 'CMP'라 칭함)공정을 진행하여 소자분리막(26)을 제작한다. Subsequently, as shown in FIG. 2D, the device isolation insulating film 26 is deposited on the entire surface of the semiconductor substrate 21, and chemical mechanical polishing (hereinafter referred to as “CMP”) until the nitride film 23b is exposed. The process proceeds to fabricate the device isolation film 26.

이어서, 도 2e에 도시된 바와 같이, 제 2트랜지스터가 형성될 영역의 질화막(23b) 및 완충 산화막(22a)을 제거한다. 이 때, 습식 식각을 이용하면, 소자분리막(26a)도 일부 식각된다. Subsequently, as shown in FIG. 2E, the nitride film 23b and the buffer oxide film 22a in the region where the second transistor is to be formed are removed. At this time, when the wet etching is used, the device isolation layer 26a is also partially etched.

이어서, 도 2f에 도시된 바와 같이, 결과물의 전면에 제 2게이트유전체(27)를 성장시킨다. 그리고 결과물의 전면에 제 2전도막(28)을 증착한다. 이 때, 제 2 전도막(28)으로 사용되는 물질은 N-type 폴리실리콘막 또는 P-type 폴리실리콘막을 사용할 수 있다. 제 2전도막(28)은 제 1전도막(24a)과 같은 물질로 형성할 수도 있고, 다른 물질로 형성할 수도 있다.Next, as shown in FIG. 2F, the second gate dielectric 27 is grown on the entire surface of the resultant. Then, the second conductive film 28 is deposited on the entire surface of the resultant product. In this case, an N-type polysilicon film or a P-type polysilicon film may be used as the material used as the second conductive film 28. The second conductive film 28 may be formed of the same material as the first conductive film 24a or may be formed of another material.

이어서, 도 2g에 도시된 바와 같이, CMP 공정을 진행하여 각 영역의 서로 다른 두 종류의 게이트 전도막(24a, 28a)이 모두 드러나도록 한다.Subsequently, as shown in FIG. 2G, the CMP process is performed to expose all two types of gate conductive films 24a and 28a in each region.

이어서, 도 2h에 도시된 바와 같이, CMP 공정을 거친 결과물 상에 제 3전도막(29)을 형성한다. 이 때, 제 3전도막(29)은 사용되는 물질은 텅스텐 또는 텅스텐실리사이드를 사용한다. Subsequently, as illustrated in FIG. 2H, a third conductive film 29 is formed on the resultant that has undergone the CMP process. In this case, the third conductive film 29 uses tungsten or tungsten silicide.

이어서, 도 2i에 도시된 바와 같이, 게이트 마스크 및 식각 공정을 진행하여 게이트 패턴을 형성한다.Subsequently, as shown in FIG. 2I, a gate mask and an etching process are performed to form a gate pattern.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다, 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. It will be understood that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 웨이퍼 상에 서로 다른 게이트전극패턴을 제작할 수 있기 때문에, 다양한 트랜지스터의 조합을 형성할 수 있다. 따라서, 원하는 성능을 갖는트랜지스터를 형성할 수 있고, 게이트 유전체 또는 전도막을 선택하여 트랜지스터의성능을 최적화 할 수 있는 효과가 있다.Since the present invention described above can produce different gate electrode patterns on the wafer, a combination of various transistors can be formed. Therefore, a transistor having a desired performance can be formed, and the gate dielectric or the conductive film can be selected to optimize the performance of the transistor.

Claims (4)

반도체 기판 상부에 패드막을 형성하는 단계;Forming a pad film on the semiconductor substrate; 제 1영역의 상기 패드막을 제거하고 드러난 기판 상에 제 1게이트 유전체를 형성하는 단계;Removing the pad layer in the first region and forming a first gate dielectric on the exposed substrate; 결과물의 전면에 제 1전도막을 형성하는 단계;Forming a first conductive film on the entire surface of the resultant product; 소자분리 마스크 및 식각 공정으로 트렌치를 형성하는 단계;Forming a trench by an isolation mask and an etching process; 결과물 상에 소자분리용 절연막을 증착하고 제 2영역의 상기 패드막이 드러나도록 CMP 하는 단계;Depositing an insulating film for device isolation on a resultant material and CMP to expose the pad film of a second region; 제 2영역의 패드막을 제거하고 제 2게이트 유전체를 형성하는 단계;Removing the pad film of the second region and forming a second gate dielectric; 결과물 상에 제 2전도막을 증착하고 상기 제 2전도막이 드러나도록 CMP하는 단계; 및Depositing a second conductive film on the resultant and CMP to expose the second conductive film; And 게이트 마스크 및 식각 공정으로 상기 제 1 및 제 2영역에 각각 게이트 패턴을 형성하는 단계Forming a gate pattern in the first and second regions, respectively, by a gate mask and an etching process 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제 1항에 있어서,The method of claim 1, 상기 제 1전도막은 N형 폴리실리콘이고, 상기 제 2전도막은 P형 폴리실리콘인 반도체 소자 제조 방법.The first conductive film is an N-type polysilicon, and the second conductive film is a P-type polysilicon. 제 1항에 있어서,The method of claim 1, 상기 제 3전도막은 텅스텐 또는 텅스텐실리사이드를 사용하는 반도체 소자 제조 방법.The third conductive film is a semiconductor device manufacturing method using tungsten or tungsten silicide. 제 1항에 있어서,The method of claim 1, 상기 패드막은 산화막 및 질화막이 적층된 박막인 반도체 소자 제조 방법.The pad film is a semiconductor device manufacturing method of a thin film in which an oxide film and a nitride film are laminated.
KR1020040091005A 2004-11-09 2004-11-09 Method for manufacturing dual gate transistor KR20060042361A (en)

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