KR20030050795A - Method for Fabricating of Semiconductor Device - Google Patents
Method for Fabricating of Semiconductor Device Download PDFInfo
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- KR20030050795A KR20030050795A KR1020010081317A KR20010081317A KR20030050795A KR 20030050795 A KR20030050795 A KR 20030050795A KR 1020010081317 A KR1020010081317 A KR 1020010081317A KR 20010081317 A KR20010081317 A KR 20010081317A KR 20030050795 A KR20030050795 A KR 20030050795A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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Abstract
Description
본 발명은 반도체 소자에 관한 것으로 특히, 게이트 패터닝(Patterning)의 안정성을 높여 생산성을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of improving productivity by increasing stability of gate patterning.
일반적으로, 엔모스 트랜지스터(NMOS Transistor)의 소자 특성을 얻기 위해서는 엔모스 게이트(Gate) 전극의 충분한 도핑이 요구되는데, 만약 엔모스 트랜지스터에 도핑이 충분히 이루어지지 않게 되면 게이트 폴리(Gate Poly)의디플리션(Depletion)이 발생하여 정상적인 소자 동작이 이루어지지 않기 때문이다.In general, in order to obtain device characteristics of an NMOS transistor, sufficient doping of an NMOS gate electrode is required. If the NMOS transistor is not sufficiently doped, a dip of gate poly Depletion occurs and normal device operation is not performed.
이하, 첨부된 도면을 참조하여 종래 기술에 따른 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 제조공정 단면도이다.1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the prior art.
종래 기술에 따른 반도체 소자의 제조방법은 도 1a에 도시된 바와 같이, 소자분리 영역(12)이 형성된 반도체 기판(11)상에 폴리 실리콘막(13)을 형성하고, 상기 폴리 실리콘막(13)상에 제 1 포토레지스트(14)를 도포한다.In the method of manufacturing a semiconductor device according to the related art, as illustrated in FIG. 1A, a polysilicon film 13 is formed on a semiconductor substrate 11 on which an isolation region 12 is formed, and the polysilicon film 13 is formed. The first photoresist 14 is applied onto it.
여기서, 상기 폴리 실리콘막(13)은 미세한 입자 크기를 갖는 주상형(Columnar) 구조를 갖는다.Here, the polysilicon film 13 has a columnar structure having a fine particle size.
이어, 노광 및 현상 공정으로 차후에 엔모스가 형성될 엔모스 지역의 상기 폴리 실리콘막(13)이 노출되도록 상기 제 1 포토레지스트(14)를 패터닝한다.Subsequently, the first photoresist 14 is patterned so that the polysilicon film 13 in the NMOS region where the NMOS is to be formed later is exposed by an exposure and development process.
이어, 패터닝된 제 1 포토레지스트(14)를 마스크로 상기 폴리 실리콘막(13)에 엔-타입(n-Type) 이온을 주입한다. 통상적으로 상기 엔-타입 이온으로 인(Phosphorus) 이온을 이용한다.Subsequently, n-type ions are implanted into the polysilicon layer 13 using the patterned first photoresist 14 as a mask. Typically, phosphorus (Phosphorus) ions are used as the N-type ions.
이어, 상기 제 1 포토레지스트(14)를 제거하고 어닐(Anneal) 공정을 실시하면, 도 1b에 도시된 바와 같이 엔 타입 이온이 주입된 상기 폴리 실리콘막(13)은 상기 주상형 폴리 실리콘(13)막보다 입자 크기가 증가되어 n 타입 폴리 실리콘막(13a)으로 형성된다.Subsequently, when the first photoresist 14 is removed and an annealing process is performed, the polysilicon film 13 into which the N type ions are implanted is implanted as shown in FIG. The particle size is larger than that of the film to form the n-type polysilicon film 13a.
이어, 전면에 제 2 포토레지스트(15)를 도포한다.Next, the second photoresist 15 is coated on the entire surface.
이어, 상기 n 타입 폴리 실리콘막(13a)과 폴리 실리콘막(13)의 일부가 노출되도록 상기 제 2 포토레지스트(15)를 패터닝한다.Next, the second photoresist 15 is patterned such that the n-type polysilicon film 13a and a part of the polysilicon film 13 are exposed.
이어, 상기 패터닝된 제 2 포토레지스트(15)를 마스크로 상기 폴리 실리콘막(13)과 n 타입 폴리 실리콘막(13a)을 선택적으로 제거하여 상기 엔모스 지역에는 상기 n 타입 폴리 실리콘막(13a)으로 엔모스 게이트(13b)를 형성하고 피모스 지역에는 상기 폴리 실리콘막(13)으로 피모스 게이트(13c)를 형성한다.Subsequently, the polysilicon layer 13 and the n-type polysilicon layer 13a are selectively removed by using the patterned second photoresist 15 as a mask to form the n-type polysilicon layer 13a in the NMOS region. The NMOS gate 13b is formed, and the PMOS gate 13c is formed of the polysilicon film 13 in the PMOS region.
이때, 상기 n 타입 폴리 실리콘막(13a)과 폴리 실리콘막(13)의 도핑 상태 및 입자 구조의 차이로 인하여 상기 n 타입 폴리 실리콘막(13a)의 식각 속도가 폴리 실리콘막(13)의 식각 속도보다 빨라지게 되어, 상기 엔모스 게이트(13b)와 피모스 게이트(13c)는 서로 다른 임계치수를 갖게 되며, 상기 엔모스 지역의 반도체 기판(11)이 식각되어 A에 도시된 바와 같이 트랜치(Trench)가 형성되기도 한다.At this time, the etching rate of the n-type polysilicon layer 13a is the etching rate of the polysilicon layer 13 due to the difference in the doping state and the particle structure of the n-type polysilicon layer 13a and the polysilicon layer 13. As it becomes faster, the NMOS gate 13b and the PMOS gate 13c have different threshold dimensions, and the semiconductor substrate 11 in the NMOS region is etched to form a trench as shown in A. ) May be formed.
그러나, 상기와 같은 종래의 반도체 소자의 제조방법은 다음과 같은 문제점이 있다.However, the conventional method of manufacturing a semiconductor device as described above has the following problems.
첫째, n 타입 폴리 실리콘막과 폴리 실리콘막의 식각 속도가 상이하여 엔모스 게이트와 피모스 게이트의 임계치수(CD : Critical Dimension)가 달라지게 되므로 NP 바이어스 문제가 발생된다.First, since the etch rates of the n-type polysilicon film and the polysilicon film are different, the critical dimension (CD) of the NMOS gate and the PMOS gate is changed, thereby causing an NP bias problem.
둘째, n 타입 폴리 실리콘막의 식각 속도가 빨라지므로 엔모스 지역의 반도체 기판이 피모스 지역의 반도체 기판보다 식각 가스에 먼저 노출되므로 게이트 산화막이 식각 가스를 충분히 방어하지 못하는 경우에는 도 1c의 A에 도시된 바와 같이 트랜치와 같은 불량 패턴이 발생된다.Second, since the etch rate of the n-type polysilicon film is increased, the semiconductor substrate of the NMOS region is exposed to the etching gas before the semiconductor substrate of the PMOS region, so that the gate oxide layer does not sufficiently protect the etching gas, as shown in A of FIG. 1C. As shown, a bad pattern such as a trench is generated.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 NP 바이어스 문제 및 패턴 불량을 방지하기 위한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of manufacturing a semiconductor device for preventing the NP bias problem and pattern defects to solve the above problems.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 제조공정 단면도1A to 1C are cross-sectional views of a manufacturing process of a semiconductor device according to the related art.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 제조공정 단면도2A through 2F are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings
21 : 반도체 기판 22 : 소자분리 영역21 semiconductor substrate 22 device isolation region
23 : 게이트 전극 23a : 엔모스 게이트23 gate electrode 23a NMOS gate
23b : 피모스 게이트 24 : TEOS막23b: PMOS gate 24: TEOS film
25 : 포토레지스트25: photoresist
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은 엔모스 영역과 피모스 영역이 정의된 반도체 기판에 복수개의 게이트를 형성하는 단계와, 상기 반도체 기판에 상기 게이트보다 두꺼운 두께의 절연막을 형성하는 단계와, 상기 게이트상에 소정 두께로 상기 절연막이 잔류하도록 상기 절연막을 평탄 제거하는 단계와, 상기 게이트 상부가 노출되도록 상기 평탄 절연막을 소정 두께로 제거하는 단계와, 상기 엔모스 영역 또는 피모스 영역 중 어느 한 영역에 형성된 게이트에만 게이트 이온을 주입하여 엔모스 영역과 피모스 영역 각각에 엔모스 게이트와 피모스 게이트를 형성하는 단계와, 상기 절연막을 완전히 제거하는 단계를 포함하여 형성함을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a plurality of gates in the semiconductor substrate defined the NMOS region and the PMOS region, and a thicker thickness than the gate in the semiconductor substrate Forming an insulating film, removing the flat insulating film so that the insulating film remains at a predetermined thickness on the gate, removing the flat insulating film to a predetermined thickness so that the upper portion of the gate is exposed, and the NMOS region Or implanting gate ions only into a gate formed in one of the PMOS regions to form an NMOS gate and a PMOS gate in each of the NMOS region and the PMOS region, and completely removing the insulating layer. It is characterized by.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 제조공정 단면도이다.2A through 2F are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
우선, 도 2a에 도시된 바와 같이 소자분리 영역(22)이 형성되어 액티브 영역이 정의된 반도체 기판(21)상에 게이트 전극(23)을 형성한다.First, as shown in FIG. 2A, the device isolation region 22 is formed to form the gate electrode 23 on the semiconductor substrate 21 on which the active region is defined.
이때, 상기 게이트 전극(23)은 엔모스 트랜지스터가 형성될 엔모스 지역과피모스 트랜지스터가 형성될 피모스 지역에 형성한다.In this case, the gate electrode 23 is formed in the NMOS region where the NMOS transistor is to be formed and the PMOS region where the PMOS transistor is to be formed.
이어, 도 2b에 도시된 바와 같이 상기 반도체 기판(21)의 전면에 TEOS막(24)을 상기 게이트 전극(23)의 두께보다 200∼2000Å의 두께만큼 두껍게 형성한다.Subsequently, as shown in FIG. 2B, the TEOS film 24 is formed on the entire surface of the semiconductor substrate 21 to be 200 to 2000 Å thicker than the thickness of the gate electrode 23.
이때, 상기 TEOS막(24) 대신에 통상적인 CVD(Chemical Vapor Deposition) 공정 또는 PVD(Physical Vapor Deposition) 공정 내지 스핀 코팅(Spin Coating) 공정으로 형성되는 옥사이드(Oxide) 계열을 물질 이용하여도 무방하다.In this case, instead of the TEOS layer 24, an oxide based material formed by a conventional chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process or a spin coating process may be used. .
이어, 도 2c에 도시된 바와 같이 상기 게이트 전극(23) 상부에 200∼800Å의 두께로 TEOS막(24)이 잔류하도록 CMP(Chemical Mechanical Polishing) 공정을 실시하여 상기 TEOS막(24)을 평탄화한다.Next, as illustrated in FIG. 2C, the TEOS film 24 is planarized by performing a chemical mechanical polishing (CMP) process so that the TEOS film 24 remains on the gate electrode 23 to a thickness of 200 to 800 占 퐉. .
상기 CMP 공정에서 게이트 전극(23) 상부의 TEOS막(24)을 완전히 제거하지 않고 잔류시키므로써 상기 CMP 공정을 통한 게이트 폴리의 손실을 방지할 수 있다.In the CMP process, the TEOS layer 24 on the gate electrode 23 is left without being completely removed, thereby preventing the loss of the gate poly through the CMP process.
이어, 도 2d에 도시된 바와 같이 희석된 HF 수용액이나, BOE(Buffered Oxide Etcher) 등을 이용한 습식 식각 공정 또는 통상의 건식 식각 공정으로 상기 게이트 전극(23)의 상부가 소정 두께로 노출되도록 상기 TEOS막(24)을 900∼1100Å의 두께만큼 제거한다.Subsequently, as shown in FIG. 2D, the TEOS is exposed to a predetermined thickness so that the upper portion of the gate electrode 23 is exposed by a wet etching process or a conventional dry etching process using a diluted HF aqueous solution, BOE (Buffered Oxide Etcher), or the like. The film 24 is removed by a thickness of 900-1100 mm 3.
이어, 도 2e에 도시된 바와 같이 전면에 포토레지스트(25)를 도포하고 노광 및 현상 공정으로 상기 엔모스 지역의 게이트 전극(23) 및 그에 인접한 TEOS막(24)이 노출되도록 상기 포토레지스트(25)를 패터닝한다.Next, as shown in FIG. 2E, the photoresist 25 is coated on the entire surface, and the photoresist 25 is exposed to expose the gate electrode 23 and the TEOS film 24 adjacent to the gate electrode 23 in the NMOS region by an exposure and development process. Pattern).
이어, 패터닝된 포토레지스트(25)를 마스크로 인(P)과 같은 통상의 n 타입 이온을 주입하여 엔모스 게이트 전극(23a)을 형성한다.Subsequently, n-type ions such as phosphorous (P) are implanted using the patterned photoresist 25 to form the NMOS gate electrode 23a.
이때, 상기 포토레지스트(25)에 의해 마스킹되는 피모스 지역의 게이트 전극(23)은 엔모스 게이트 전극(23a)에 대응되는 피모스 게이트 전극(23b)이다.At this time, the gate electrode 23 of the PMOS region masked by the photoresist 25 is the PMOS gate electrode 23b corresponding to the NMOS gate electrode 23a.
그리고, 상기 포토레지스트(25)를 제거한 후, 피모스 게이트 전극(23b)만을 노출하는 마스크를 이용하여 피모스 게이트 전극(23b)만을 선택적으로 도핑하므로써 차후에 형성되는 소오스/드레인 영역과 게이트 전극(23a/23b)을 독립적으로 도핑할 수 있도록 한다.After the photoresist 25 is removed, only the PMOS gate electrode 23b is selectively doped using a mask exposing only the PMOS gate electrode 23b to subsequently form a source / drain region and a gate electrode 23a. / 23b) can be independently doped.
이어, 도 2f에 도시된 바와 같이, 상기 TEOS막(24)을 완전히 제거하여 본 발명의 실시예에 따른 반도체 소자를 완성한다.Subsequently, as shown in FIG. 2F, the TEOS film 24 is completely removed to complete the semiconductor device according to the embodiment of the present invention.
본 발명의 다른 실시예는 상기 엔모스 지역의 게이트 전극(23)을 도핑하는 대신 피모스 지역의 게이트 전극(23)을 도핑하는 방법이다.Another embodiment of the present invention is a method of doping the gate electrode 23 of the PMOS region instead of doping the gate electrode 23 of the NMOS region.
즉, 상기 포토레지스트(25)를 피모스 지역의 게이트 전극(23) 및 그에 인접한 TEOS막(24)이 노출되도록 패터닝한 후, 상기 패터닝된 포토레지스트(25)를 마스크로 통상의 p 타입 이온을 주입하여 피모스 게이트 전극(23b)을 형성하고, 상기 포토레지스트(25)에 의해 마스킹되는 엔모스 지역의 게이트 전극(23)으로 상기 피모스 게이트 전극(23b)에 대응되는 엔모스 게이트 전극(23a)을 형성하는 것이다.That is, after the photoresist 25 is patterned to expose the gate electrode 23 and the TEOS film 24 adjacent to the PMOS region, the p-type ion is patterned using the patterned photoresist 25 as a mask. The PMOS gate electrode 23b is formed by implantation, and the NMOS gate electrode 23a corresponding to the PMOS gate electrode 23b is a gate electrode 23 of the NMOS region masked by the photoresist 25. ) To form.
상기와 같은 본 발명의 반도체 소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing a semiconductor device of the present invention as described above has the following effects.
첫째, 게이트 식각 이후에 게이트 이온을 주입하므로 게이트 식각 공정시 엔모스 게이트 폴리와 피모스 게이트 폴리간의 식각율 차이로 인한 엔모스 게이트와 피모스 게이트의 임계치수를 동일하게 형성할 수 있으므로 NP 바이어스 문제를 방지할 수 있다.First, since gate ions are implanted after the gate etching process, the NMOS gate and PMOS gate poly dimensions can be equally formed in the gate etching process due to the difference in the etching rate between the NMOS gate poly and the PMOS gate poly. Can be prevented.
둘째, 게이트 식각시 엔모스 게이트 폴리와 피모스 게이트 폴리의 식각 속도가 동일하므로 오버 에치로 인한 액티브 영역의 불량 패턴을 방지할 수 있다.Second, since the etch rates of the NMOS gate poly and the PMOS gate poly are the same during gate etching, it is possible to prevent a defective pattern of the active region due to over-etching.
셋째, NP 바이어스 문제 및 불량 패턴을 방지할 수 있으므로 소자의 신뢰성 및 생산성을 향상시킬 수 있다.Third, since the NP bias problem and the bad pattern can be prevented, the reliability and productivity of the device can be improved.
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