JP2008535258A - Construction of fully depleted and partially depleted transistors on the same chip - Google Patents

Abstract

Fully depleted silicon-on-insulator (FD-SOI) transistor (150) and partially-depleted silicon-on-insulator (FD-SOI) transistor (152) in a single integration As part of the circuit manufacturing process flow, a method for forming on a semiconductor substrate (104) is disclosed. A semiconductor device structure manufactured by the method is also disclosed.

Description

  The present invention relates generally to semiconductor devices, and more particularly to fully depleted and partially depleted silicon-on-insulator (SOI) devices in integrated circuit manufacturing processes. Related to manufacturing.

  Semiconductor device geometries are shrinking in size. The demand for higher performance circuits has led to the development of high speed sub-100 nanometer (nm) silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology. In SOI technology, metal oxide semiconductor field effect transistors (MOSFETs) are formed on a thin layer of silicon overlaying a layer of insulating material such as silicon oxide. Devices formed on SOI offer many advantages over their many competitors (counterparts). For example, SOI devices typically have reduced junction capacitance, little to no reverse body effect, soft-erro immunity, complete dielectric Has isolation and little to no latch-up. Therefore, SOI technology allows for high speed performance, higher packing density, and reduced power consumption.

  There are two types of conventional SOI devices. They are partially depleted (PD-SOI) devices and fully depleted SOI (FD-SOI) devices. Conventional PD-SOI transistor devices have a body thickness that is greater than the maximum width of the depletion layer in silicon during device operation. As a result, in operation, PD-SOI devices have a “partial” depletion of the silicon body, while FD-SOI has a “perfect” void in the silicon body. Conventional PD-SOI and FD-SOI devices are planar devices and are therefore formed in the plane of the wafer.

  PD-SOI and FD-SOI devices have their own advantages and disadvantages. For example, PD-SOI devices are readily manufacturable but require a large design load due to the floating body effects associated therewith. More specifically, in PD-SOI devices, charge carriers generated by impact ionization near one source / drain region accumulate in the floating body beneath the transistor channel. obtain. When enough carriers accumulate in the floating body, the body potential is effectively changed.

  The floating body effect occurs in the PD-SOI device due to charge build-up in the floating body region. Such floating body effects can degrade the electrical performance of the circuit by causing kinks in the current-voltage (IV) curve of the device. In general, the body potential of PD-SOI can fluctuate during static, dynamic, or transitional device operation, and the body potential of PD-SOI can be temperature, voltage, circuit topology, and It is a function of many factors such as switching history. Therefore, the circuit design using the PD-SOI element must take such factors into account, and therefore the floating body effect presents a large barrier to the adoption of PD-SOI technology. There are certain circuit applications.

  Another way to avoid the floating body effect in SOI devices is to employ fully depleted SOI (FD-SOI) technology. Since the body is completely depleted during device operation, the FD-SOI device is not affected by the floating body effect. Therefore, FD-SOI technology is relatively design friendly with respect to the floating body effect. FD-SOI devices have better junction capacitance, lower off-state leakage, less soft error, lower operating voltage, and lower gate delay compared to PD-SOI devices. It is also believed to provide.

  Traditionally, in FD-SOI technology, devices with low body doping and / or thin body thickness are used. Further, for good control of the short channel effect, the element body thickness is usually reduced to be less than 1/3 of the gate length. However, this presents some problems of the FD-SOI technology itself. This is because it is difficult to obtain or manufacture an SOI substrate having a uniform ultra-thin Si film (as required for the manufacture of FD-SOI devices having an ultra-thin body). This is because non-uniformity in thickness can lead to large variations in device characteristics and negatively affect manufacturing ease. Furthermore, it is difficult to build an analog transistor, a high voltage I / O transistor, or a transistor having a Vt different from a high performance FD-SOI transistor on the same chip. These types of transistors are more quickly built with PD-SOI transistors.

  As a result, both PD-SOI and FD-SOI transistor elements (where any element can be employed based on circuit application requirements) can be implemented on a single semiconductor substrate while having reliability. It would be useful to be able to form as part of an integrated circuit manufacturing process.

  The present invention relates to a fully depleted silicon-on-insulator (FD-SOI) and a partially-depleted silicon-on-insulator (PD-SOI) as part of an integrated circuit manufacturing process. Related to the formation of transistor elements. The formation of these different types of transistors on the same semiconductor substrate allows to meet different circuit application requirements. For example, FD-SOI transistors can be used when speed and low threshold voltage (Vt's) are important. Similarly, PD-SOI transistors require dynamic Vsub modulation when low off-current is important, when high voltage I / O transistors are required, and when analog transistors are required. Can be used if and / or if multiple transistors with different Vt's are required. Capacitors can also be built from polysilicon and substrate layers, or by other methods. Similarly, bipolar transistors can be manufactured.

  In accordance with one or more features of the present invention, a fully depleted silicon-on-insulator (FD-SOI) transistor and a partially-depleted silicon-on-insulator (PD-SOI) ) A method for forming a transistor as part of an integrated circuit manufacturing process is disclosed. The method includes providing a silicon-on-insulator (SOI) substrate comprising a layer of silicon material formed over a layer of insulating material formed over the semiconductor substrate. The layer of silicon material is suitable for forming a partially depleted transistor by first growing a first growth layer of oxide material over the layer of silicon material. Thinned (here, by growing the first layer of oxide material, the silicon layer is thinned by consuming silicon as part of the growth process). ). A layer of nitride material is then formed over the first growth layer of oxide material. The layer of nitride material, the first growth layer of oxide material, and the layer of silicon material are patterned (eg, etched) into which trenches for isolation regions are formed. Establish. A layer of dielectric material is deposited to fill the trench. This layer of dielectric material is then planarized. The region of the SOI substrate where the partially depleted transistor is to be formed is masked off and the layer of nitride material is removed from the region where the fully depleted transistor is to be formed. Is done. The first growth layer of oxide material is removed in the region where a fully depleted transistor is to be formed. Next, the mask is removed in the region of the SOI substrate where the partially depleted transistor is to be formed. A layer of silicon material in the region where the fully depleted transistor is to be formed is grown by growing a second grown layer of oxide material over the layer of silicon material. Thinned to a thickness suitable for forming a fully depleted transistor. Here, growing the second growth layer of oxide material thins the layer of silicon material by consuming silicon as part of the growth process. Next, the layer of nitride material is removed from the region where the partially depleted transistor is to be formed. The first growth layer of oxide material has been removed in the region where the partially depleted transistor is to be formed, and the second growth layer of oxide material has been fully depleted. It is removed in the region where the transistor is to be formed. Thereafter, a partially depleted transistor is formed in the region where the partially depleted transistor is to be formed, and a fully depleted transistor is formed as a fully depleted transistor. Formed in the power region.

  In accordance with one or more features of the present invention, an integrated circuit is disclosed that includes a fully depleted transistor and a partially depleted transistor formed on a single semiconductor substrate. . Fully depleted and partially depleted transistors are formed as part of an integrated circuit manufacturing process. Here, the fully depleted transistor is a silicon-on-insulator (SOI) of the semiconductor substrate that is thinner than the silicon-on-insulator (SOI) region of the semiconductor substrate where the partially depleted transistor is formed. It is formed in the (SOI) area.

  FIG. 1 illustrates a fully depleted silicon-on-insulator (FD-SOI) and a partially-depleted silicon-on-insulator (FD−) according to one or more features of the present invention. 1 illustrates an exemplary method 10 for forming an (SOI) transistor device in an integrated circuit manufacturing process. Those skilled in the art related to the present invention will appreciate that the method of FIG. 1 can be applied to the manufacture of various and enormous devices, but for illustrative purposes, Related methods related to the exemplary elements shown in FIGS. 2-15 are disclosed. However, this should not be taken in a limited way.

  In method 100 (FIG. 1), silicon-on-insulator (SOI) starting material 102 (FIG. 2) is prepared at 12. The SOI starting material can include a semiconductor substrate 104. A layer 106 of non-conductive insulating material is formed over the substrate. A thin layer 108 of silicon is formed over the layer of insulating material 106 (FIG. 2). The layer of insulating material 106 may comprise, for example, a buried oxide layer (BOX). Similarly, the semiconductor substrate 104 may be a semiconductor body (such as any type of semiconductor wafer or one or more dies on the wafer and any other type of semiconductor layer associated therewith). body) (eg, formed of silicon or SiGe). Illustratively, the layer of silicon 108 may have a thickness between about 800 angstroms and about 1200 angstroms.

  At 14, a first growth layer 112 of oxide-based material is grown over the layer of silicon 108 (FIG. 3). As the first growth layer of oxide material 112 grows, some of the layer of silicon material 108 is consumed as part of the growth process. In this manner, the growth of the layer 112 of oxide material reduces the thickness of the layer 108 of silicon (especially after the first growth layer 112 of oxide material is later removed). By way of example, the first growth layer 112 of oxide material can be formed to a thickness of about 200 angstroms or less, thereby reducing the layer of silicon material to a thickness of about 800 angstroms to about 1000 angstroms. The In any event, the layer of silicon material 112 has a thickness suitable for forming the resulting partially depleted transistor therein.

  At 16 (FIG. 4), a layer 114 of nitride-based material is then deposited over the oxide layer 112. The layer 114 of nitride material may be formed to a thickness of, for example, about 700 angstroms to about 800 angstroms. The layer 114 of nitride material, the first growth layer 112 of oxide material, and the layer 108 of silicon are then patterned 18 and etched away into the trench 118. Form. The trenches are different (within subsequent processing) different SOI in the SOI substrate, where different devices such as fully depleted or partially depleted transistors (FIG. 5) can be formed. Isolate "active" areas or regions 120. While three grooves 118 and four active regions are shown by way of example, it is understood that any suitable number of such regions can be formed by one or more features of the present invention. Will.

  The patterning at 16 can be performed in any suitable manner, for example by lithographic techniques. Here, lithography broadly refers to a process for transferring one or more patterns between various media. In lithography, a light sensitive resist coating (not shown) is formed over one or more layers (eg, layers 114, 112, 108) to which a pattern is to be transferred. The resist coating then exposes it to one or more types of radiation or light that passes (optionally) intervening through the lithography mask containing the pattern. To be patterned. The light causes more or less exposed or unexposed portions of the resist coating to be able to dissolve, depending on the type of resist used. Next, a developer is used to remove more easily soluble areas, leaving a patterned resist. The patterned resist can then be selectively processed (eg, etched) to transfer the pattern to the underlying layer or layers. Act as a mask for.

  Next, at 20 (FIG. 6), a layer 122 of dielectric material, such as an oxide-based material, is deposited. This material 120 fills the grooves 118 between the different active areas 120 and electrically isolates the active areas (and thus the elements formed therein) from each other. It will be appreciated that the layer 122 of dielectric material is preferably deposited rather than grown so that the silicon material 108 is not consumed when the layer 122 of dielectric material is formed. Let's go. The layer 122 of dielectric material can be formed by a chemical vapor deposition process, such as, for example, high pressure chemical vapor deposition (HPCVD). Next, at 22, a planarizing activity, such as chemical mechanical polishing (CMP), is performed to remove excess material 122 and a layer 122 of dielectric material (FIG. 7). Planarize. It will be appreciated that the layer 114 of nitride material may serve as a blocking layer for the CMP process.

  The active area in which the partially depleted transistor is to be formed is then covered at 24 with a layer 126 of masking material, such as resist (FIG. 8). In the illustrated example, two active regions 120a, 120b are shown as being masked off, and two active regions 120c, 120d are shown as not being masked off, while one or It will be appreciated that with more features, any suitable number of regions can (or cannot) be masked off. At 26, the layer 114 of nitride material is removed from the active regions 120c, 120d where a fully depleted transistor is to be formed (FIG. 9). For example, plasma etching may be used to remove the layer 114 of nitride material.

  At 28, a first growth of the oxide material is then performed, for example by stripping or etching this layer of material with a hydrogen fluoride (HF) based agent (FIG. 10). Layer 112 is removed from active areas 120c, 120d. Since the deposited layer 122 of material is formed from the same or similar dielectric material, the extra (unmasked) amount of this layer 122 between the active areas is also at 28 It will be understood that it will be removed. The layer 126 of masking material formed at 24 is then removed from the partially depleted transistor region at 30 (FIG. 11). However, it should be understood that the layer 126 of masking material may be removed before the first growth layer 112 of oxide material is removed.

  At 32, a second growth layer 120 of oxide material is grown over the SOI regions 120c, 120d where a fully depleted transistor is to be formed (FIG. 12). Growing the second growth layer 130 of oxide material consumes some of the silicon 108c, 108d in the regions 120c, 120d as part of the oxide growth process. Thus, growing the second growth layer 130 of oxide material further thins the silicon material 108c, 108d in the regions 120c, 120d (particularly, the second growth layer 130 of oxide material is later removed). After). Illustratively, the second growth layer 130 of oxide material can reduce the layer 108 of silicon material in regions 120c, 120d from about 50 angstroms to about 200 angstroms thick. In any event, the regions of silicon material 108c, 180d within regions 120c, 120d have a thickness suitable for forming the resulting fully depleted transistor therein. The nitride material 114 remaining on the regions 120a, 20b prevents the oxide second growth layer 130 from growing there-over. Will be understood.

  At 34, the layer of nitride material 114 is removed from the active regions 120a, 120b where a partially depleted transistor is to be formed (FIG. 13). For example, a hot phosphoric acid solution and / or plasma etching may be used to remove the layer 114 of nitride material. Next, at 36, the first growth layer 112 of oxide material and the second growth layer 130 of oxide material are formed into layers 112 and 130 using, for example, a hydrogen fluoride (HF) based solution. (Removing (FIG. 14) removes from the active areas 120a, 120b and 120c, 120d, respectively. The deposited layer of material 122 is formed from the same or similar dielectric material. Thus, it will be appreciated that at 36 the extra (unmasked) amount of this layer 122 between the active areas is also removed. Different portions of silicon 108a, 108b, and 108c, 108d having exposed are exposed in active regions 120a, 120b, and 120c, 120d, respectively, where partially depleted and Each fully depleted transistor is formed That.

  Thus, at 38, different transistors can be formed in different regions (FIG. 15). More specifically, a fully depleted silicon-on-insulator (FD-SOI) transistor can be formed in regions 120c, 120d with further thinned silicon 108c, 180d, while partially A depleted silicon-on-insulator (PD-SOI) transistor can be formed in regions 120a, 120b comprising thinned silicon 108a, 108b. While two thinned silicon regions 108a, 108b and further thinned silicon regions 108c, 108d are shown in the illustrated example, depending on one or more features of the present invention, It will be appreciated that an appropriate number of such regions can be fashioned upon a semiconductor substrate. Similarly, in the example, only one FD-SOI transistor 150 is shown, illustrated in the further thinned silicon region 108d, and only one PD-SOI in the thinned silicon region 108a is shown. However, any suitable number of transistors can be formed in different regions 108a, 108b, 108c, 108d. Different transistors can be formed by a constant manufacturing process that varies slightly and / or by selectively exposing different portions of a region to different processes. For example, certain portions of the thinned regions 108a, 108b may be selectively masked off to accept one or more types of dopant material.

Generally, a gate structure 160 and source and drain regions 164, 166 are formed to implement some different transistor (FIG. 15). Thereafter, silicide, metallization, and / or other back-end processing (not shown) may be performed. To form the gate structure 160, a thin gate oxide 170 is formed over the upper surface of the silicon region. The gate oxide 170 may be formed by any suitable material formation process, such as, for example, thermal oxidation processing. By way of example, for example, the oxide layer 70 may be formed to a thickness between about 20 angstroms and 500 angstroms at a temperature between about 800 degrees centigrade and about 1000 degrees centigrade in the presence of O ₂ . This layer 170 of oxide material can serve, for example, as a gate oxide in a high voltage CMOS transistor device. Alternatively, a layer 170 of oxide material having a thickness of about 70 angstroms or less can be formed to serve as a gate oxide in, for example, a low voltage CMOS transistor device.

  A gate layer 172 (eg, polysilicon or other conductive material) is then deposited over the layer 170 of gate oxide material. The polysilicon layer 172 may be formed to a thickness of, for example, about 1000 angstroms to about 5000 angstroms, and may be a p-type dopant (boron) or an n-type dopant depending on the type of transistor to be formed (type (s)). A dopant such as (eg, phosphorus) may be included. The dopant may be present in the form originally provided in the polysilicon 172, or may subsequently be provided there (eg, via a doping process). Gate oxide layer 170 and gate polysilicon layer 172 may then be patterned to form gate structure 160. This gate structure comprises a gate dielectric and a gate electrode and is disposed over the channel region 174 in the silicon region 108.

Once the patterned gate structure is formed, LDD, MDD, or other extension implants (not shown) can be performed according to one or more types of transistors to be formed, Left and right sidewall spacers 178a, 178b may be formed along the left and right lateral sidewalls of the patterned gate structure 160. Implantation to form source (S) region 164 and drain (D) region 166 is then performed. Here, any suitable mask and implantation process can be used to form the source and drain regions 164, 166, thereby achieving the desired transistor types. For example, one or more openings through which p-type source / drain implants (eg, boron (B and / or BF ₂ )) are performed to provide p for PMOS transistor elements. A PMOS source / drain mask can be used to define the openings that form the mold source and drain regions. Similarly, one or more openings through which n-type source / drain implants (eg, phosphorous (P) and / or arsenic (As)) are performed to form the NMOS transistor element. An NMOS source / drain mask may be employed to define the openings that form the n-type source and drain regions for. Depending on the type of masking technique employed, if desired, such implantation may also selectively dope the polysilicon 172 of the gate structure 160 of certain transistors. Thus, it will be appreciated that channel region 174 is defined between source and drain regions 164, 166 in different transistors. It will also be appreciated that the channel region 174 may be doped prior to forming the gate oxide 170 to adjust Vt's if necessary.

  Thus, by forming a transistor according to one or more features of the present invention, a fully depleted silicon on insulator (FD-SOI) and a partially depleted silicon on insulator. Insulator (PD-SOI) transistor elements can be manufactured within a single integrated circuit manufacturing process. By forming different types of transistors on the same semiconductor structure, their respective advantages can be integrated to satisfy different circuit application requirements. For example, FD-SOI transistors can be used when higher speed and lower threshold voltage (Vt's) are important. Similarly, if lower off-current is important, if high voltage I / O transistors are desired, if transistors for dynamic Vsub modulations are needed, and / or different If multiple transistors with Vt's are needed, PD-SOI transistors can be used. Similarly, bipolar transistors can also be fabricated with one or more features of the present invention.

  Various other additions, deletions, substitutions, and other modifications have been described in the examples without departing from the scope of the claimed invention, without departing from the scope of the claimed invention. It will be understood that steps or structures can be made.

  In relation to the above description, the following items are disclosed.

(Invention 1)
A method of forming a fully depleted silicon-on-insulator (FD-SOI) transistor and a partially-depleted silicon-on-insulator (PD-SOI) transistor in an integrated circuit manufacturing process. And
A silicon-on-insulator (SOI) comprising a semiconductor substrate, a layer of insulating material formed over the semiconductor substrate, and a layer of silicon material formed over the layer of insulating material Prepare the board,
A layer of silicon material is suitable for forming a partially depleted transistor by growing a first grown layer of oxide material over the layer of silicon material. A thinning step to grow a first growth layer of oxide material by consuming silicon as part of the growth process. Is to thin the layer of (thins),
Forming a layer of nitride material over the first growth layer of oxide material;
Patterning a layer of nitride material, wherein the first growth layer of the oxide material and the layer of silicon material establish therein trenches Is intended for
Deopsiting a layer of dielectric material that fills the groove;
Planarizing the deposited layer of dielectric material;
Masking off an area of the SOI substrate in which a partially depleted transistor is to be formed;
Removing a layer of nitride material in a region where a fully depleted transistor is to be formed;
Removing the first growth layer of the oxide material in a region where a fully depleted transistor is to be formed;
Unmasking the region of the SOI substrate in which the partially depleted transistor is to be formed;
In a region where a fully depleted transistor is to be formed, a layer of silicon material is grown fully over the layer of silicon material over a second growth layer of oxide material. Thinning to a thickness suitable for forming a structured transistor, wherein growing a second growth layer of oxide material consumes silicon as part of the growth process Makes the layer of silicon material thinner,
Removing a layer of nitride material in a region where a partially depleted transistor is to be formed;
In the region where the partially depleted transistor is to be formed, the first growth layer of oxide material is removed, and in the region where the fully depleted transistor is to be formed, the second layer of oxide material is formed. Removing the growth layer of, and
In a region where a partially depleted transistor is to be formed, a partially depleted transistor is formed, and in a region where a fully depleted transistor is formed, a fully depleted transistor is formed. Forming step,
Including methods.

(Invention 2)
The layer of silicon material in the region where the fully depleted transistor is to be formed is thinned through etching rather than by growing a second growth layer of oxide material; The method according to invention 1.

(Invention 3)
The method of claim 1, wherein the layer of silicon material is formed to a thickness between about 800 angstroms and about 1200 angstroms, and the layer of nitride material is formed to a thickness of about 700 angstroms to about 800 angstroms. .

(Invention 4)
A first growth layer of oxide material thins the layer of silicon material to a thickness between about 800 angstroms and about 1000 angstroms;
A second growth layer of oxide material thins the layer of silicon material to a thickness between about 50 angstroms and about 200 angstroms;
The method according to any one of Inventions 1, 2, or 3.

(Invention 5)
Forming a fully depleted transistor comprises:
Forming a fully depleted gate structure over the thinned silicon in the region where the fully depleted transistor is to be formed;
Forming a source region in the thinned silicon adjacent to one side of the fully depleted gate structure; and
Forming a drain region in the thinned silicon adjacent to the other side of the fully depleted gate structure;
Including
And
Forming a partially depleted transistor comprises:
Forming a partially depleted gate structure over the thinned silicon in the region where the partially depleted transistor is to be formed;
Forming a source region in the thinned silicon adjacent to one side of the partially depleted gate structure; and
Forming a drain region in the thinned silicon adjacent to the other side of the partially depleted gate structure;
including,
The method according to invention 1.

(Invention 6)
A fully depleted gate structure includes a gate dielectric and a gate electrode;
A partially depleted gate structure includes a gate dielectric and a gate electrode;
The method according to invention 5.

(Invention 7)
Fully depleted and partially depleted transistors are formed as part of the integrated circuit manufacturing process,
A fully depleted transistor is thinner than a silicon-on-insulator (SOI) region of the semiconductor substrate where the partially-depleted transistor is formed. (SOI) region,
An integrated circuit comprising a fully depleted transistor and a partially depleted transistor formed on a single semiconductor substrate.

(Invention 8)
A partially depleted transistor is formed in a silicon layer thinned to a thickness between about 800 angstroms and about 1000 angstroms;
A fully depleted transistor is formed in a silicon layer that is further thinned to a thickness between about 50 angstroms and about 200 angstroms.
The circuit according to the invention 7.

(Invention 9)
Fully depleted silicon-on-insulator (FD-SOI) transistor (150) and partially-depleted silicon-on-insulator (FD-SOI) transistor (152) in a single integration As part of the circuit manufacturing process flow, a method for forming on a semiconductor substrate (104) is disclosed. A semiconductor device structure manufactured by the method is also disclosed.

In accordance with one or more features of the present invention, a fully depleted silicon-on-insulator (FD-SOI) and a partially-depleted silicon-on-insulator (FD-SOI) transistor device FIG. 3 is a flow diagram illustrating an example of a method for forming an in-circuit manufacturing process. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element. An exemplary fully depleted silicon-on-insulator (FD-SOI) in an integrated circuit manufacturing process, such as the exemplary method of FIG. 1, according to one or more features of the present invention, and FIG. 6 is a partial cross-sectional view illustrating the formation of a partially depleted silicon-on-insulator (FD-SOI) transistor element.

Explanation of symbols

102 Starting material 104 Semiconductor substrate 106 Non-conductive insulating material layer 108 Silicon thin layer 108a Silicon 108b Silicon 108c Silicon 108d Silicon 112 First growth layer 114 of oxide-based material 114 Nitride-based material layer 118 Groove 120 "Active" areas or regions
120a Active region 120b Active region 120c Active region 120d Active region 122 Layer of dielectric material 126 Layer of masking material 130 Second growth layer 150 of oxide material Silicon-on-insulator (FD-SOI) transistor 160 Gate structure 164 Source region 166 Drain region 170 Gate oxide 172 Gate layer 178a Left sidewall spacer 178b Right sidewall spacer

Claims (1)

A method of forming a fully depleted silicon-on-insulator (FD-SOI) transistor and a partially-depleted silicon-on-insulator (PD-SOI) transistor in an integrated circuit manufacturing process. And
A silicon-on-insulator (SOI) comprising a semiconductor substrate, a layer of insulating material formed over the semiconductor substrate, and a layer of silicon material formed over the layer of insulating material Prepare the board,
A layer of silicon material is suitable for forming a partially depleted transistor by growing a first grown layer of oxide material over the layer of silicon material. A thinning step to grow a first growth layer of oxide material by consuming silicon as part of the growth process. Is to thin the layer of (thins),
Forming a layer of nitride material over the first growth layer of oxide material;
Patterning a layer of nitride material, wherein the first growth layer of the oxide material and the layer of silicon material establish therein trenches Is intended for
Deopsiting a layer of dielectric material that fills the groove;
Planarizing the deposited layer of dielectric material;
Masking off an area of the SOI substrate in which a partially depleted transistor is to be formed;
Removing a layer of nitride material in a region where a fully depleted transistor is to be formed;
Removing the first growth layer of the oxide material in a region where a fully depleted transistor is to be formed;
Unmasking the region of the SOI substrate in which the partially depleted transistor is to be formed;
In a region where a fully depleted transistor is to be formed, a layer of silicon material is grown fully over the layer of silicon material over a second growth layer of oxide material. Thinning to a thickness suitable for forming a structured transistor, wherein growing a second growth layer of oxide material consumes silicon as part of the growth process Makes the layer of silicon material thinner,
Removing a layer of nitride material in a region where a partially depleted transistor is to be formed;
In the region where the partially depleted transistor is to be formed, the first growth layer of oxide material is removed, and in the region where the fully depleted transistor is to be formed, the second layer of oxide material is formed. Removing the growth layer of, and
In a region where a partially depleted transistor is to be formed, a partially depleted transistor is formed, and in a region where a fully depleted transistor is formed, a fully depleted transistor is formed. Forming step,
Including methods.

Images