KR20060041198A - Silver alloy material, circuit substrate, electronic device and method of manufacturing circuit substrate - Google Patents

Abstract

The circuit board of the present invention includes a silver alloy material containing at least one element selected from tin, zinc, lead, bismuth, indium, and gallium as a constituent material of the gate wiring and the gate electrode, and containing silver as a main component. I use it. In particular, it is preferable to use silver as a main component and the silver alloy material containing indium for gate wiring and a gate electrode. Thereby, by adjusting content of indium, the silver alloy material which can adjust suitably resistance value, adhesive force, plasma resistance, a reflection characteristic, etc. can be provided. In addition, it is possible to apply these alloys to the characteristics required for each part of the circuit board.

Circuit board, constituent material, silver alloy material, content, resistance value, adhesion, plasma resistance, reflection characteristic

Description

SILVER ALLOY MATERIAL, CIRCUIT SUBSTRATE, ELECTRONIC DEVICE AND METHOD OF MANUFACTURING CIRCUIT SUBSTRATE}

1 is a plan view of a circuit board according to an embodiment of the present invention.

2 is a cross-sectional view taken along the line A-A of the circuit board of FIG.

(A) is a top view which shows the terminal part vicinity of the circuit board shown in FIG. 1, (b) is sectional drawing of the arrow B-B of FIG. 3 (a).

4 is a plan view of a TFT array substrate, showing an example of the circuit board shown in FIG.

5 is a schematic configuration diagram of a manufacturing apparatus for producing a circuit board of the present invention.

6 is a process chart showing a manufacturing process of the circuit board of the present invention.

FIG. 7A is a plan view showing a pixel portion at the completion of the gate wiring pretreatment step, FIG. 7B is a plan view showing a pixel portion at the completion of the gate wiring formation process, and FIG. CC line arrow sectional drawing of 7 (b).

(A) is a top view which shows the terminal part at the completion of a gate wiring preprocessing process, FIG. 8 (b) is a top view which shows the terminal part at the completion of a gate wiring formation process, and FIG. 8 (c) is a figure DD line arrow sectional drawing of 8 (b).

9A to 9D are diagrams illustrating a step of forming a hydrophilic liquid region in a gate wiring pretreatment step.

10A is a plan view showing a pixel portion at the completion of the gate insulating film / semiconductor film forming step, and FIG. 10B is a cross-sectional view taken along the line E-E in FIG. 10A.

(A) is a top view which shows the terminal part at the completion of a gate insulating film / semiconductor film forming process, FIG. 11 (b) is sectional drawing of the F-F line arrow of FIG.

FIG. 12A is a plan view showing a pixel portion at the completion of the gate insulating film / semiconductor film processing step, and FIG. 12B is a cross-sectional view taken along the line G-G in FIG. 12A.

FIG. 13A is a plan view showing the terminal portion at the completion of the gate insulating film / semiconductor film processing step, and FIG. 13B is a cross-sectional view taken along the line H-H in FIG. 13A.

FIG. 14A is a plan view of a pixel portion at the completion of the source / drain wiring pretreatment process, FIG. 14B is a plan view of a pixel portion at the completion of the source / drain wiring formation process, and FIG. Sectional arrow line II of 14 (b).

Fig. 15 is a sectional view of the arrow showing the pixel portion at the completion of the channel portion processing step and corresponding to the position of the line I-I in Fig. 14B.

(A) is a top view which shows the pixel part at the time of completion of a protective film / interlayer insulation layer film forming process, FIG. 16 (b) is sectional drawing of the arrow J-J of FIG. 16 (a).

FIG. 17A is a plan view showing the terminal portion when the protective film and interlayer insulating layer film forming step is completed, and FIG. 17B is a cross-sectional view taken along the line K-K in FIG. 17A.

(A) is a figure which shows the pixel part and terminal part at the time of completion of a protective film process process, and the arrow display cross section in the position on the JJ line | wire of (a) of FIG. 16, (b) of FIG. Is a view showing a pixel portion and a terminal portion at the completion of the protective film processing step, and an arrow-shaped sectional view corresponding to the position of the KK line in FIG.

Fig. 19A is a plan view showing a terminal portion of a circuit board of still another embodiment of the present invention, and Fig. 19B is a cross-sectional view taken along the line L-L in Fig. 19A.

20 is a graph of the visible light reflectance of the silver film of Comparative Example 1 shown in Table 1. FIG.

21 is a graph of the visible light reflectance of the aluminum film of Comparative Example 3 shown in Table 1. FIG.

Fig. 22 is a graph of the visible light reflectance of the silver alloy film (indium 0.05 wt%) of Example 7 shown in Table 1;

23 is a graph of the visible light reflectance of the silver alloy film (0.2 wt% indium) of Example 8 shown in Table 1. FIG.

24 is a graph of visible light reflectance of the silver alloy film (0.5 wt% indium) of Example 3 shown in Table 1. FIG.

25 is a graph of the visible light reflectance of the silver alloy film (1.6 wt% indium) of Example 4 shown in Table 1. FIG.

(A) is a top view which shows the pixel part at the completion of a gate wiring formation process, FIG. 26 (b) is sectional drawing of the arrow of the M-M line of FIG. 26 (a).

(A) is a top view which shows the terminal part at the completion of a gate wiring formation process, FIG. 27 (b) is sectional drawing of the arrow line N-N of FIG. 27 (a).

28 is a plan view of a circuit board according to another embodiment of the present invention.

FIG. 29 is a cross-sectional view taken along the line O-O of the circuit board of FIG. 28;

(A) is a top view which shows the vicinity of the terminal part of the circuit board shown in FIG. 28, and FIG. 30 (b) is sectional drawing of the P-P line arrow of FIG.

(A) is a top view which shows the other example which shows the terminal part vicinity of the circuit board shown in FIG. 1, and FIG. 31 (b) is sectional drawing of the Q-Q line arrow of FIG.

32 (a) to 32 (e) are diagrams showing a step of forming a wiring portion and a terminal portion of the circuit board of the present invention.

FIG. 33A is a diagram showing a state in which the wiring portion is formed using the material M, and FIG. 33B is a diagram showing a state in which the terminal portion is formed using the material N;

34 (a) to 34 (c) are diagrams showing the state of the boundary portion where the materials M and N contact.

Fig. 35 is a schematic diagram of the gate wiring in the circuit board of the present invention.

36A is a diagram showing a conventional wiring pattern, and FIG. 36B is a diagram showing the wiring pattern of the present invention.

37A and 37B are diagrams illustrating another example of wiring formation in the circuit board of the present invention.

38A and 38B show still another example of wiring formation in the circuit board of the present invention.

39 (a) and 39 (b) show still another example of wiring formation in the circuit board of the present invention.

40 (a) to 40 (c) are diagrams illustrating still another example of wiring formation in the circuit board of the present invention.

(A) is a top view which shows the pixel part at the completion of a gate wiring formation process, FIG. 41 (b) is sectional drawing of the arrow R-R of FIG. 41 (a).

(A) is a top view which shows the terminal part at the completion of a gate wiring formation process, FIG. 42 (b) is sectional drawing of the S-S line arrow of FIG. 42 (a).

<Explanation of symbols for the main parts of the drawings>

11: TFT array substrate

12: glass substrate

13: gate wiring

14: source wiring

15: TFT

16: auxiliary capacitance wiring

17: gate electrode

18: gate insulating layer

19: amorphous silicon layer

20: n ⁺ type silicon layer

21: source electrode

22: drain electrode wiring

23: contact hole

24: pixel electrode

25: protective layer

26: interlayer insulation layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silver alloy material, and in particular, a silver alloy material constituting a wiring and / or an electrode on a circuit board using an insulating substrate, a material thereof, or a material other than the flowable silver alloy. The formed circuit board, the manufacturing method of a circuit board, and electronic devices, such as a display apparatus, a liquid crystal display device, and an image input device using a circuit board, are mentioned.

A liquid crystal display device, which is one of electronic devices, includes a TFT array substrate having many TFTs (thin film transistors), wirings, and the like as a circuit board.

Conventionally, a TFT array substrate is manufactured by a series of processes described in Non-Patent Document 1 (flat panel display 1999 (page 129 of Nikon Micro Devices, Nikon BP Co.)). Photolithography was needed.

In such a conventional method of manufacturing a TFT array substrate using photolithography, many vacuum apparatuses, such as film forming apparatuses used in each film forming step, and processing apparatuses such as a dry etching apparatus, are used, and thus, further enlargement is desired in recent years. In order to manufacture the TFT array board | substrate currently, enormous installation cost is needed.

In order to solve such a subject, the technique which forms wiring etc. by the inkjet system is proposed. In this technique, for example, as disclosed in Patent Document 1 (Japanese Patent Application Laid-Open No. Hei 11-204529 (published on July 30, 1999)), a wiring forming material is formed on a substrate to form wiring. The affinity region and the non-affinity region are formed to form a wiring by dropping droplets of the wiring material on the affinity region by an ink jet method.

In addition, Patent Document 2 (Japanese Laid-Open Patent Publication: Japanese Patent Laid-Open No. 2000-353594 (published on December 19, 2000)) similarly uses a inkjet method to form a wiring material from a wiring forming region in a wiring forming technique. It is disclosed to form banks on both sides of the wiring formation region, to make the upper portion of the bank non-philic, and to make the wiring formation region lyophilic in order to suppress the extraction.

As a material for forming a wiring by the ink jet method as described above, as disclosed in Non-Patent Document 2 (pages 67 to 78 of Japanese Patent No. 2, June 17, 2002, Nikkei BP Co., Ltd.), A fluid metal-containing material (ink) obtained by dispersing silver or gold nanoparticles in a solvent is used. After these are dripped at the predetermined | prescribed place on a board | substrate, the metal contained in the process appears, such as baking, and turns into wiring, etc. Thus, as a metal which can be processed as a fluid metal containing material, palladium, platinum, etc. are mentioned besides silver and gold. However, considering the price of raw materials, only silver is realistic.

For this reason, it is considered to use silver which can be used in the inkjet system as a material for forming a wiring on a TFT array substrate and as a wiring material for producing another circuit board.

Moreover, although aluminum is frequently used as a wiring material and a light reflection film material on a circuit board like the conventional TFT array substrate, silver has superior properties to aluminum in that it has low electrical resistivity and high reflectance in the visible light region. Known.

Thus, although silver is a material attracting attention as a wiring material on a circuit board, the use range is limited by the property. For example, when silver is formed on a glass substrate by a vapor deposition method, a sputtering method, or the like, there is a significant lack of heat resistance, such as grain growth and surface turbidity, even when firing at about 250 ° C. In addition, the adhesion to the glass substrate is also weak.

In particular, in the manufacture of TFT array substrates, dry etching is often used for etching of insulating films and the like. Resistance to this environment (plasma resistance) is remarkably low in the case of silver. Therefore, silver is a material which is hard to use as it is as a material which comprises the wiring on a TFT array substrate.

Moreover, as a conventional silver, there existed a problem that heat resistance was low and reflectance fell significantly also by baking at 200 degreeC, for example. Therefore, conventional silver was not available when heat resistance was needed during the manufacturing process. For example, in a reflective liquid crystal display device, it was difficult to use it as a material of the light reflection film provided on a TFT array substrate.

Moreover, the said nonpatent literature 2 discloses using the fluid wiring material which disperse | distributed the nanoparticles of silver and gold in a solvent as a material for forming wiring by the inkjet system mentioned above. After these are dripped at the predetermined | prescribed place on a board | substrate, the metal contained in the process appears, such as baking, and turns into wiring, etc. Thus, as a metal which can be processed as a fluid wiring material, palladium, platinum, etc. are mentioned other than silver and gold.

By the way, considering the price of raw materials, only silver is realistic among them. Regarding the formation of wiring using silver, Patent Document 3 (Japanese Laid-Open Patent Publication: Japanese Patent Laid-Open No. 2003-80694 (published on March 19, 2003)) discloses a method for forming wiring without using a bank.

For this reason, using silver which can be used by the inkjet system is also considered as a material which comprises the wiring on a TFT array substrate.

By the way, when forming a thin film laminated board | substrate, for example, when it is a TFT array board | substrate used for a liquid crystal passive, as performance required for wiring, a resistance should be low, smooth surface property, process gas, such as an etching, or using this Resistance in the plasma, adhesion to the base material, electrical contact with the dissimilar material, that is, low contact resistance or unnecessary diffusion does not occur, corrosion resistance, and the like are required.

However, it is difficult to cover all of these performances with one type of material. In sputtering, vapor deposition, and CVD film formation, a single film or an alloy material having a performance suitable for a purpose is laminated and deposited through a photolithography process and an etching process. I'm patterning.

Moreover, in the wiring formation method using the inkjet system which simplifies a wiring formation process, the silver material as a material used for inkjet is used as the particulate colloidal material which disperse | distributed microparticles | fine-particles in the dispersion medium, The wiring material on a circuit board Although it is a material attracting attention as a material, the use range was limited by the property.

For example, when silver is deposited on a glass substrate by a vapor deposition method, a sputtering method, or the like, grain growth becomes remarkable from firing at about 250 ° C., so that a smooth surface is roughened and surface turbidity occurs depending on the temperature. Has a problem that remarkably lacks heat resistance.

In addition, in order to use silver as a thin film, it is essential to have adhesion to glass. Particularly, silver, which is a coating material, cannot be expected to have an injection effect on a substrate during the film formation process. It becomes weak and has a problem in workability and stability. Moreover, when the adhesion force is improved by baking, the problem that surface smoothness deteriorates by the grain growth characteristic of silver as mentioned above arises.

In addition, there is a problem even when the wiring on the TFT array substrate is configured. For example, in the manufacture of a TFT array substrate, dry etching is often used for etching of an insulating film or the like. When exposed to the plasma in the atmosphere of this dry etching gas, film degradation and peeling occur by oxidation or the like. For this reason, there is a problem in using silver as it is as a wiring material.

Therefore, in the case where silver is used as the wiring material, in order to solve the various problems as described above, a treatment for improving the adhesion on the insulating substrate is performed, or the surface smoothness due to heat or the film degradation due to etching gas, In order to prevent peeling, it is necessary to form the thin film which becomes a protective film on silver wiring. That is, the problem that a thin film is multilayered on an insulating substrate arises, and as a result, the number of manufacturing processes of a circuit board increases, and the problem also arises that cost increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a silver alloy material capable of realizing a material having heat resistance, strong adhesion to a glass substrate, high plasma resistance, and good light reflectivity, and preventing multilayering of thin films. An object of the present invention is to provide a circuit board, a method for manufacturing the same, and an electronic device capable of suppressing an increase in the number of manufacturing steps of the circuit board and an increase in cost.

In order to achieve the above object, the inventors of the present application have made a thorough investigation and, in the case where a wiring or an electrode is formed on an insulating substrate using silver as a main component and fine particles of an alloy containing indium as a material, Compared to the case where the wiring or the electrode is formed on the insulating substrate using the fine particles of the material as the material, the adhesive force of the wiring and the electrode to the insulating substrate is improved, and the heat resistance and the plasma resistance of the wiring and the electrode are found to be improved. . In addition, it was found that similar effects can be obtained even in the case of an alloy in which tin, zinc, lead, bismuth, and gallium are added to silver as well as the above indium.

Moreover, when an appropriate amount of indium was added to silver and formed into a film, it discovered that the silver alloy film which maintains high visible light reflectance is obtained also by baking at 200 degreeC or 300 degreeC. Since such a silver alloy film has a high reflectance as a whole compared with the case where the conventional light reflection film of aluminum is used, it discovered that brighter display is possible, for example when used for the light reflective electrode etc. of a reflective liquid crystal display device.

That is, the silver alloy material of this invention is a material which comprises the wiring and / or electrode formed on an insulated substrate, Comprising silver as a main component, The at least 1 type element chosen from tin, zinc, lead, bismuth, indium, and gallium. Characterized in that it comprises a.

According to the material of the said structure, the wiring and / or the electrode which are low electrical resistance, and have high process resistance, such as heat resistance, adhesion to a glass substrate, and plasma resistance, can be formed.

In addition, the inventors of the present application and the like have found that, by adjusting the necessary characteristics for each part of the wiring on the same wiring, it is possible to reduce the number of manufacturing steps of the circuit board and to reduce the cost.

That is, the circuit board of this invention is a circuit board with wiring formed on the board | substrate WHEREIN: The characteristic of the at least 2 site | part on the same wiring is respectively different, It is characterized by the above-mentioned.

Here, the same wiring is a shape continuous wiring. In the circuit on a board | substrate, a circuit board | substrate is formed by gathering a plurality of such wirings, and it means one unit of these some wirings.

In order to make the characteristic of one site | part on the same wiring different from the characteristic of another site | part, it can implement | achieve by making the composition ratio of the material of each site | part different, respectively. Moreover, it can also implement | achieve by making each the structure material of each site | part different.

Other objects, features, and advantages of the present invention will be fully understood from the description below. Further advantages of the present invention will become apparent from the following description with reference to the accompanying drawings.

Embodiment 1

EMBODIMENT OF THE INVENTION Embodiment of this invention is described as follows.

In this embodiment, first, the silver alloy material of the present invention will be described. Next, a TFT array substrate and a liquid crystal display device using the silver alloy material will be described.

The silver alloy material of this invention is a material which comprises the wiring and / or electrode formed on insulating board | substrates, such as a glass substrate, Comprising silver mainly, At least, it selects from tin, zinc, lead, bismuth, indium, gallium. It is characterized by including one or more types of elements.

When the silver alloy material of the said structure is used, the wiring and / or the electrode which are low electrical resistance, and have high process resistance, such as heat resistance, the adhesive force with respect to a glass substrate, and plasma resistance, can be formed.

Below, the above-mentioned advantage of the silver alloy material of this invention is demonstrated, referring Examples 1-9 and Comparative Examples 1 and 2. FIG.

The silver alloy material of this invention was created in the following procedures, and it formed into a film on an insulating substrate, and evaluated process tolerance.

Preparation of the silver alloy material of this invention and film-forming of this silver alloy material to the insulating substrate were performed by the vapor deposition method by the electron beam vapor deposition machine (Japan Vacuum Technology Co., Ltd., high vacuum vapor deposition apparatus EBX-10D).

First, as an evaporation source, silver, tin, zinc, lead, bismuth, indium, gallium, or the like or granular raw materials with a purity of 99.9% or more were mixed at a predetermined weight ratio.

Subsequently, the mixed raw materials were placed in a molybdenum crucible, melted and alloyed in a vacuum better than 1 × 10 ⁻⁵ Torr.

Finally, after confirming that it melt | dissolved completely, it formed into a film on the alkali free glass substrate. In addition, the glass substrate temperature at the time of film-forming was set to 100 degreeC. In addition, the film thickness of the alloy film formed into a film on the glass substrate was made so that it might become all about thickness of 0.2 micrometer.

In this embodiment, although such a method was used for preparation and film formation of an alloy, it is not necessarily limited to this. The sputtering method using a solid solution, a sintered compact, and another target may be sufficient, and the method of apply | coating a fluid liquid material containing a metal element in a suitable density | concentration, or another method may be sufficient.

The silver alloy film created in this way confirmed the composition with the ogre electron spectrometer (Parking Elma, SAM670). Although there was no composition distribution in the film thickness direction and it was uniform, the composition ratio of the whole silver alloy film which was created shifted somewhat from the mixing ratio of a raw material. However, the deviation is a degree which does not affect the object, the means, the effect, etc. of the present invention at all. The silver alloy film thus produced is a typical example of the present invention.

About the alloy film which consists of silver and indium, in order to know a more accurate composition, quantitative analysis was performed by ICP emission spectrometry. The method is as follows.

First, what peeled the silver alloy film formed into a film on the alkali free glass substrate with the metal spoon as a sample was used. Before peeling, the thickness of the silver alloy film on a glass substrate was about 0.2 micrometer, and the quantity of the obtained sample was about 10 mg with respect to each Example. Subsequently, what dissolved this sample in 50 mL of 3N-nitric acid was used as the measurement liquid of ICP emission spectrometry. As a measuring apparatus, SPS-1700HVR manufactured by SIA Nanotechnology Co., Ltd. was used, and argon was used as the plasma gas.

In this embodiment, as the process resistance of a silver alloy film, adhesive force, heat resistance, electrical resistivity, and plasma resistance were evaluated. These items are the most basic items for wiring on a circuit board or the like. Each item is explained in full detail below.

The adhesive force was directly formed into a film on an alkali free glass substrate, and was investigated.

When using it for a circuit board like the present invention, the adhesion to the glass substrate is a useful index.

Here, the test of the adhesive force was performed after the baking process of 200 degreeC and 1 hour in nitrogen atmosphere. After baking, the adhesive tape was stuck to the film surface which cut | disconnected, and the method of peeling an adhesive tape so that a film surface was removed was used. Judgment was made favorable only when defects and peeling were not seen at all when peeling was seen on the membrane surface even in part.

Evaluation of heat resistance was performed by observing the film surface after baking at 300 degreeC and 1 hour in nitrogen atmosphere with the electron microscope (Hitachi Corporation, S-4100). Judgment was good when the unevenness | corrugation did not generate | occur | produce on a film surface at all, and made the case where the protrusion of the height of a film thickness or less generate | occur | produced a part of the film surface slightly, and made it the other than that bad.

Evaluation of the electrical resistivity was performed with respect to the board | substrate after baking at 200 degreeC and 1 hour in nitrogen atmosphere. The electrical resistivity was calculated | required from the sheet resistance value calculated | required by the 4-needle method by the measuring instrument (Mitsubishi Chemical Corporation, Lorestar-GP), and the film thickness measured separately.

Evaluation of plasma resistance was performed using the dry etching apparatus (RIE, reactive ion etching system). Specifically, after the substrate was transported in the process chamber, discharge was performed while introducing various etching gases.

Criteria for evaluation were as chlorine (Cl ₂₎ gas, carbon tetrafluoride (CF ₄₎ gas and oxygen (O ₂₎ 3 Conditions for introducing a mixture gas of oxygen (O ₂₎ gas in the gas.

Hereinafter, the third condition for each condition Cl _2, CF ₄ + O ₂ refers to the condition, O ₂ conditions. Discharge time was 180 second, 60 second, and 60 second, respectively. In addition, this discharge time is intentionally set on strict conditions, being aware of the five-sheet mask process described later.

In order to determine the plasma resistance, the sheet resistance value of the film was examined. Surface resistance value was measured similarly to the case of electrical resistivity. As a criterion of determination, when the surface resistance value was within 2.5 times, 2.5 times, and within 7 times with respect to the process before, it set as good and slightly good, respectively, and made other than that the defect.

These evaluation items are the examples set in order to show the property of the silver alloy material of this invention to the last. The individual conditions are set intentionally stricter than the assumed use conditions in order to clarify the difference. In carrying out the present invention, evaluation of these items is not necessarily required, and the details of observation means, judgment criteria, conditions, and the like are merely examples. The application range of this invention is not limited by these evaluation items and individual conditions.

About the silver alloy material of this invention, the example of an evaluation result is shown in Table 1, Table 2.

In each table | surface, the comparative example 1 is an example of the metal film which consists of silver single substance, and the comparative example 2 is an example of the silver alloy film which mixed 2 weight% aluminum to the evaporation source. Examples 1 to 9 are 10% by weight of tin, 10% by weight of zinc, 1% by weight of indium, 3% by weight of indium, 5% by weight of indium, and 10% by weight of silver in the evaporation source. As an example of the silver alloy film which mixed indium, 0.1 weight% indium, 0.3 weight% indium, and 20 weight% indium, it is an Example of this invention. In addition, although each raw material contains a very small amount of impurities, since the amount does not affect the result, the description of the impurities is omitted.

First, the ICP emission analysis value, the adhesion force, and the evaluation result of heat resistance are described in Table 1 below.

In the results of the quantitative analysis by the ICP emission spectrometry described above, for each of Examples 3 to 8, the content of indium with respect to silver was 0.5%, 1.6%, 3.4%, 9.3%, 0.05 % By weight and 0.2% by weight.

As shown in Table 1, in the film made of silver which is Comparative Example 1, both the adhesion and the heat resistance were poor. In the firing test at 250 ° C. for 1 hour, which is more relaxed than this, silver is remarkably lacking in heat resistance such as reliable surface turbidity. Here are some of the reasons why it has conventionally been difficult to use silver as wiring.

On the other hand, in the silver alloy film which added tin, zinc, and indium to silver as described in Example 1-Example 9 of this invention, the improvement of the adhesive force with respect to a glass substrate can be seen as a whole. Regarding the addition of indium, as in Example 3, when the content of indium to silver is approximately 0.5% by weight or more, a certain improvement in adhesion can be seen.

Also in heat resistance, the improvement of heat resistance can be seen in Examples 1-9 of this invention as a whole. In particular, in Examples 7 and 8, although the content of indium with respect to silver is very small, 0.05 wt% and 0.2 wt%, respectively, the heat resistance can be improved. For this reason, addition of indium can be said to be very effective for the improvement of heat resistance.

The reason why the adhesion strength is improved is that the elements such as tin, zinc and indium constituting the silver alloy of the present invention are extremely small and diffuse into the glass substrate, and the interface disappears, so that the adhesion energy becomes a large value close to the bulk aggregation energy. I think it is. This idea is supported by the fact that in the silver alloy film of this invention, the state which baked at 200 degreeC 1 hour and the adhesive force were larger than the state formed into a film at 100 degreeC of board | substrates. That is, this invention is based on the principle that adhesive force is obtained by the diffusion of tin, zinc, indium, etc. in a silver alloy film.

Moreover, the scope of the present invention is not limited to obtaining an adhesive force by the method of baking after film-forming like a present Example, but includes the case where the adhesive force is obtained by fully raising the board | substrate temperature at the time of film-forming.

On the other hand, the reason why the heat resistance is improved is that the film contains tin, zinc, and indium, so that a change occurs in the lattice constant of the crystal and the size of the crystal grain, and the movement of silver atoms in the film is suppressed, causing grain growth. It seems to be difficult.

Here, in the silver alloy material of the present embodiment, it is also important that the composition of the obtained film is set so as to enter a region in which the mixed element melts into a primary solid solution (solid solution) dissolved in silver crystals. If it is set to the area | region which makes such a primary solid solution, even if baking a film | membrane, it will be difficult to precipitate the intermediate solid solution and intermetallic compound which have a crystal structure different from silver crystal | crystallization, and a new grain will hardly grow on a film surface. Therefore, even if it bakes, surface property does not change, and as a result, heat resistance becomes high.

Although the composition range which makes such a primary solid solution depends also on environmental temperature, when it is tin, zinc, and indium, each content is less than 11-14 weight%, less than 25-39 weight%, and 27-28 weight% with respect to silver. It is less than a range.

Thus, from the evaluation result of Table 1, the silver alloy material of this invention improves heat resistance compared with silver, especially when it is an alloy with indium, and improves the adhesive force in the case of containing indium 0.5 weight% or more. Could see.

In addition, the silver alloy material of the present invention may be an alloy of gallium, which is equivalent to indium, tin, which is equivalent to lead, and bismuth having much similar properties to lead in the elemental periodic table, and similarly exhibit excellent adhesion and heat resistance.

Next, the evaluation result which investigated the electrical resistivity and plasma resistance is described in Table 2 below.

From the evaluation result of Table 2, it turned out that the electrical resistivity is equal to or less than the conventional aluminum alloy as a low electrical resistance of about 7 microohm-cm or less except Example 6 and Example 9. Thereby, it turns out that the silver alloy material of this invention is suitable as materials, such as wiring which is low electrical resistance. Moreover, if electrical resistivity is about 10 microohm-cm or less, it can be used practically as a material of the circuit board for large display devices.

Especially in Example 7, Example 8, and Example 3, although the content rate of indium with respect to silver is 0.5 weight% or less, each electric resistance is very low value of 2.2 micro ohm cm, 2.3 micro ohm cm, and 2.7 micro ohm cm. . In aluminum, since the electrical resistivity is 2.7 µΩcm even in the bulk state, the thickness is not 2.7 µΩcm or less in the thin film, and these are low electrical resistances which cannot be made of aluminum.

Therefore, in the silver alloy material of this invention, especially when the content rate of indium with respect to silver is 0.5 weight% or less, the formation of the low electrical resistance wiring which cannot be achieved with conventional aluminum wiring is possible. When especially low electrical resistance of wiring is desired, it is good to make a circuit board using the silver alloy material of this invention, for example in the liquid crystal display device used for liquid crystal TVs.

However, since the content of indium is low, the plasma resistance is not sufficient, and it is generally necessary to laminate another metal film or the like. As for the adhesion to the substrate, since the content of indium is low, it is not sufficient, so a basic treatment or the like may be required.

Plasma resistance is improved in Examples 1 to 6 and Example 9 of the present invention. In particular, about indium, when it contained about 0.5 weight% or more, the improvement of the plasma resistance was seen. Strictly speaking, however, there are alloy materials that become defective depending on the plasma conditions.

In the case of the silver group of Comparative Example 1, both of the silver and aluminum of Comparative Example 2 were poor, but in Example 1, slightly good under O ₂ condition, in Example 2, good under Cl ₂ condition, and slightly under O ₂ condition. It became good. Particularly useful as silver alloys are the cases of Examples 3 to 6, and Example 9, characterized in that they comprise indium. The Cl ₂ conditions, and all that is as good, the greater the effect of improving the plasma resistance. Although Example 5, which has a relatively high indium content, was found to be good under all plasma conditions, the electrical resistivity was low at 6.1 mu OMEGA cm. On the other hand, in Example 6 and Example 9, although the electrical resistivity is comparatively high in a table | surface, plasma resistance improved more than Example 5.

As described above, the plasma resistance is improved because the vapor pressure of the compounds such as tin, zinc, indium, etc. in the silver alloy, and chlorine, fluorine, oxygen, etc. supplied from the gas introduced into the chamber is lower than that of silver. It seems to be because they have fulfilled the role of protective layer in slowing down erosion.

On the other hand, like Example 7 and Example 8, in the case of containing indium at a ratio of 0.5% by weight or less with respect to silver, all plasma resistances were poor.

As described above, the silver alloy material of the present invention is a material having both low electrical resistance and plasma resistance, especially when indium is contained in a proportion of 0.5% by weight or more. Plasma is often required, and the present invention is a particularly useful material. However, the component and ratio of constituent elements, such as tin, zinc, and indium, of the silver alloy material of this invention do not necessarily satisfy all the characteristics in a table | surface, and may select so that a required resistance may be satisfy | filled in some cases.

Moreover, especially when the silver alloy material of this invention contains indium in the ratio of 0.5 weight% or less, an electrical resistivity is 2.7 microohm cm or less, and its electrical resistance is very low. Therefore, it can be used especially for the use of the circuit board for liquid crystal display devices used for liquid crystal TVs.

In addition, the silver alloy material of the present invention may be an alloy of gallium, which is equivalent to indium, tin, which is equivalent to lead, and bismuth having much similar properties to lead in the elemental periodic table, and similarly exhibit excellent properties.

In summary, it was found that the silver alloy material of the present invention is a very useful material having both adhesion, heat resistance, low electric resistance, and plasma resistance as process resistance.

In addition, these evaluation results are the results in the conditions set to show the property of the silver alloy material of this invention to the last. The individual conditions are intentionally set to stricter conditions than the assumed use conditions in order to clarify the difference between the materials. The application range of this invention is not limited by the result of Table 1, Table 2.

The silver alloy material of the present invention also includes aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, It may be characterized by including an element selected from neodymium. By adding these elements, heat resistance, plasma resistance, and adhesive force can be further improved, and an optimum alloy material can be obtained.

When using the silver alloy material of this invention as a constituent material, such as wiring of a TFT array board | substrate, a preferable material is the silver alloy material containing zinc mainly as silver. Thus, when zinc is added to silver, the effect of the improvement of heat resistance, adhesive force, and plasma resistance is acquired, and it becomes a material suitable for the manufacturing process of a TFT array substrate.

Moreover, the silver alloy material of this invention may contain the other element added intentionally in addition to silver and zinc. The present invention is based on the fact that adding zinc to silver is effective for improving heat resistance, adhesion, and plasma resistance. Therefore, even when it contains other elements other than these, the silver alloy material of the structure which can acquire the effect by zinc addition is contained in the scope of the present invention.

In addition, when using the silver alloy material of this invention as a constituent material, such as wiring of a TFT array board | substrate, the most preferable material is the silver alloy material containing indium mainly as a silver. As described above, in the case where indium is added to silver, when the ratio of indium to silver is 0.5% by weight or more, the effect of significantly improving plasma resistance is obtained, which is a material suitable for the manufacturing process of the TFT array substrate. do.

When using the silver alloy material of this invention as a constituent material, such as wiring of a TFT array board | substrate, the most preferable material as a low electrical resistance is a material especially containing indium in 0.5 weight% or less with respect to silver. At this time, the electrical resistivity is 2.7 μΩcm or less, and thus low electrical resistance wiring can be formed which cannot be achieved with conventional aluminum wiring. When especially low electrical resistance of wiring is desired, it is good to make a circuit board using the silver alloy material of this invention, for example in the liquid crystal display device used for liquid crystal TVs.

As another excellent characteristic of the silver alloy material of this invention, when it contains an indium suitably, it has a high visible light reflectance and maintains this even after baking at 200 degreeC or 300 degreeC. This will be described below.

As a sample for a measurement, the silver or silver alloy film equivalent to the comparative example, Example shown in Table 1, Table 2, and the aluminum film created by the same procedure as the comparative example 3 were used for the reference. These were all formed into an alkali free glass substrate, and the glass substrate temperature at the time of film forming was set to 100 degreeC, and the film thickness was set to about 0.2 micrometer thickness. For the measurement of the visible light reflectance, the measurement was performed over the entire visible light region of 380 nm to 780 nm using a spectrophotometer (Hitachi Instruments Service, U-4100).

The visible light reflectance of the silver alloy film of this invention is demonstrated in FIGS. 20-25. In these figures, the horizontal axis represents the wavelength of light irradiated onto the metal film sample, and the vertical axis represents the visible light reflectance as the reflectance of the light. In each figure, the reflectance after film-forming completion, 200 degreeC baking, and 300 degreeC baking is recorded, and the change of the reflectance by baking is also understood. Moreover, the processing conditions of these baking were made into the conditions which bake for 1 hour in nitrogen atmosphere using the clean oven.

In detail, first, in the case of Comparative Example 1 shown in Fig. 20, as described above, the heat resistance is remarkably poor. Despite the high reflectance at the completion of film formation at 100 ° C, the reflectance remarkably decreases after firing at 200 ° C and 300 ° C. For this reason, it was not able to endure the manufacturing process which involves the baking process of about 200 degreeC, and it was difficult to use it as a light reflection film use of the reflection type liquid crystal display device, for example.

Next, in Comparative Example 3 (aluminum) as shown in FIG. 21, the light reflectance hardly changes after completion of film formation, firing at 200 ° C., and firing at 300 ° C. Aluminum is a material often used conventionally as a light reflection film use of a reflective liquid crystal display device.

22 is an example of the silver alloy film containing 0.05% by weight of indium with respect to silver as an example of the silver alloy film of the present invention. In this case, the results are significantly different from those in the silver in Fig. 20, and the decrease in reflectance is significantly small even by the thermal firing at 200 ° C and 300 ° C. In comparison with the case of the aluminum film of Fig. 21, the reflectance is high in almost the wavelength region after firing at 200 占 폚, and the reflectance is high as a whole except for the extremely narrow region on the short wavelength side even after firing at 300 占 폚. Thereby, it turns out that the silver alloy film of a present Example has high visible light reflectance and is excellent as a light reflection film.

23 is an example of the silver alloy film of the present invention, which is an example of a silver alloy film containing 0.2 wt% of indium with respect to silver. In this case, the result is almost the same as in the seventh embodiment of FIG. The reduction in reflectance is small even by firing at 200 ° C. and 300 ° C., and the visible light reflectance is higher than that of the aluminum film as a whole, which is excellent as a light reflection film.

24 is a case where indium is contained in a ratio of 0.5% by weight with respect to silver. By firing at 200 ° C, the reflectance is superior to that of the aluminum film as a whole except for a part of the short wavelength side. However, after firing at 300 DEG C, the reflectance decreases particularly on the short wavelength side, which is not an advantage over the aluminum film. Thus, it is good to add indium suitably about silver, and when indium is extended too much, a reflectance will fall.

25 is a case where indium is contained in a ratio of 1.6% by weight with respect to silver. In this case, since the content of indium has increased, the reflectance decreases as a whole. Therefore, it cannot be said that it is superior to aluminum.

In summary, in the present invention, in the case of containing indium at a ratio of 0.5% by weight or less, the reflectance only slightly changes in the state of film formation even after firing at 200 ° C., and almost all over the visible light region even when compared with aluminum. High reflectance For this reason, it is suitable for a light reflection film use.

In addition, in the present invention, when indium is contained in a proportion of 0.2% by weight or less, the decrease in reflectance is also suppressed by firing at 300 ° C, and the reflectance is high almost over the entire visible light region even when compared with aluminum. For this reason, it is suitable for the light reflection film use especially when heat resistance is needed.

Moreover, the silver alloy material of this invention may contain the other element added intentionally in addition to silver and indium. The present invention is based on the fact that adding indium to silver is most effective for improving plasma resistance. Therefore, even when it contains other elements other than these, the silver alloy material of the structure which can acquire the effect by indium addition is contained in the scope of the present invention.

The scope of the present invention extends as an embodiment to a material containing silver, zinc and tin in the case of a material containing silver, zinc and indium, and in the case of a material containing silver, tin and indium.

The silver alloy material of this invention is used suitably as a material which comprises the wiring etc. on TFT array substrate. And this TFT array board | substrate is used suitably for the liquid crystal display device which is one of an electronic device.

The TFT array substrate and the liquid crystal display device according to the present embodiment will be described below with reference to FIGS. 1 to 4.

The liquid crystal display device according to the present embodiment has a pixel shown in FIG. 1. 1 is a top view which shows schematic structure of one pixel in the TFT array substrate 11 of a liquid crystal display device. In addition, sectional drawing of the arrow A-A in FIG. 1 is shown in FIG.

1 and 2, in the TFT array substrate 11, on the glass substrate (insulating substrate) 12, the gate wiring 13 and the source wiring 14 are provided in a matrix form. Near these intersections, a TFT 15 as a switching element is provided. In addition, the storage capacitor wiring 16 is provided between the adjacent gate wirings 13.

As shown in FIG. 2, on the glass substrate 12, a gate electrode 17 formed by branching from the gate wiring 13, and a storage capacitor wiring 16 are formed, and the gate insulating layer 18 is formed thereon. Is formed.

On the gate electrode 17, an amorphous silicon layer 19, an n ⁺ type silicon layer 20, a source electrode 21, and a drain electrode wiring 22 are formed via the gate insulating layer 18. TFT 15 is formed. Here, the source electrode 21 branches off from the source wiring 14.

The drain electrode wiring 22 extends from the TFT 15 to the contact hole 23, serves as a drain electrode of the TFT 15, and electrically connects the TFT 15 and the pixel electrode 24. And the contact hole 23 to form an electric capacitance between the storage capacitor wiring 16 and the storage capacitor wiring 16. In this upper layer, a protective layer 25 covering the TFT 15, an interlayer insulating layer 26 for planarization, and the like, and a pixel electrode 24 for applying a voltage to a liquid crystal or the like are formed.

Hereinafter, the area | region on the glass substrate 12 in which such a pixel is provided is called pixel formation area 61, and is shown in subsequent FIG.

Moreover, the liquid crystal display device which concerns on this embodiment has the terminal part 28 shown to Fig.3 (a). The terminal portion 28 is a connecting portion for electrically connecting an external circuit board, a driver IC for driving, and the like to the TFT array substrate 11. 3A is a plan view showing the schematic configuration of one terminal portion in the TFT array substrate 11 of the liquid crystal display device. 3B is a cross-sectional view taken along the line B-B in FIG. 3A.

As shown in FIG.3 (b), the terminal part 28 is comprised so that the terminal wiring 30, the gate insulating layer 18, and the terminal electrode 29 may be arrange | positioned from the glass substrate 12 side. The terminal electrode 29 is disposed for the purpose of improving electrical connection with an external circuit board and a driver IC for driving. The terminal wiring 30 is connected to the gate wiring 13, the source wiring 14, and the like in the pixel formation region 61.

Hereinafter, the area | region on the glass substrate 12 in which this terminal part 28 is provided is called terminal part formation area 62, and is shown in following FIG.

4 is a plan view of the TFT array substrate 11, wherein the pixel formation region 61 and the terminal portion formation region 62 are disposed as shown on the glass substrate 12. The pixel formation region 61 and the terminal portion formation region 62 are each provided with a plurality of pixels and terminal portions as shown in Figs.

In the present embodiment, a pattern forming apparatus for discharging or dropping the material of a layer to be formed, such as, for example, an ink jet method, is used to manufacture the TFT array substrate 11. As shown in FIG. 5, the pattern forming apparatus includes a mounting table 32 on which a substrate 31 (corresponding to the glass substrate 12) is mounted, an ink jet head 33, and an ink jet. The X direction drive part 34 which moves the head 33 to an X direction, and the Y direction drive part 35 which moves to a Y direction are provided. The ink jet head 33 discharges, for example, fluidic droplets containing a wiring material onto the substrate 31 on the mounting table 32.

Further, the pattern forming apparatus includes an ink supply system 36 for supplying ink to the ink jet head 33, discharge control of the ink jet head 33, an X-direction driver 34 and a Y-direction driver 35. The control unit 37 which performs various controls, such as drive control, is provided. The application position information is output from the control unit 37 to the X and Y direction drive parts 34 and 35, and the discharge information is output to the head driver (not shown) of the ink jet head 33. As a result, the ink jet head 33 operates in conjunction with the X and Y direction driving units 34 and 35 to supply the desired amount of liquid droplets to the target position on the substrate 31.

The ink jet head 33 may be a piezo system using a piezo actuator, a bubble system having a heater in the head, or another system. Control of the ink discharge amount from the ink jet head 33 is possible by control of the applied voltage. The droplet ejection means may be any method as long as the droplet ejection means is capable of supplying droplets, such as a method of simply dropping the droplets instead of the ink jet head 33. Alternatively, a method such as coating or dipping may be used to obtain a predetermined pattern by using a lyophilic region and a non-lyophilic region with respect to the wiring forming material previously formed on the substrate.

Next, the manufacturing method of the TFT array substrate 11 in the liquid crystal display device of this embodiment is demonstrated.

In this embodiment, as shown in FIG. 6, the TFT array substrate 11 includes a gate wiring preprocessing step 101, a gate wiring forming step 102, a gate insulating film and semiconductor film forming step 103, and a gate. Insulating film / semiconductor film processing step 104, source / drain wiring pretreatment step 105, source / drain wiring forming step 106, channel part processing step 107, protective film / interlayer insulating layer film forming step 108, protective film It consists of the process process 109 and the pixel electrode formation process 110.

(Gate Wiring Pretreatment Step 101)

In this gate wiring pretreatment step 101, pretreatment for forming the gate wiring 13, the gate electrode 17, the storage capacitor wiring 16, and the like is performed using the pattern forming apparatus described above. This will be described below with reference to FIGS. 7A and 8A. FIG.7 (a) and FIG.8 (a) are top views of the glass substrate 12 with which the TFT array substrate 11 is equipped.

In the gate wiring pretreatment step 101, the gate wiring forming region 41, the gate electrode forming region 42, the storage capacitor wiring forming region 43, and the terminal wiring forming region 44 shown in these figures are shown. A process for appropriately applying the fluidic wiring material is performed by ejection (dropping) of the fluidic wiring material in the pattern forming apparatus.

This processing is roughly as follows.

As a 1st thing, the board | substrate gives a property on a board | substrate (glass board | substrate 12) with respect to a fluid wiring material that it is easy to wet or is easy to repel. Hydrophilic regions (lyophilic regions) for forming the gate wiring forming region 41, the gate electrode forming region 42, the storage capacitor wiring forming region 43, and the terminal wiring forming region 44, and these as non-forming regions It is a hydrophilic water repellent treatment (hydrophilic liquid treatment) which patterns a water repellent region (liquid repellent region).

The second is a process of forming a guide for restricting liquid flow, that is, a guide along the gate wiring formation region 41 or the like.

In the former, the hydrophilic liquid treatment by the photocatalyst using titanium dioxide is typical. In the latter, guide formation is performed by photolithography using a resist material. Further, in order to grant Garachine liquid to the guide or the substrate surface, there is a case for carrying out a process of exposing them to a plasma atmosphere the introduction of CF _4, O ₂ gas. The resist used here is peeled off after wiring formation.

Here, the photocatalyst treatment using titanium dioxide was performed as follows. That is, what mixed ZONYL FSN (brand name: DuPont company) which is a fluorine-type nonionic surfactant with the isopropyl alcohol was apply | coated to the glass substrate 12 of the TFT array substrate 11. In addition, a mixture of titanium dioxide fine particle dispersion and ethanol was applied as a photocatalyst layer to a mask such as a gate wiring pattern by spin coating and fired at 150 ° C. And the glass substrate 12 was exposed by UV light using the said mask. As exposure conditions, it irradiated for 2 minutes with the intensity | strength of 70 kW / cm <2> using 365 nm ultraviolet light.

Here, formation of the hydrophilic liquid region by titanium dioxide is demonstrated below with reference to FIG.9 (a)-FIG.9 (d).

FIG. 9A shows a glass film 1 having a first film 2 in which ZONYL FSN (trade name, manufactured by DuPont), which is a fluorine-based nonionic surfactant, is mixed with isopropyl alcohol using spin coating or the like. The coated portion is shown.

FIG. 9B is a part where UV exposure is performed with a mask 4 such as a gate wiring pattern provided on the transparent glass substrate 3, and as the photocatalyst layer 5 on the pattern surface of the mask 4, The mixture of the titanium dioxide fine particle dispersion and ethanol is applied and heat treated at 150 ° C.

After exposure under the above conditions, as shown in FIGS. 9C and 9D, only the UV-exposed portion 6 improved wettability, and a lyophilic region was formed.

(Gate Wiring Formation Step 102)

Next, the gate wiring forming step 102 will be described below with reference to FIGS. 7B, 7C, 8B, and 8C.

FIG.7 (b), FIG.7 (c), FIG.8 (b), and FIG.8 (c) are the figure which shows the state which completed the gate wiring formation process 102. FIG. FIG.7 (b) and FIG.8 (b) are top views in the pixel formation area 61 and the terminal part formation area 62 on the glass substrate 12, respectively. FIG.7 (c) and FIG.8 (c) are sectional drawing of the C-C line arrow, and D-D line arrow sectional drawing in FIG.7 (b), FIG.8 (b), respectively.

In this gate wiring formation process 102, the fluidic wiring material was apply | coated to the lyophilic region, such as the gate wiring formation area 41. As shown in FIG. The pattern forming apparatus was used here, and the organic wiring film was coated for the fluid wiring material, and what disperse | distributed silver indium alloy microparticles | fine-particles in the organic solvent was used. Silver and indium contained in the fluid wiring material at this time were set so that the ratio of indium to silver might be about 5 weight%. The wiring width was approximately 50 µm and the discharge amount of the wiring material from the ink jet head 33 was set to 40 pl.

In addition, the ratio of silver and indium contained in this fluid wiring material considers that dry etching is performed by the gate insulating film / semiconductor film process process 104, the channel part process process 107, and the protective film process process 109 later. Therefore, it is selected to have plasma resistance. However, the ratio can be suitably selected according to the manufacturing process, the performance of the TFT array substrate, and the like which are required.

On the lyophilic side, since the fluid wiring material discharged from the ink jet head 33 becomes wider along the gate wiring formation area 41, the application is performed by appropriately adjusting the discharge interval at approximately 100 to 500 mu m intervals. It was done. After application | coating, it baked at 300 degreeC for 1 hour, and formed the gate wiring 13, the gate electrode 17, the storage capacitor wiring 16, and the terminal wiring 30 which consist of silver and indium.

Here, since the gate wiring 13 etc. are comprised from silver and indium, it has sufficient heat resistance with respect to 300 degreeC conditions, and does not lose surface smoothness. In conventional silver, the surface smoothness is remarkably lost, so that leakage with the upper layer occurs, resulting in a defect.

In addition, although the gate wiring 13 etc. directly contact the glass substrate 12, since it consists of silver and indium in this Example, the adhesive force with respect to a glass substrate is enough and it does not peel in a later process. In conventional silver, since the adhesive force is small, peeling generate | occur | produced in a later process and it became defect.

The calcination temperature is set at 300 ° C because the processing heat of about 300 ° C is applied in the gate insulating film / semiconductor film film forming step 103. Therefore, the firing temperature is not limited to this temperature.

(Gate Insulating Film and Semiconductor Film Formation Step (103))

Subsequently, the gate insulating film / semiconductor film forming step 103 will be described below with reference to FIGS. 10A and 10B, and FIGS. 11A and 11B. .

10 (a), 10 (b), 11 (a) and 11 (b) show the glass substrate 12 in a state where the gate insulating film / semiconductor film film forming step 103 is completed. It is a figure which shows. FIG.10 (a) and FIG.11 (a) are top views in the pixel formation area 61 and the terminal part formation area 62 on the glass substrate 12, respectively. 10 (b) and 11 (b) are cross sectional views taken along the line E-E arrow and Fig. F-F line shown in Figs. 10 (a) and 11 (a), respectively.

In this gate insulating film / semiconductor film film forming step 103, the gate insulating film 45 and the amorphous silicon layer (the gate insulating layer 18) are formed on the glass substrate 12 which has passed through the gate wiring forming step 102, respectively, later. 19) and the continuous film formation of the amorphous silicon film 46, and an n ⁺ n ⁺ silicon film 47 is a silicon layer (20). Here, the gate insulating film 45 is a film made of silicon nitride. All these films were formed by CVD method, and each film thickness was 0.3 micrometer, 0.15 micrometer, and 0.04 micrometer in order. The film-forming temperature was 300 degreeC.

As described in the above step, the gate wiring 13 is improved in heat resistance by indium added in addition to silver, and new crystal growth is suppressed. Therefore, even under a high temperature condition of 300 ° C., the surface is not roughened, so that the gate wiring 13 having a good surface property is obtained rather than being formed of silver single body. For this reason, it does not leak with the semiconductor layer 27 and the source electrode 21 formed on it via the gate insulating layer 18, and a yield improves and the characteristic of TFT is stabilized.

(Gate Insulation Film and Semiconductor Film Processing Step 104)

Next, the gate insulating film / semiconductor film processing step 104 will be described below with reference to FIGS. 12A, 12B, 13A, and 13B. .

12 (a), 12 (b), 13 (a) and 13 (b) are diagrams showing a state in which the gate insulating film / semiconductor film processing step 104 is completed. 12 (a) and 13 (a) are plan views in the pixel formation region 61 and the terminal portion formation region 62 on the glass substrate 12, respectively. 12 (b) and 13 (b) are cross-sectional views taken along the line G-G and the cross-section taken on the line H-H in FIGS. 12 (a) and 13 (a), respectively.

In this gate insulating film and semiconductor film processing process 104, it processed using photolithography.

First, the amorphous silicon film 46 and the n ⁺ type silicon film 47 were processed by first photolithography. These are processed so as to remain in an island shape above the gate electrode 17 in the pixel formation region 61, and are processed so as not to be left in the terminal portion formation region 62. As a result, the amorphous silicon layer 19, after obtained the n ⁺ type silicon processed film 48 is an n ⁺ type silicon layer (20). The etching was performed by introducing a mixed gas of sulfur hexafluoride (SF ₆ ) gas and hydrogen chloride (HCl) gas by a dry etching method. Since the gate insulating film 45 covers the whole surface of the board up to this point, the terminal wiring 30 and the like are not exposed to the dry etching atmosphere.

Subsequently, the gate insulating film 45 was processed by second photolithography. In the terminal portion formation region 62, the gate insulating film 45 was partially etched to obtain the gate insulating layer 18 and the opening 49. The etching was performed by introducing a mixed gas of CF ₄ gas and O ₂ gas by a dry etching method.

In the dry etching of the gate insulating film 45, the opening 49 formed in the terminal portion forming region 62 and the illustration are omitted, but the terminal wiring 30 is placed in a dry etching atmosphere in other portions for electrical connection. Exposed. This is because the dry etching method is a method of good controllability, but in actual production, over etching cannot be prevented.

Here, if the terminal wiring 30 is formed of silver which is a conventional technique, it does not have plasma resistance. Therefore, the terminal wiring 30 is largely etched into the opening 49, resulting in a defect. On the other hand, in this embodiment, the terminal wiring 30 is comprised from silver and indium, and it sets so that the ratio of indium to silver may be about 5 weight%. For this reason, it has plasma resistance and can withstand such a dry etching process.

(Source Drain Wiring Pretreatment Step 105)

Next, the source-drain wiring pretreatment step 105 will be described below with reference to FIG. 14A. FIG. 14A illustrates a wiring for forming the source wiring 14, the source electrode 21, and the drain electrode wiring 22 on the glass substrate 12 that has undergone the gate insulating film and semiconductor film processing step 104. It is a top view which shows the state which formed the guide 52. FIG.

In the source / drain wiring forming step 106, since no wiring or the like is formed in the terminal portion forming region 62, only the pixel forming region 61 will be described here.

In this process, the wiring guide 52 is formed so that the area | region (source-drain formation area 53) which forms the source wiring 14, the source electrode 21, and the drain electrode wiring 22 is excluded. The wiring guide 52 was formed using the photoresist material. That is, the photoresist was applied onto the glass substrate 12 which passed through the gate insulating film / semiconductor film processing process 104, and after prebaking, exposure and development were performed using the photomask, and postbaking was performed next. . In the wiring guide 52 formed here, the line width of the region forming the source wiring 14 and the source electrode 21 is 10 μm, and the line width of the region constituting the drain electrode wiring 22 is 10 μm to 40. It formed so that it might become micrometer. The interval between the source electrode 21 and the drain electrode wiring 22, that is, the length of the channel portion 51 of the TFT is set to 4 μm.

In addition, the upper surface of the gate insulating layer 18 is subjected to a lyophilic treatment with oxygen plasma so that the wiring material applied by the pattern forming apparatus is fused to the surface serving as the base surface, and the wiring guide 52 is CF. _The liquid repellent treatment may be performed by exposing to ₄ plasma.

In addition, instead of the formation of the wiring guide 52 described above, the hydrophilic liquid treatment by the photocatalyst used for the gate electrode formation may be performed according to the wiring or the pattern of the electrode.

(Source / Drain Wiring Formation Step (106))

Subsequently, the source-drain wiring forming step 106 will be described below with reference to FIGS. 14B and 14C. 14B and 14C are diagrams showing a state in which the source / drain wiring forming step 106 is completed. FIG. 14B is a plan view of the pixel formation region 61 on the glass substrate 12. FIG. 14C is a cross-sectional view taken along the line I-I in FIG. 14B.

In this source / drain wiring forming step 106, since no wiring or the like is formed in the terminal portion forming region 62, only the pixel forming region 61 will be described.

This source-drain wiring formation process 106 is a process of forming the source wiring 14, the source electrode 21, and the drain electrode wiring 22 using the wiring guide 52 provided in the previous process. . The pattern forming apparatus as shown in FIG. 5 was used for the coating device.

Under the present circumstances, what disperse | distributed the silver indium alloy microparticles | fine-particles which coated the organic film in the organic solvent was used for the fluidic wiring material. Silver and indium contained in the fluid wiring material at this time were set so that the ratio of indium to silver might be about 5% by weight.

In addition, the ratio of silver and indium contained in this fluidic wiring material is selected so as to have plasma resistance in consideration of the dry etching performed in the subsequent channel portion processing step 107 and the protective film processing step 109. . However, the ratio can be suitably selected according to the manufacturing process, the performance of the TFT array substrate, and the like which are required.

Here, the discharge amount of the fluid wiring material from the ink jet head 33 was set to 2 pl. Formation film thickness was 0.3 micrometer. Since the temperature of baking was formed into a film at about 300 degreeC, the amorphous silicon film 46 etc. was made into the temperature 200 degreeC lower than this. The wiring guide 52 was removed using the organic solvent.

(Channel part processing process 107)

Subsequently, the channel processing step 107 will be described below with reference to FIG. 15. FIG. 15 is a view showing a state where the channel processing step 107 has been completed, and is an arrow-sectional sectional view corresponding to the position of the line I-I in FIG. 14B.

In this channel portion processing step 107, the channel portion 51 of the TFT is processed. Although this process is performed by dry etching using chlorine gas, new photolithography is not performed at this time, and processing is performed using the patterns of the source electrode 21 and the drain electrode wiring 22.

In the present embodiment, a pattern forming apparatus such as an ink jet apparatus is used for the previous step. When the source wiring 14, the source electrode 21, and the drain electrode wiring 22 are formed in this way, it is impossible in the process to leave a resist on them. Therefore, in this channel part processing process 107, since the channel part 51 is processed using these source wirings 14 etc. as a mask, these source wirings 14 etc. start etching. It is exposed to a dry etching atmosphere for a long time from the end to the end.

That is, especially in the case of using a pattern forming apparatus such as an ink jet apparatus, the source wiring 14 or the like is required to be resistant to high dry etching atmosphere (plasma resistance).

Since the source wiring 14 etc. which comprise the conventional silver single substance do not have plasma resistance, since most of wiring is etched and the target electroconductivity is not obtained, it became defect. On the other hand, in this embodiment, the source wiring 14 etc. are comprised from silver and indium, and it sets so that the ratio of indium to silver may be about 5 weight%. For this reason, it has plasma resistance and can withstand such a dry etching process.

Thus, since the wiring material which consists of silver and indium of this invention has high plasma resistance, the manufacturing method of the TFT array board | substrate using the pattern forming apparatus conventionally difficult is facilitated.

(Protective film and interlayer insulating layer film forming step 108)

Subsequently, the protective film and interlayer insulating layer film forming step 108 will be described below with reference to FIGS. 16A and 16B and 17A and 17B. . 16 (a) and 16 (b) and 17 (a) and 17 (b) are diagrams showing a state where the present protective film / interlayer insulating layer film forming step 108 is completed. . FIG. 16A and FIG. 17A are plan views of the pixel formation region 61 and the terminal portion formation region 62 on the glass substrate 12, respectively. 16B and 17B are sectional views taken along the line J-J arrow and K-K line arrow in FIGS. 16A and 17A, respectively.

In this protective film and interlayer insulation layer film forming step 108, first, a silicon nitride film 55 is formed on the glass substrate 12 that has undergone the previous step by CVD. The substrate temperature at this time is set to 200 ° C.

Next, the photosensitive acrylic resin material was apply | coated on this silicon nitride film 55. FIG. Subsequently, the interlayer insulating layer 26 having a predetermined pattern was obtained by performing exposure using a mask, developing, and baking. At this time, the opening part 56 is formed in the part which the drain electrode wiring 22 and the storage capacitor wiring 16 overlap. On the other hand, in the terminal part formation area 62, the interlayer insulation layer 26 is not formed in the whole surface.

(Protective Film Processing Step (109))

Subsequently, the protective film processing step 109 will be described below with reference to FIGS. 18A and 18B. 18A and 18B are diagrams showing a state in which the protective film processing step 109 is completed. 18A and 18B are arrow sectional views at positions indicated by the J-J lines and the K-K lines in FIGS. 16A and 17A, respectively.

In the protective film processing step 109, the silicon nitride film 55 formed in the protective film and the interlayer insulating layer film forming step 108 is processed into a pattern of the interlayer insulating layer 26. In the pixel formation region 61, the silicon nitride film 55 directly below the opening 56 is etched to obtain the protective layer 25 and the contact hole 23. On the other hand, in the terminal part formation area 62, the silicon nitride film 55 is etched and removed in the whole surface. The etching was performed by introducing a mixed gas of CF ₄ gas and O ₂ gas by a dry etching method.

In the dry etching of the silicon nitride film 55, a part of the drain electrode wiring 22 or the terminal wiring 30 is dried in the contact hole 23 or the opening 49 in the terminal portion 28. It is exposed to an etching atmosphere. This is because the dry etching method is a method of good controllability, but in actual production, over etching cannot be prevented.

Silver, which is a conventional technique, does not have plasma resistance. Therefore, in this case, a part of the drain electrode wiring 22 and the terminal wiring 30 are largely etched, resulting in a defect. On the other hand, in this embodiment, the drain electrode wiring 22 and the terminal wiring 30 are comprised from silver and indium, and it sets so that the ratio of indium to silver may be about 5 weight%. For this reason, it has plasma resistance and can withstand such a dry etching process.

(Pixel Electrode Formation Step 110)

As a final step, an ITO (indium tin oxide) film serving as the pixel electrode 24 and the terminal electrode 29 was later formed by the sputtering method. The substrate temperature at this time was 200 degreeC. Subsequently, this ITO film was patterned using photolithography to obtain a TFT array substrate 11 shown in FIGS. 1, 2, 3A, 3B, and 4.

Thus, since the material of this invention has the adhesive force with respect to the outstanding glass substrate which does not exist in the conventional silver single body, it withstands a series of manufacturing processes, and the defect by peeling of a gate wiring does not arise.

In addition, since the material of the present invention has excellent heat resistance not found in the conventional silver single body, even when the substrate is exposed under the high temperature conditions of 300 ° C as in the present embodiment, the surface does not become rough, so that the gate wiring has good surface smoothness. (13), storage capacitor wiring 16, gate electrode 17 and the like are obtained. For this reason, the source wiring 14, the semiconductor layer 27, the source electrode 21, etc. which are formed thereon via the gate insulating layer 18 do not leak, and a yield improves, and the characteristic of TFT is also It is stable.

And, above all, the material of the present invention having high plasma resistance enables such a manufacturing process.

In this embodiment, etching of the gate insulating film 45 in the gate insulating film / semiconductor film processing step 104, etching of the n ⁺ type silicon processing film 48 in the channel portion processing step 107, and a protective film Dry etching is used in three steps of the etching of the silicon nitride film 55 in the processing step 109. At this time, when wiring, an electrode, etc. were formed by the conventional silver single body, it etched at the time of over-etching or when it became an etching mask of another film | membrane, and became defect. By the way, like this embodiment, since the wiring material of this invention containing silver and indium has the outstanding plasma resistance, it does not become a defect.

As described above, in the manufacture of a TFT array substrate, dry etching is used abundantly, and accordingly, high dry etching resistance (plasma resistance) is required as a material constituting a wiring, an electrode, or the like. The material containing indium mainly composed of the silver of the present invention has high plasma resistance, and is particularly excellent as a material for forming wirings, electrodes and the like on a TFT array substrate.

In addition, the material of this invention is especially effective when drawing and forming the source wiring 14, the source electrode 21, etc. with the pattern forming apparatus like the inkjet system like this embodiment. In this case, since the source wiring 14 or the like becomes an etching mask for the formation of the n ⁺ type silicon layer 20, it is exposed to a dry etching atmosphere for a long time from the start of etching to the end. Therefore, this process was difficult in the case of using a conventional silver single body. However, the material of the present invention makes it possible to manufacture a TFT array substrate by such a pattern forming apparatus.

As described above, the silver alloy material of the present invention is a material that is particularly suitable for a manufacturing process using a coating device such as an ink jet device, and is included in a fluid wiring material and is advantageously used. Moreover, as mentioned later, also in the manufacturing method performed without using a pattern forming apparatus, it is a material used advantageously similarly.

In this embodiment, it is a six-sheet mask process which performs an exposure and image development process using a photomask six times in total. In order to produce a TFT array substrate at a lower cost, a five-sheet mask process of reducing this once is also widely used. In this case, the easiest method that does not use halftone exposure or the like is to form the gate insulating layer 18 and the protective layer 25 by successively etching the gate insulating film 45 and the silicon nitride film 55. It is a way. However, in this case, especially, the exposed part formed in the drain electrode wiring 22 is exposed to a dry etching atmosphere for a long time, and it is necessary to withstand severe use conditions.

In order to think about this reason, the state of the board | substrate under etching is considered. First, since there is a film on the entire surface while the silicon nitride film 55 is etched, there is no problem. However, during the etching of the gate insulating film 45 subsequent to this, for example, an exposed portion formed in the contact hole 23 of the drain electrode wiring is always directly exposed to the dry etching atmosphere from the start to the end of the etching. This is a very long time and is a harsh process condition.

Therefore, in the case of such a five-sheet mask process, in particular, high plasma resistance is required for the drain electrode wiring 22. The silver alloy material of the present invention represented by silver alloy material containing silver and indium has a high plasma resistance. Since it is provided with a castle, it can be used also in such a case, and its use range is wide.

In addition, although this embodiment forms the terminal wiring 30 in the same process as the gate wiring 13 etc. in a six-sheet mask process, the scope of the present invention is not limited to this. In most current manufacturing methods in which a silicon nitride film, which is a gate insulating layer 18 or a protective layer 25, is formed on the entire surface of a substrate and partially removed by dry etching, a portion for removing them for electrical connection is provided. Essentially, plasma resistance against over etching is necessarily required for electrodes, wirings, and the like disposed thereunder. This invention provides the material excellent in plasma resistance, and exhibits the outstanding effect with respect to the manufacturing process of these TFT array substrates.

In this embodiment, what disperse | distributed the silver indium alloy microparticles | fine-particles which coated the organic film in the organic solvent was used for the fluidic wiring material. Silver and indium contained in the fluid wiring material at this time were set so that the ratio of indium to silver might be about 5% by weight. However, the ratio of indium to silver can be appropriately selected so as to have appropriate plasma resistance in accordance with the manufacturing process, or in accordance with the performance of the TFT array substrate required.

In addition, the form of this fluid wiring material is not limited to the form containing silver and indium as microparticles | fine-particles of a silver indium alloy. The fine particles of silver and the fine particles of indium may be prepared separately and may be dispersed in a solvent independently. Moreover, it is not necessarily limited to microparticles | fine-particles, The form which silver or indium contains in a solvent in the aspect of a metal compound may be sufficient.

In this embodiment, although the wirings, electrodes, etc. of the source wiring 14, the gate wiring 13, etc. were formed with the silver alloy material containing silver and indium, it is not limited to this, Comprising: It contains silver and zinc. A silver alloy material may be sufficient. You may form the gate wiring 13 etc. by the silver alloy material containing silver and at least 1 type of element chosen from tin, zinc, lead, bismuth, indium, and gallium. In addition to these elements, at least aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, The silver alloy material which contains the element chosen from neodymium may be sufficient.

[Embodiment 2]

Another embodiment of the present invention will be described below with reference to FIGS. 6 and 19 (a) and 19 (b).

In the first embodiment, in the gate wiring forming step 102 and the source and drain wiring forming step 106, a pattern forming apparatus such as an ink jet method is used.

The TFT array substrate 71 according to the present embodiment is created similarly to the case of the first embodiment, in the same manner as the manufacturing process diagram shown in FIG. 6, but the difference is two or more types of fluidity in the gate wiring forming step 102. It is a point to form (differentially apply | coating) wirings from which a composition differs in each part in a board | substrate using wiring material.

In the following description, components having substantially the same functions as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted here.

19A and 19B show the TFT array substrate 71 in the present embodiment. FIG. 19A is a plan view of the terminal portion forming region 62 of the TFT array substrate 71, and FIG. 19B is a cross-sectional view taken along the line L-L in FIG. 19A. The pixel portion formed in the pixel formation region 61 shown in FIG. 4 is configured similarly to the first embodiment. As shown in Figs. 19A and 19B, in the TFT array substrate 71 of the present embodiment, the terminal wiring 72 is in contact with the terminal wiring connecting portion 73, and they have electrical conduction.

Since the terminal wiring 72 is covered with the gate insulating layer 18, the terminal wiring 72 may be selected so as to have heat resistance and adhesion to the glass substrate during process resistance. The plasma resistance is not necessary because it is not exposed to a dry etching atmosphere. On the other hand, in order to make the circuit board used especially for a large sized liquid crystal display device, the electrical resistance of the terminal wiring 72 should be made as small as possible. For this reason, the terminal wiring 72 was configured so that the content of indium with respect to silver became 3 weight%. The electrical resistivity of this part is about 6 mu OMEGA cm. In addition, the gate wiring 13, the gate electrode 17, and the storage capacitor wiring 16 in the pixel formation region 61 also have indium to silver so as to have a lower electrical resistance for the same reason as the terminal wiring 72. It was comprised so that content of may be 3 weight%.

On the other hand, the terminal wiring connection part 73 is exposed to a dry etching atmosphere by over etching in the etching process for electrical connection. Therefore, emphasis was placed on plasma resistance, and it comprised so that content of indium with respect to silver might be 10 weight%. This terminal wiring connection portion 73 is much shorter than the gate wiring 13 on the TFT array substrate, the source wiring 14 and the terminal wiring 72, and the electrical resistivity may be larger than the other portions.

Of course, similarly to Embodiment 1, both the terminal wiring 72 and the terminal wiring connection part 73 may have the same structure, ie, content so that content of indium may be 5 weight% with respect to silver. By the way, according to the performance required for the individual parts as in the present embodiment, wiring, electrodes, etc., which are lower electric resistances as a whole, can be formed, so that a larger circuit board and a larger There is an advantage that a display device or the like can be realized.

The manufacturing method of this embodiment is demonstrated below.

As described above, the TFT array substrate 71 in the present embodiment is produced in almost the same manner as in the first embodiment, but the difference is that in the gate wiring forming step 102, the differential coating of the fluid wiring material is applied. It is a point. This is achieved by providing the pattern forming apparatus as shown in FIG. 5 with a function of discharging at least two types of fluidic wiring materials. That is, the ink supply system 36 and the control unit 37 are provided so that at least two ink jet heads 33 are provided or two kinds of fluid wiring materials can be handled in the same ink jet head 33. The discharge position information can also be realized by making it correspond to this.

By using such a pattern forming apparatus, two types of fluidic wiring materials having different contents of indium to silver were discharged in the same manner as in the first embodiment. In the area | region for forming the terminal wiring 72, when it became the terminal wiring 72, the fluidic wiring material which content of indium with respect to silver became 3 weight% was discharged. On the other hand, in the area | region for forming the terminal wiring connection part 73, when it became the terminal wiring connection part 73, the fluidic wiring material which content of indium with respect to silver became 10 weight% was discharged. On the other hand, in the region for forming the gate wiring 13, the gate electrode 17, and the storage capacitor wiring 16 in the pixel formation region 61, the same fluidic wiring material as that of the terminal wiring 72 was discharged. After discharge, baking was carried out at 300 ° C. for 1 hour in the same manner as in the first embodiment to obtain a predetermined terminal wiring 72, a terminal wiring connecting portion 73, and the like.

In the present embodiment, a pattern forming apparatus such as an ink jet method can apply a separate coating on the substrate surface, and wirings formed at the same process require different plasma resistance or conductivity at each part. It is important to have a good combination of the indium content of the material of the present invention and the relationship between conductivity and process resistance. This makes it possible to manufacture a large-sized TFT array substrate which is easy to manufacture and has good electrical characteristics.

In addition, in this embodiment, the terminal wiring 72 and the terminal wiring connecting portion 73 have boundaries 74 having different indium contents as shown in FIGS. 19A and 19B. But it is not limited to this. The indium content may change slowly near the boundary. As the formation method, fluidized wiring materials may be mixed with each other naturally, and may be intentionally mixed, such as discharging two types alternately. In addition, the position of the boundary 74 is not necessarily limited to the position of FIG. It may be connected to another part to some extent so that the effect as mentioned above may be acquired substantially.

Of course, it is an important point of this embodiment to provide wiring, an electrode, etc. which increased indium content in the part which is needed as TFT array substrate 71 and is exposed to a dry etching atmosphere during a manufacturing process.

Thus, the silver alloy material of this invention respond | corresponds to many manufacturing processes by performing separate coating even when content of indium with respect to silver is comparatively low like 1 weight% or 3 weight%, for example. It can be suitably used as a material which constitutes wiring and an electrode of (13) etc., especially low electrical resistance.

In addition, the form of the fluid wiring material in this embodiment is not limited to the form containing silver and indium as microparticles | fine-particles of a silver indium alloy. The fine particles of silver and the fine particles of indium may be prepared separately and may be dispersed in a solvent independently. Moreover, it is not necessarily limited to microparticles | fine-particles, The form which silver or indium contains in a solvent in the aspect of a metal compound may be sufficient.

Moreover, in this embodiment, although the gate wiring 13 etc. were formed with the silver alloy material containing silver and indium, it is not limited to this, The silver alloy material containing silver and zinc may be sufficient. You may form the gate wiring 13 etc. by the silver alloy material containing silver and at least 1 type of element chosen from tin, zinc, lead, bismuth, indium, and gallium. In addition to these elements, at least aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten and neodymium A silver alloy material characterized by including an element selected from may be sufficient.

In addition, you may use according to the place so that a structure may differ from each other on TFT array substrate 71, such as silver and indium, silver, and zinc.

Embodiment 3

Another embodiment of the present invention will be described as follows.

In the second embodiment, in the gate wiring forming step 102, a pattern forming apparatus typified by an ink jet method is used, and differential coating of different wiring materials on the TFT array substrate 71 is performed.

In the following description, components having substantially the same functions as the first and second embodiments are denoted by the same reference numerals, and description is omitted here.

In the present embodiment, in place of the gate wiring forming step 102, in the source and drain wiring forming step 106, separate coating of wiring materials having different configurations is performed. For example, this is comprised so that content of indium with respect to silver may be 3 weight% in the case of the source electrode 21 and the source wiring 14, and 10 weight% in the case of the drain electrode wiring 22. FIG.

In addition, in the drain electrode wiring 22, the content of indium with respect to silver may be apply | coated so that it may become 3 weight% and 10 weight%, and plasma resistance may improve in the vicinity of the contact hole 23. FIG. In addition, such an application | coating may be performed at arbitrary places on the TFT array substrate of this embodiment.

In addition, the form of the fluid wiring material in this embodiment is not limited to the form containing silver and indium as microparticles | fine-particles of silver indium alloy similarly to Embodiment 2. As shown in FIG. The fine particles of silver and the fine particles of indium may be prepared separately and may be dispersed in a solvent independently. Moreover, it is not necessarily limited to microparticles | fine-particles, The form which silver or indium contains in a solvent in the aspect of a metal compound may be sufficient.

In addition, the wiring material used by this embodiment is not limited to the material comprised from silver and indium similarly to Embodiment 2, The silver alloy material containing silver and zinc may be sufficient. You may form the source wiring 14 etc. by the silver alloy material containing silver and at least 1 type of element chosen from tin, zinc, lead, bismuth, indium, and gallium. In addition to these elements, at least aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten and neodymium A silver alloy material characterized by including an element selected from may be sufficient.

Moreover, you may use according to the place differently so that a structure may differ from each other on TFT array substrates, such as silver and indium, silver, and zinc.

In addition, Embodiment 2 and Embodiment 3 can be implemented in combination. That is, it is also possible to perform separate coating in both the gate wiring forming step 102 and the source and drain wiring forming step 106.

In Embodiments 1 to 3 of the present invention described above, a pattern forming apparatus for ejecting droplets of a fluid wiring material such as an ink jet method was used. However, the silver alloy material of the present invention can be advantageously used similarly without using such a pattern forming apparatus. In this case, the TFT array substrate is manufactured by the most common method using the conventional sputtering method or vapor deposition method and photolithography in a corresponding process. However, wirings, electrodes, and the like formed according to the silver alloy composition of the present invention are obtained using a sputtering target, a vaporization evaporation source, and the like, instead of the fluidic wiring material. In this case, the silver alloy material of the present invention is advantageously used as a material having excellent process resistance such as heat resistance, adhesion, plasma resistance, and low electrical resistance.

In addition, the silver alloy material of the present invention can be advantageously used as one layer of a multilayer wiring structure formed by superposing two or more layers of materials. For example, even if calcined at 300 ° C., surface smoothness is not lost as in the case of silver alone, and especially, including indium, its content is relatively large, for example, 5% by weight or 10% by weight with respect to silver. In this case, it has sufficient plasma resistance and can be effectively used as a protective metal layer for protecting the wiring under the layer. In addition, it can be used as all or part of the source electrode 21 and the drain electrode wiring 22 for directly contacting the semiconductor layer 27 in Embodiment 1 to obtain an electrical connection, and similarly excellent heat resistance, It exhibits an adhesive force and is advantageously used for the manufacturing process of a TFT array substrate.

Alternatively, the silver alloy material of the present invention may be used for a light reflective electrode on a TFT array substrate used for a reflective TFT liquid crystal display device or the like. In this case, due to the excellent heat resistance of the silver alloy material of the present invention, even if it is heat-fired at 300 ° C, for example, the surface smoothness is not lost as in the case of silver alone. Therefore, light scattering other than the design does not occur, and sufficient light reflectance can be maintained as a light reflective electrode, and the characteristics as a TFT array substrate can be fully exhibited.

Moreover, in the silver alloy material of this invention, especially when the content rate of indium with respect to silver is 0.5 weight% or less, the electrical resistivity is 2.7 microohm cm or less, and formation of the low electrical resistance wiring which cannot be achieved with conventional aluminum wiring is This is possible and profitable. However, since the content of indium is low, the plasma resistance is not sufficient, and it is generally necessary to laminate another metal film or the like. Regarding the adhesion force to the substrate, since the content of indium is low, it is not sufficient, so a basic treatment or the like may be necessary.

[Embodiment 4]

Another embodiment of the present invention will be described as follows.

In addition, in the following description, the component which has a function substantially the same as the said Embodiment 1 thru | or Embodiment 3 is shown with the same code | symbol, and description is abbreviate | omitted here.

In the second embodiment, in the gate wiring forming step 102, a pattern forming apparatus typified by an ink jet method is used, and differential coating of different wiring materials on the TFT array substrate 71 is performed. On the other hand, in the said Embodiment 3, in the source-drain wiring formation process 106, the separate application | coating of the wiring material from which a structure differs was performed.

In the present embodiment, in the gate wiring forming step 102, the sputtering method is used to form wirings, and the wirings are laminated with the silver alloy material of the present invention and titanium.

26 (a) and 26 (b), 27 (a) and 27 (b) show a state in which the gate wiring forming step 102 is completed in the present embodiment. to be. 26A and 27A are plan views in the pixel formation region 61 and the terminal portion formation region 62 on the glass substrate 12, respectively. FIG. 26B and FIG. 27B are cross-sectional views taken along the line M-M and cross-section taken on the line N-N in FIG.

In these figures, the gate wiring 80, the gate electrode 81, the storage capacitor line 82, and the terminal wiring 83 have the same laminated structure and consist of two layers. Each layer 80a, 81a, 82a, 83a on the side close to the glass substrate 12 is made of the silver alloy of the present invention, and the content of indium with respect to silver is 0.2% by weight. Each layer 80b, 81b, 82b, and 83b on the upper layer side thereof is made of titanium. The film thicknesses of the reference numerals 80a, 81a, 82a, 83a, 80b, 81b, 82b, and 83b were all 0.2 µm.

In this embodiment, since each layer 80a, 81a, 82a, and 83a of the side near the glass substrate 12 is formed from the alloy which consists of silver and indium, it is heat resistant, and is about 300 degreeC in a later process. Even if firing is performed, no adverse effect is observed on the gate wiring 80 or the like. In the case where these were formed of conventional silver single members, since there was no heat resistance, remarkable surface irregularities occurred, and leak defects with the upper layer occurred.

If the content of indium is a silver alloy of 0.5% by weight or less, as described above, the electrical resistivity is 2.7 µΩcm or less, and the formation of wiring of low electrical resistance, which is not feasible with aluminum, is possible. In the example of this embodiment, the electrical resistivity is very low, about 2.3 mu OMEGA cm. Therefore, when low electrical resistance of wiring is particularly desired, for example, in a liquid crystal display device such as for a liquid crystal TV, the silver alloy material of the present invention is a useful material.

In this embodiment, the formation method of the gate wiring 80 etc. is demonstrated. In the gate wiring forming step 102, since the pattern forming apparatus represented by the ink jet method is not used, the process corresponding to the gate wiring pretreatment step 101 has not been performed.

First, the silver alloy film containing indium 0.2 weight% with respect to silver was formed into a film of 0.2 micrometer on the glass substrate 12 by the sputtering method. At this time, as a target for sputter | spatter, the alloy target which made indium into the solid solution was used.

Next, titanium was continuously formed into a film by the sputtering method in vacuum. The film thus obtained was processed by photolithography to obtain gate wirings and the like shown in FIGS. 26A and 26B, 27A and 27B. The dry etching method was used for the etching at this time.

The terminal wiring 83 and the like require plasma resistance in consideration of the subsequent steps, but in the present embodiment, it is obtained by titanium on the upper layer side.

Thus, the silver alloy material of this invention may be used as one layer of a multilayer wiring structure, and by making indium 0.5 weight% or less with respect to silver, the wiring of the low electrical resistance which cannot be realized with conventional aluminum is implement | achieved.

Moreover, in the formation method, although the silver alloy film of this invention was formed into a film directly on the glass substrate 12, when the adhesive force with respect to a board | substrate is not fully acquired, even if the intermediate | middle layer which consists of metals etc. is provided in the middle of both. The adhesion may be obtained by surface-treating the glass substrate with plasma, chemicals, or the like.

In the present invention, the materials of the upper layers 80b, 81b, 82b, and 83b are not limited to titanium, but include chromium, molybdenum, tantalum, tungsten, or nitrogen and oxygen in these materials, or ITO. Metal oxides, such as (indium tin oxide), may be sufficient. In the formation of the gate wiring 80 and the like, the fluid wiring material may be applied and laminated in the same manner as in the first embodiment, or may be formed by film deposition and processing by a vapor deposition method using an evaporation source made of silver and indium.

In the present embodiment, in the gate wiring forming step 102, the wiring is formed by a film made of the silver alloy and titanium of the present invention, but as another embodiment of the present invention, the source and drain wiring forming step 106 is performed. In the same manner, a wiring formed of a laminated film may be formed. Even in this case, since the alloy made of silver and indium has heat resistance, no adverse effect is seen even if firing is performed in a later step.

Also in this case, by making indium 0.5 weight% or less with respect to silver, the wiring of the low electrical resistance which cannot be realized with conventional aluminum can be implement | achieved.

Alternatively, the silver alloy material of the present invention may be used for a light reflective electrode on a TFT array substrate used for a reflective TFT liquid crystal display device or the like. In this case, due to the excellent heat resistance of the silver alloy material of the present invention, even if it is heat-fired at 300 ° C, for example, the surface smoothness is not lost as in the case of silver alone. Therefore, light scattering other than the design does not occur, and sufficient light reflectance can be maintained as a light reflective electrode, and the characteristics as a TFT array substrate can be fully exhibited.

In this case, the silver alloy material which preferably contains indium 0.5 weight% or less with respect to silver is preferable, More preferably, the silver alloy material which contains 0.2 weight% or less of indium with respect to silver is preferable.

[Embodiment 5]

Another embodiment of the present invention will be described as follows.

In addition, in the following description, the component which has a function substantially the same as the said Embodiments 1-4 is shown with the same code | symbol, and description is abbreviate | omitted here.

As described in Embodiment 1 of the present invention, among the silver alloy materials of the present invention, a film made of a silver alloy material containing 0.5 wt% or less of indium with respect to silver has a high visible light reflectance even after firing at 200 ° C. More preferably, the film | membrane produced from the silver alloy material containing 0.2 weight% or less of indium with respect to silver has high visible light reflectance even after baking at 300 degreeC. For this reason, it is suitable for a light reflection film use.

In this embodiment, the light reflective electrode is formed of the silver alloy material containing 0.2 weight% of indium with respect to silver. Many of these light reflective electrodes are formed on a TFT array substrate. This will be described below.

The reflective TFT liquid crystal display device according to the present embodiment has a pixel shown in FIG. 28. 28 is a plan view showing a schematic configuration of one pixel in the TFT array substrate 91 of the reflective TFT liquid crystal display device. 29 is a cross sectional view taken along the line O-O in FIG. In the present embodiment, one of the points different from the liquid crystal display devices such as Embodiment 1 of the present invention is that the light reflective electrode 84 is provided. This light reflecting electrode is an electrode for applying a voltage to a liquid crystal layer (not shown) included in the liquid crystal display device, and has a role of obtaining image display by reflecting or scattering external light incident on the liquid crystal display device. .

Moreover, the liquid crystal display device which concerns on this embodiment has the terminal part 28 shown to FIG. 30 (a). The terminal portion 28 is a connecting portion for electrically connecting an external circuit board, a driver IC for driving, and the like to the TFT array substrate 91. 30A is a plan view showing the schematic configuration of one terminal portion in the TFT array substrate 91 of the liquid crystal display device. In addition, the sectional view of the P-P line arrow in FIG. 30A is shown in FIG. 30B.

As shown in FIG. 30B, the terminal portion 28 is configured to arrange the terminal wiring 30, the gate insulating layer 18, and the terminal electrode 85 from the glass substrate 12 side. Unlike the first embodiment and the like of the present invention, the terminal electrode 85 is made of a silver alloy material containing 0.2% by weight of indium with respect to silver.

Incidentally, in the reflective TFT liquid crystal display device, an uneven shape may be provided in the interlayer insulating layer 26 to control reflection or scattering of external light. However, since it does not affect the contents of the present invention, it is omitted here. have.

In order to manufacture this reflective TFT liquid crystal display device, it is necessary to bake the substrate at about 160 ° C to 200 ° C after the formation of the light reflective electrode. For example, it is because film-forming of a liquid crystal aligning film (not shown). For this reason, heat resistance is necessary for the light reflective electrode 84.

In conventional silver, since heat resistance was remarkably inferior, it was cloudy and was a material which can not be used at all. In the silver alloy material of the present invention, for example, when indium is contained in an amount of 0.2% by weight with respect to silver, it is possible to withstand these firings and obtain a total visible light reflectance higher than that of aluminum commonly used in the past. For this reason, by using the silver alloy material of this invention for a reflective TFT liquid crystal display device, the display which is brighter than the case of the conventional aluminum is possible, and the advantage that display performance improves is acquired.

The manufacturing method of the light reflective electrode 84 and the terminal electrode 85 which concern on this embodiment is demonstrated below.

In this embodiment, the film formation was performed on the board | substrate of completion of the protective film processing process 109 as shown to FIG. 18 (a) and FIG. 18 (b). The film-forming method was sputtering method, the film-forming temperature was 100 degreeC, and the target for sputter | spatter used the alloy target which made indium into the solid solution. Thus, the silver alloy film containing 0.2 weight% of indium with respect to silver was formed into a film with a thickness of 0.2 micrometer.

The silver alloy film thus obtained was processed into a predetermined pattern by photolithography to obtain a light reflective electrode 84 and a terminal electrode 85 shown in FIGS. 28 to 30. The etching at this time was performed by wet etching using an etching solution containing acetic acid, phosphoric acid and nitric acid.

Thus, among the silver alloy materials of this invention, the film | membrane made from the silver alloy material containing indium 0.5 weight% or less with respect to silver has a high visible light reflectance even after baking at 200 degreeC, and the light reflectance is generally superior to aluminum. Therefore, it is very useful industrially. More preferably, a film made of a silver alloy material containing indium of 0.2% by weight or less with silver has a high visible light reflectance even after firing at 300 ° C., and has the advantage of being able to withstand more stringent manufacturing conditions.

In addition, the manufacturing method of the light reflective electrode 84 and the terminal electrode 85 is not limited to these methods, and may be formed after apply | coating a fluidic wiring material similarly to Embodiment 1, etc., and contains indium. You may form and process into a film by the vapor deposition method using the evaporation source which consists of silver.

In the above forming method, although the silver alloy film of the present invention is formed directly on the interlayer insulating layer 26, when sufficient adhesion cannot be obtained, an intermediate layer made of metal or the like may be provided between the two. The adhesion may be obtained by surface-treating the surface of the interlayer insulating layer with plasma, chemicals, or the like.

In addition, the silver alloy material of this invention is used also as a bus electrode and the data electrode on the glass substrate which comprises a PDP (plasma display panel). These electrodes are disposed on the front glass substrate or the rear glass substrate in order to drive the PDP. Conventionally, these electrodes have been composed of silver, chromium / copper / chrome, and aluminum / chromium. Since copper and aluminum had weak adhesive force with respect to a glass substrate, it could not be used unless it set it as the structure which sandwiches a chromium layer between glass substrates in this way. On the other hand, the conventional silver had a problem in heat resistance, growth of crystal grains occurred by high temperature baking, and it was a material which is difficult to use.

On the other hand, since the silver alloy material of this invention has the outstanding heat resistance and the adhesive force with respect to a glass substrate, it is advantageously used as a bus electrode and a data electrode instead of these materials, such as conventional silver.

Embodiment 6

Another embodiment of the present invention will be described as follows.

In this embodiment, a TFT array substrate and a liquid crystal display device using the silver alloy material described in each of the above embodiments as a wiring material for wiring (including electrodes) of a TFT array substrate, which is a kind of circuit board, will be described. .

The silver alloy material used here is a material constituting a wiring or an electrode formed on an insulating substrate such as a glass substrate, and is mainly composed of silver and at least one selected from tin, zinc, lead, bismuth, indium, and gallium. It contains the above elements.

When the silver alloy material of the said structure is used, the wiring or electrode which is low electrical resistance, and has high process resistance, such as heat resistance, adhesion to a glass substrate, and plasma resistance, can be formed.

The TFT array substrate and the liquid crystal display device according to the present embodiment will be described below with reference to FIGS. 1, 2, 4, and 31.

The liquid crystal display device according to the present embodiment has a pixel shown in FIG. 1. 1 is a top view which shows schematic structure of one pixel in the TFT array substrate 11 of a liquid crystal display device. In addition, sectional drawing of the arrow A-A in FIG. 1 is shown in FIG.

1 and 2, in the TFT array substrate 11, on the glass substrate (insulating substrate) 12, the gate wiring 13 and the source wiring 14 are provided in a matrix form. And a TFT 15 serving as a switching element is provided near these intersections. In addition, the storage capacitor wiring 16 is provided between the adjacent gate wirings 13.

As shown in FIG. 2, on the glass substrate 12, a gate electrode 17 formed by branching from the gate wiring 13, and a storage capacitor wiring 16 are formed, and the gate insulating layer 18 is formed thereon. Is formed.

On the gate electrode 17, an amorphous silicon layer 19, an n ⁺ type silicon layer 20, a source electrode 21, and a drain electrode wiring 22 are formed via the gate insulating layer 18. TFT 15 is formed. Here, the source electrode 21 branches off from the source wiring 14.

The drain electrode wiring 22 extends from the TFT 15 to the contact hole 23, serves as a drain electrode of the TFT 15, and electrically connects the TFT 15 and the pixel electrode 24. And the contact hole 23 to form an electric capacitance between the storage capacitor wiring 16 and the storage capacitor wiring 16. In this upper layer, a protective layer 25 covering the TFT 15, an interlayer insulating layer 26 for planarization, and the like, and a pixel electrode 24 for applying a voltage to a liquid crystal or the like are formed.

Hereinafter, the area | region on the glass substrate 12 in which such a pixel is provided is called pixel formation area 61, and is shown in subsequent FIG.

Moreover, the liquid crystal display device which concerns on this embodiment has the terminal part 28 shown to Fig.31 (a). The terminal portion 28 is a connecting portion for electrically connecting an external circuit board, a driver IC for driving, and the like to the TFT array substrate 11. 31 (a) is a plan view showing a schematic configuration of one terminal portion in the TFT array substrate 11 of the liquid crystal display device. In addition, sectional drawing of the L-L line arrow in FIG. 31A is shown in FIG. 31B.

As shown to FIG. 31B, the terminal part 28 is comprised so that the terminal wiring 30, the gate insulating layer 18, and the terminal electrode 29 may be arrange | positioned from the glass substrate 12 side. The terminal electrode 29 is disposed for the purpose of improving electrical connection with an external circuit board and a driver IC for driving. The terminal wiring 30 is connected to the gate wiring 13, the source wiring 14, and the like in the pixel formation region.

Moreover, in this embodiment, the said terminal wiring 30 and the terminal electrode 29 are all formed on the glass substrate 12, and all are comprised from the silver indium alloy which is a silver alloy material of the same composition. However, in the terminal wiring 30 and the terminal electrode 29, the content ratio of indium to silver is different. Here, the mixing ratio is adjusted so that the content ratio of indium to silver in the terminal wiring 30 is smaller than the content ratio of indium to silver in the terminal electrode 29.

Hereinafter, the area | region on the glass substrate 12 in which this terminal part 28 is provided is called terminal part formation area 62, and is shown in following FIG.

4 is a plan view of the TFT array substrate 11, wherein the pixel formation region 61 and the terminal portion formation region 62 are disposed as shown on the glass substrate 12. The pixel formation region 61 and the terminal portion formation region 62 are each provided with a plurality of pixels and terminal portions as shown in Figs. 1, 2 and 31, respectively.

In the present embodiment, since the pattern forming apparatus described in the first embodiment is used for manufacturing the TFT array substrate 11, details of the apparatus are omitted.

In addition, in this embodiment, as shown to FIG. 31 (b), the terminal wiring 30 and the terminal electrode 29 are all formed on the glass substrate 12, Moreover, each content of indium is In order to form with different silver alloy materials, the ink jet head 33 needs to have the mechanism which can discharge the fluid wiring material which consists of silver alloy materials from which a compounding ratio differs at least.

For example, as shown in Figs. 32A and 32B, the flowable wiring material of the low resistance material for the wiring portion is discharged along the traveling direction (arrow direction) of the ink jet head 33. Figs. And a first head 33a for discharging, and a second head 33b for discharging the fluidic wiring material of the plasma material for the terminal portion, in order. The first head 33a and the second head 33b. It is conceivable to appropriately switch to discharge the fluid wiring material.

Details of the formation of the terminal portion using the ink jet head 33 having the above configuration will be described later.

Here, although the manufacturing method of the TFT array substrate 11 in the liquid crystal display device of this embodiment is demonstrated, the description is abbreviate | omitted about the content similar to the said 1st Embodiment.

That is, also in this embodiment, similarly to the first embodiment, the TFT array substrate 11 is manufactured by the manufacturing process shown in FIG.

Therefore, differences from the first embodiment will be mainly described.

(Gate Wiring Pretreatment Step 101)

In this gate wiring pretreatment step 101, the description of the same thing as the above embodiment is omitted.

(Gate Wiring Formation Step 102)

Next, the gate wiring forming step 102 will be described below with reference to FIGS. 7B, 7C, 8B, and 8C.

FIG.7 (b), FIG.7 (c), FIG.8 (b), and FIG.8 (c) are the figure which shows the state which completed the gate wiring formation process 102. FIG. FIG.7 (b) and FIG.8 (b) are top views in the pixel formation area 61 and the terminal part formation area 62 on the glass substrate 12, respectively. FIG.7 (c) and FIG.8 (c) are sectional drawing of the C-C line arrow, and D-D line arrow sectional drawing in FIG.7 (b), FIG.8 (b), respectively.

Next, a fluidic wiring material was applied to hydrophilic regions (liquid region) such as the gate wiring forming region 41. Here, a pattern forming apparatus is used, and a flexible wiring material can be used for wiring such as silver copper alloy, silver palladium alloy, silver gold alloy, etc. coated with an organic film, which is described in Examples 3 to 6 above. The thing which disperse | distributed silver indium alloy microparticles | fine-particles in the organic solvent was used. This is because the flatness, the plasma resistance, and the low resistance can be broadly supported by the content of indium, and can be used in combination where necessary for the purpose and where the low resistance is required. Silver and indium contained in the fluid wiring material at this time were suitably adjusted to the ratio of indium with respect to silver about 10 weight% or less. The wiring width was approximately 50 µm, and the discharge amount of the wiring material from the ink jet head 33 was set to 40 pl.

The alloy fine particles are prepared by finely mixing silver and indium in advance, and alloying them by a method such as arc melting or ion beam as a parent material to produce fine particles by evaporating them again in a rare gas and an organic solvent atmosphere to disperse them in a solvent. You can also do it.

In addition, the ratio of silver and indium contained in this fluid ink considers that dry etching is performed in the gate insulating film / semiconductor film processing process 104, the channel part processing process 107, and the protective film processing process 109 later. In the places exposed to the plasma, a silver indium alloy was used so that the ratio of indium to silver was about 10% by weight.

On the other hand, since the temperature of 300 degreeC is applied to the gate wiring at the time of the gate insulating film / semiconductor film forming process 103 which is a subsequent process, the surface of a gate wiring should not be roughened by crystal growth etc. also by this temperature. In addition, since the time required for the signal to be applied to the gate wiring is a short time of several tens of microseconds, it is necessary that the response characteristic change due to the signal delay with the TFT located at a position away from the TFT close to the driver by the resistance of the gate wiring is as small as possible. Therefore, the wiring is required to be low resistance. In consideration of this, a portion in which the ratio of indium to silver is about 5% by weight is used in a portion which is covered with a gate insulating layer or a protective film and is not directly exposed to plasma. However, the ratio can be suitably selected according to the manufacturing process, the performance of the TFT array substrate, and the like which are required.

In the hydrophilic (liquid) -treated surface, since the fluid wiring material discharged from the ink jet head 33 is widened along the gate wiring formation region 41, the ejection interval is appropriately adjusted at intervals of approximately 50 to 500 mu m. Application was carried out. After application | coating, it baked at 300 degreeC for 1 hour, and formed the gate wiring 13, the gate electrode 17, the storage capacitor wiring 16, and the terminal wiring 30 which consist of silver and indium.

Here, since the gate wiring 13 etc. are comprised from silver and indium, it has sufficient heat resistance with respect to 300 degreeC conditions, and does not lose surface smoothness. In conventional silver, the surface smoothness is remarkably lost, so that leakage with the upper layer occurs, resulting in a defect.

In addition, although the gate wiring 13 etc. contact | connects the glass substrate 12 directly, in this embodiment, since it is comprised from silver and indium, the adhesive force with respect to a glass substrate is enough and it does not peel in a later process. In conventional silver, since the adhesive force is small, peeling generate | occur | produced in a later process and it became defect.

The calcination temperature is set at 300 ° C because the processing heat of about 300 ° C is applied in the gate insulating film / semiconductor film film forming step 103. Therefore, the firing temperature is not limited to this temperature.

Next, the formation of the gate wiring by the ink jet method will be described. 35 shows a schematic diagram of the gate wirings. The whole gate wiring is shown and consists of the gate wiring 13, the storage capacitor wiring 16, and the terminal wiring 30. As shown in FIG. The gate wiring 13 is connected to a terminal of a driver IC (not shown) at the end of the substrate. The storage capacitor wiring 16 is collected in the terminal wiring 30 at one end thereof. In addition, each member number of FIG. 35 has shown the part corresponding to FIG.7 (a)-FIG.7 (c) and FIG.8 (a)-FIG.8 (c) with the same number.

As described above, the gate wiring portion is made of a silver alloy material having a ratio of indium to silver of 5% by weight, and the terminal wiring and a terminal are made of a silver alloy material having a ratio of indium to silver of 10% by weight. . These different kinds of wiring materials were separately mounted in the droplet supply apparatus of the ink jet apparatus shown in FIG. 5, and the ink jet head 33 was also prepared by the number of types of fluidic wiring materials. Here, 2 heads (refer to FIG. 32 (a) and FIG. 32 (b)) were prepared for the ratio of indium to silver for 5% by weight and the ratio of indium to silver for 10% by weight.

This situation is illustrated in FIGS. 32A and 32B. In FIG. 32 (a), the wiring material whose ratio of indium to silver is 5 weight% in the gate wiring formation area 41 of FIG. 7 (a) is made into the 1st head 33a which is a head dedicated to this material. The application is shown by the following. Next, as shown in FIG. 32 (b), the wiring material having an indium ratio of 10% by weight is used for the terminal wiring forming region 44 in FIG. 8 (a). ) Shows that the coating is performed.

At this time, since the two materials are flowable materials, they are mixed with each other on the glass substrate 12 after discharge, and are thus electrically connected after the subsequent firing step. In the intermixed regions, an intermediate state is formed partially by the nutrient solution, but, for example, all flow into the terminal portions of the terminal wiring forming region 44 in FIG. What is necessary is just to change wiring material in front of the terminal wiring formation area | region 44 so that it may not become a compounding ratio, for example, it is sufficient to switch each material in the part of several hundred micrometers before the terminal part. Of course, you may apply from a terminal part first.

In addition, you may form the gate electrode 17 shown in FIG.7 (b) by the silver alloy material with much indium content. This is because the gate electrode 17 is particularly preferably excellent in smoothness because a semiconductor layer is formed on the gate electrode 17 in a later step, and the ratio of indium to silver is 5 weights. This is because the effect is more stably obtained at 10% by weight than in the crystal growth inhibition. Moreover, as another material from which the same surface smoothness is obtained, you may mix silver with high melting metals, such as cobalt, titanium, niobium, molybdenum, for example.

When the characteristic of the wiring formed in this way is further demonstrated, the characteristic of the at least 2 site | part on the same wiring will respectively differ. Here, the characteristics are different at the wiring portion and the electrode portion of the gate wiring 30. Specifically, as described above, by varying the ratio of indium to silver in the silver indium alloy which is the wiring material, the characteristics in the respective portions (parts) are different from each other.

Moreover, in order to make the characteristic of a site | part different, you may differ in wiring material.

Here, the same wiring is a shape continuous wiring. In the circuit on a board | substrate, a circuit board | substrate is formed by gathering a plurality of such wirings, and it means one unit of these some wirings.

As described above, the wiring is preferably formed in a single layer. On the other hand, wiring has been multilayered conventionally for the following reasons.

Conventionally, there is no change in surface properties with respect to the applied heat, that is, resistance to etching gas in plasma in heat resistance and dry etching processing, that is, compatibility of plasma resistance, adhesion, etc., with resistance values as wiring This has been done by superimposing wiring materials in layer shape conventionally. That is, for example, titanium, molybdenum, or the like as an adhesion material, tantalum, on or under a wiring material which has a low resistance metal such as aluminum as a main metal and heat resistance is provided by applying a small amount of silicon and copper thereto. Niobium or the like was formed on and used as a plasma resistant material.

In this manner, conventionally, a two-layer or three-layer structure may be taken to achieve the desired performance. In particular, the wiring material used for the TFT array substrate often needs to satisfy two or more items of various performances described herein at the same time. For this reason, in forming one wiring-shaped film | membrane, a film formation process requires two or more times like 2 times and 3 times, and since an apparatus is also needed by the process, facility investment increases. Moreover, also when processing the formed film in a pattern, in order to process the layered film by the same etching material, the selection does not become as intended.

In the TFT array substrate, the film thickness may be limited for later steps. This is because a film such as a wiring formed on the top may be cut off due to the step generated by the overlapping films. In a situation where the film thickness is limited, the material formed in a layer form, that is, the tantalum and niobium is often high in specific resistance.

Therefore, the lower resistance metal part which mainly contributes to electrical conduction is required to have a lower resistance. For this reason, it is very difficult to find a material of low resistance or to find a material to be replaced when already alloyed with other required performance.

In addition, there is also a method of coping in the direction of increasing the wiring width. For example, in a panel for liquid crystal, it is also difficult to increase the wiring width because a bright screen is required by increasing the opening area of the pixel.

From this point of view, the wiring formed in a single layer as in the present application solves the above problems and is very important both in terms of cost and performance. This is the same for not only liquid materials but also sputtering and vapor deposition.

In the liquid material, in particular, the inkjet method enables the separate coating at the time of formation, so that the meaning of further monolayer is increased. Moreover, even if it is a liquid material, forming a liquid material in layer shape with ink jet does not change that it is a subject considering the manufacturing cost, such as equipment investment and tact time.

Moreover, as another advantage in the case of using a liquid material, it is the point which can use the material of the same system especially when adjusting the compounding ratio of indium in silver indium system like this embodiment. The material of the same system is a solvent in which particulate materials are dispersed, or a protective colloid which prevents agglomeration and dispersing of fine particles by using similar ones, or when the metal is contained in the solvent as a metal compound, the solvents By mixing, it does not precipitate unnecessary deposits. As an example of the fine particles, in the same system solvent, the shock at the time of mixing is small, and the fine particles hardly aggregate or precipitate due to mixing. When the liquid materials which consist of solvents having polarities that are too different from each other are mixed, separation and aggregation are likely to occur. The ink jet head for discharging such a liquid material also has a wide selection of head constituent materials, such as adhesives used inside the head, for fluid wiring materials, so that the head can be easily tuned to fluid wiring materials. do. Of course, it is possible to carefully select and mix in different solvent systems so that there is no other aggregation or precipitation. However, this sorting and tuning often take a lot of time, and considering this point, it is very useful to be a material of the same system.

In addition, what is called a single layer here refers to formation of the wiring by one layer in film-forming, and formation of the functional film required in order to satisfy | fill performance as a wiring by one application | coating in liquid. For example, like hydrophilic (hydrophilic) treatment, it is necessary to separate coating, and multilayered with a layer which does not function to actively improve adhesion, and is deposited in a subsequent step, and further imparts adhesion. The case where the film which improves adhesiveness is formed first and the above-mentioned structure is formed by one application | coating etc. is not excluded by being a single layer.

(Gate Insulating Film and Semiconductor Film Formation Step (103))

In this embodiment, the gate insulating film / semiconductor film film forming step 103 is the same as that in the first embodiment, and thus description thereof is omitted.

(Gate Insulation Film and Semiconductor Film Processing Step 104)

Next, the gate insulating film / semiconductor film processing step 104 will be described below with reference to FIGS. 12A, 12B, 13A, and 13B. .

12 (a), 12 (b), 13 (a) and 13 (b) are diagrams showing a state in which the gate insulating film / semiconductor film processing step 104 is completed. 12 (a) and 13 (a) are plan views in the pixel formation region 61 and the terminal portion formation region 62 on the glass substrate 12, respectively. 12 (b) and 13 (b) are cross-sectional views taken along the line G-G and the cross-section taken on the line H-H in FIGS. 12 (a) and 13 (a), respectively.

In this gate insulating film and semiconductor film processing process 104, it processed using photolithography.

First, the amorphous silicon film 46 and the n ⁺ type silicon film 47 were processed by first photolithography. These are processed so that they are not left in the terminal portion formation region 62 so as to remain island-shaped above the gate electrode 17 in the pixel formation region 61. As a result, the amorphous silicon layer 19, after obtained the n ⁺ type silicon processed film 48 is an n ⁺ type silicon layer (20). The etching was performed by introducing a mixed gas of sulfur hexafluoride (SF ₆ ) gas and hydrogen chloride (HCl) gas by a dry etching method. Since the gate insulating film 45 covers the whole surface of the board up to this point, the terminal wiring 30 and the like are not exposed to the dry etching atmosphere.

Subsequently, the gate insulating film 45 was processed by second photolithography. In the terminal portion formation region 62, the gate insulating film 45 was partially etched to obtain the gate insulating layer 18 and the opening 49. The etching was performed by introducing a mixed gas of CF ₄ gas and O ₂ gas by a dry etching method.

In the dry etching of the gate insulating film 45, the opening 49 formed in the terminal portion forming region 62 and the illustration are omitted, but the terminal wiring 30 is placed in a dry etching atmosphere in other portions for electrical connection. Exposed. This is because the dry etching method is a method of good controllability, but in actual production, over etching cannot be prevented.

Here, if the terminal wiring 30 is formed of silver which is a conventional technique, it does not have plasma resistance. Therefore, the terminal wiring is largely etched in the opening portion 49, resulting in a defect. On the other hand, in this embodiment, the terminal wiring 30 is comprised from silver and indium, and it sets so that the ratio of indium to silver may be about 10 weight%. For this reason, it has plasma resistance and can withstand such a dry etching process.

(Source Drain Wiring Pretreatment Step 105)

Since this source-drain wiring pretreatment process 105 is the same as that of the said Embodiment 1, description is abbreviate | omitted.

(Source / Drain Wiring Formation Step (106))

Since this source-drain wiring formation process 106 is the same as that of the said Embodiment 1, description is abbreviate | omitted.

Also, here, the wiring having a single layer has advantages similar to those described in the gate wiring process.

(Channel part processing process 107)

Since this channel part processing process 107 is the same as that of Embodiment 1, description is abbreviate | omitted.

(Protective film and interlayer insulating layer film forming step 108)

Since the protective film and the interlayer insulating layer film forming step 108 are the same as those in the first embodiment, description thereof is omitted.

(Protective Film Processing Step (109))

Since this protective film processing process 109 is the same as that of Embodiment 1, description is abbreviate | omitted.

(Pixel Electrode Formation Step 110)

As a final step, an ITO (indium tin oxide) film serving as the pixel electrode 24 and the terminal electrode 29 was later formed by the sputtering method. The substrate temperature at this time was 200 degreeC. Subsequently, this ITO film was patterned using photolithography to obtain the TFT array substrate 11 shown in FIGS. 1, 2, 31 (a), 31 (b) and 4.

Thus, since the material of this invention has the adhesive force with respect to the outstanding glass substrate which does not exist in the conventional silver single body, it withstands a series of manufacturing processes, and the defect by peeling of a gate wiring does not arise.

Moreover, since the material of this invention has the outstanding heat resistance which the conventional silver single-piece does not have, even if a board | substrate is exposed under the high temperature conditions of 300 degreeC like this Example, the surface will not become rough and the gate wiring will have good surface smoothness. (13), storage capacitor wiring 16, gate electrode 17 and the like are obtained. For this reason, the source wiring 14, the semiconductor layer 27, the source electrode 21, etc. which are formed thereon via the gate insulating layer 18 do not leak, and a yield improves, and the characteristic of TFT is also It is stable.

And, above all, the material of the present invention having high plasma resistance enables such a manufacturing process.

In this embodiment, etching of the gate insulating layer 18 in the gate insulating film / semiconductor film processing step 104, etching of the n ⁺ type silicon processing film 48 in the channel portion processing step, and protective film processing step ( Dry etching is used in three processes of the etching of the silicon nitride film 55 in 109 in total. At this time, when wiring, an electrode, etc. were formed by the conventional silver single body, it etched at the time of over-etching or when it became an etching mask of another film | membrane, and became defect. By the way, like this embodiment, since the wiring material of this invention containing silver and indium has the outstanding plasma resistance, it does not become a defect.

As described above, in the manufacture of a TFT array substrate, dry etching is used abundantly, and accordingly, high dry etching resistance (plasma resistance) is required as a material constituting a wiring, an electrode, or the like. The material containing indium mainly composed of the silver of the present invention has high plasma resistance, and is particularly excellent as a material for forming wirings, electrodes and the like on a TFT array substrate.

The material of the present invention is particularly used when the source wiring 14, the semiconductor layer 27, the source electrode 21 and the like are drawn and formed by a pattern forming apparatus such as an ink jet method as in the present embodiment. Valid. In this case, since the source wiring 14 or the like becomes an etching mask for the formation of the n ⁺ type silicon layer 20, it is exposed to a dry etching atmosphere for a long time from the start of etching to the end. Therefore, this process was difficult in the case of using a conventional silver single body. However, the material of the present invention makes it possible to manufacture a TFT array substrate by such a pattern forming apparatus.

As described above, the silver alloy material of the present invention is particularly suitable for a manufacturing process using a coating apparatus such as an ink jet apparatus, and is a material that is included in the fluid wiring material and is advantageously used. Moreover, as mentioned later, also in the manufacturing method performed without using a pattern forming apparatus, it is a material used advantageously similarly.

In this embodiment, it is a six-sheet mask process which performs an exposure and image development process using a photomask six times in total. In order to produce a TFT array substrate at a lower cost, a five-sheet mask process of reducing this once is also widely used. In this case, the gate insulating layer 18 and the protective layer 25 are formed by continuously etching the gate insulating film 45 and the silicon nitride film 55. However, in this case, especially, the exposed part formed in the drain electrode wiring 22 is exposed to a dry etching atmosphere for a long time, and it is necessary to withstand severe use conditions.

In order to think about this reason, the state of the board | substrate under etching is considered. First, since there is a film on the entire surface while the silicon nitride film 55 is etched, there is no problem. However, during the etching of the gate insulating film 45 subsequent to this, the exposed portion formed in the contact hole 23 of the drain electrode wiring is always directly exposed to the dry etching atmosphere from the start to the end of the etching. In the case of six masks, there was only over etching, which is a very long time and is a harsh process condition.

Therefore, in the case of such a five-sheet mask process, in particular, high plasma resistance is required for the drain electrode wiring 22. The silver alloy material of the present invention represented by silver alloy material containing silver and indium has a high plasma resistance. Since it is provided with a castle, it can be used also in such a case, and its use range is wide.

In addition, although this embodiment forms the terminal wiring 30 simultaneously with a gate wiring etc. in a six-sheet mask process, the scope of the present invention is not limited to this. In most current manufacturing methods in which a silicon nitride film, which is a gate insulating layer 18 or a protective layer 25, is formed on the entire surface of a substrate and partially removed by dry etching, a portion for removing them for electrical connection is provided. Essentially, plasma resistance against over etching is necessarily required for electrodes, wirings, and the like disposed thereunder. This invention provides the material excellent in plasma resistance, and exhibits the outstanding effect with respect to the manufacturing process of these TFT array substrates.

In this embodiment, what disperse | distributed the silver indium alloy microparticles | fine-particles which coated the organic film in the organic solvent was used for the fluidic wiring material. Silver and indium contained in the fluid wiring material at this time were formed using the indium-to-silver ratio about 10 weight% or less suitably. However, this ratio of indium to silver can be appropriately selected depending on the production process, or having appropriate plasma resistance, depending on the manufacturing process.

In addition, the form of this fluid wiring material is not limited to the form containing silver and indium as microparticles | fine-particles of a silver indium alloy. The fine particles of silver and the fine particles of indium may be prepared separately and may be dispersed in a solvent independently. Moreover, it is not necessarily limited to microparticles | fine-particles, The form which silver or indium contains in a solvent in the aspect of a metal compound may be sufficient.

In this embodiment, although the wirings, electrodes, etc. of the source wiring 14, the gate wiring 13, etc. were formed with the silver alloy material containing silver and indium, it is not limited to this, Comprising: It contains silver and zinc. A silver alloy material may be sufficient. You may form the gate wiring 13 etc. by the silver alloy material containing silver and at least 1 type of element chosen from tin, zinc, lead, bismuth, indium, and gallium. In addition to silver, aluminum and copper may be the main metals, and in addition to these elements, aluminum, copper, nickel, gold, silver, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, It may be a silver alloy material comprising an element selected from zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten and neodymium.

Here, the details of wiring formation in the gate wiring forming step 102 and the source-drain wiring forming step 106 described above will be described below.

First, the gate wiring forming step 102 will be described with reference to FIGS. 32A to 32E.

First, as shown in Fig. 32A, in the gate wiring pretreatment step 101, the ink jet head is formed in the wiring formation region of the glass substrate 12 on which the surface is subjected to a hydrophilic water (hydrophilic solution) treatment. By the first head 33a of (33), the fluid wiring material of the low resistance material for wiring parts is discharged, and the terminal wiring 30 is formed.

Subsequently, as shown in FIG. 32B, in the terminal electrode formation region on the glass substrate 12 after the terminal wiring 30 is formed, to the second head 33b of the ink jet head 33. As a result, the fluid wiring material of the plasma material for the terminal portion is discharged to form the terminal electrode 39.

Subsequently, as shown in FIG. 32 (c), after firing the terminal wiring 30 and the terminal electrode 29 formed on the glass substrate 12, the gate insulating film 45 serving as a protective film is connected to the terminal wiring ( 30 and the terminal electrode 29 are formed to cover.

Thereafter, as shown in FIG. 32 (d), in order to perform terminal processing, a resist material 100 serving as a mask is provided to open the gate insulating film 45 of the portion corresponding to the terminal electrode 29. Then, a pattern is formed by mask exposure or the like.

Finally, as shown in FIG. 32E, after etching the region of the gate insulating film 45 corresponding to the terminal electrode 29, the resist material 100 is peeled off to close the terminal portion 28. Form.

In this way, when the ink jet head 33 is provided with two heads for each function to handle two kinds of fluid wiring materials, the ink supply system 36, the control unit 37, and the ejection position Information and the like also need to be associated with this.

The terminal portion 28 thus formed is as shown in Figs. 31A and 31B. In addition, the terminal wiring 30 is in contact with the terminal electrode 29, and they are in electrical conduction.

Since the terminal wiring 30 is covered with the gate insulating layer 18, the terminal wiring 30 may be selected so as to have heat resistance and adhesion to the glass substrate during process resistance. Plasma resistance is unnecessary because it is not exposed to a dry etching atmosphere.

For example, when manufacturing the circuit board used especially for a large liquid crystal display device as an example and demonstrating, since a wiring length becomes long in a large liquid crystal display device, it is preferable to make small the electrical resistance of wiring. In this case, the terminal wiring 30 can be configured so that the content of indium to silver is 3% by weight. At this time, the electrical resistivity of this portion is about 4 mu OMEGA cm. Further, the gate wiring 13, the gate electrode 17, and the storage capacitor wiring 16 in the pixel formation region 61 also have a lower electrical resistance because of the same length as the terminal wiring 30 because the wiring length becomes longer. The content of indium with respect to silver may be 3 weight% as much as possible.

On the other hand, the terminal electrode 29 is exposed to a dry etching atmosphere by over etching in the etching step for electrical connection. Therefore, the plasma resistance can be emphasized, and it can also be comprised so that content of indium with respect to silver may be 10 weight%. This terminal electrode 29 may be much shorter than the gate wiring 13, the source wiring 14, and the terminal wiring 30 on the TFT array substrate, and the electrical resistivity may be larger than other portions.

Of course, you may comprise the terminal wiring 30 and the terminal electrode 29 so that both may have the same structure, ie, content of indium with respect to silver will be 10 weight%. However, by performing separate coating according to the performance required for the individual parts as in the present embodiment, wirings, electrodes, and the like having lower electrical resistance as a whole can be formed, so that larger circuit boards and larger displays can be formed. There is an advantage that can realize the device.

Here, the ink jet head 33 uses the first head 33a and the second head 33b to discharge two types of fluidic wiring materials having different indium contents to silver, thereby providing terminal wiring and The terminal electrode is formed. Specifically, in the region for forming the terminal wiring 30, when the terminal wiring 30 was used, a fluid wiring material having a content of indium with respect to silver of 3% by weight was discharged. On the other hand, in the area | region for forming the terminal electrode 29, when it became the terminal electrode 29, the fluidic wiring material which content of indium with respect to silver became 10 weight% was discharged.

On the other hand, in the region for forming the gate wiring 13, the gate electrode 17, and the storage capacitor wiring 16 in the pixel formation region 61, the same fluidic wiring material as that of the terminal wiring 30 was discharged. After discharge, baking was carried out at 300 ° C. for 1 hour to obtain predetermined terminal wirings 30, terminal electrodes 29, and the like. Thus, by using the flexible wiring material whose content of indium is 3 weight% in the wiring part of the pixel formation area 61, wiring of further low resistance is possible.

In the present embodiment, a pattern forming apparatus such as an ink jet method can apply a separate coating on the substrate surface, and wirings formed at the same process require different plasma resistance or conductivity at each part. It is important to have a good combination of the indium content of the material of the present invention and the relationship between conductivity and process resistance. This makes it possible to manufacture a large-sized TFT array substrate which is easy to manufacture and has good electrical characteristics.

In addition, in this embodiment, although the terminal wiring 30 and the terminal electrode 29 have the boundary which the material from which indium content differs, it is not limited to this. The indium content may change slowly near the boundary. As the formation method, fluidized wiring materials may be mixed with each other naturally, and may be intentionally mixed, such as discharging two types alternately.

Of course, it is an important point of this embodiment to provide wiring, an electrode, etc. which increased the indium content in the part which is needed as the TFT array substrate 11 in the part exposed to a dry etching atmosphere during a manufacturing process.

Thus, the silver alloy material of this invention respond | corresponds to many manufacturing processes by performing separate coating even when content of indium with respect to silver is comparatively low like 1 weight% or 3 weight%, for example. It can be suitably used as a material which constitutes wiring and an electrode of (13) etc., especially low electrical resistance.

Moreover, in this embodiment, although the gate wiring 13 etc. were formed with the silver alloy material containing silver and indium, it is not limited to this, The silver alloy material containing silver and zinc may be sufficient. You may form the gate wiring 13 etc. by the silver alloy material containing silver and at least 1 type of element chosen from tin, zinc, lead, bismuth, indium, and gallium. Moreover, not only silver but aluminum and copper may be used as a main metal, and in addition to these elements, at least, aluminum, copper, nickel, gold, silver, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, A silver alloy material characterized by containing an element selected from titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten and neodymium may be used.

In addition, you may use according to the place so that a structure may differ from each other on TFT array substrate 11, such as silver and indium, silver, and zinc.

Next, the detail of the source-drain wiring formation process 106 is demonstrated below. Herein, the content of indium to silver is 3% by weight in the case of the source electrode 21 and the source wiring 14, and 10% by weight in the case of the drain electrode wiring 22.

Further, in the drain electrode wiring 22, the content of indium with respect to silver may be applied by fractionation so as to be 3% by weight or 10% by weight, and the plasma resistance may be improved in the vicinity of the contact hole 23. In addition, such an application | coating may be performed at arbitrary places on the TFT array substrate of this embodiment.

The wiring material of the source / drain wiring is not limited to a material composed of silver and indium, and may be a silver alloy material containing silver and zinc. You may form the source wiring 14 etc. by the silver alloy material containing silver and at least 1 type of element chosen from tin, zinc, lead, bismuth, indium, and gallium. Moreover, not only silver but aluminum and copper may be a main metal, and in addition to these elements, at least, aluminum, copper, nickel, gold, silver, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, A silver alloy material characterized by including an element selected from zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and neodymium.

Moreover, you may use according to the place differently so that a structure may differ from each other on TFT array substrates, such as silver and indium, silver, and zinc.

In the case of manufacturing the TFT array substrate 11, as described above, in both the gate wiring forming step 102 and the source / drain wiring forming step 106, separate coating may be performed, Only one step may be subjected to separate coating.

Here, when the wiring material such as the wiring portion or the terminal portion is applied in accordance with the application, the portions where the respective materials are in contact will be described.

For example, as shown in Fig. 33A, after applying the terminal wiring 30 as the wiring portion from the material M, as shown in Fig. 33B, the terminal electrode forming the terminal portion ( The material N is apply | coated to the place corresponded to 29). At this time, the material M and the material N are in contact with each other or in a state in which they are mixed with each other at the boundary portion P. FIG.

34 (a) to 34 (c) show a state that is expected to occur at the boundary when different materials M and N are in contact with each other by ink jet application.

Fig. 34 (a) shows a case where the materials M and N are mixed with each other in the liquid at the boundary, and because they are mixed with each other, a state different from the material M and the material N, i.e., a state in which an intermediate state (intermediate region) is generated, is shown. .

* This state changes depending on the mixing ratio of the material M and the material N. To what extent they mix with each other to form an intermediate state is also related to how long the solvent contained after application remains. That is, when a solvent dries, it does not arise that they mix with each other by fluidity of a liquid. However, although the intermediate states of materials M and N are produced by melting of the particulate metal during firing, the region is considered to be very narrow compared with the intermediate states produced by mixing with each other in the liquid state. Here, attention is paid to mixing with each other in the liquid state, and the boundary between the materials M and N becomes very unclear at this time.

FIG. 34B shows a state in which the materials M and N are not mixed in the liquid state in a state in which the material N is applied after the solvent powder of the material M applied first is roughly dried.

In this state, since the materials M and N are not mixed, the boundary between both exists relatively clearly. However, at the time of baking, the intermediate state by the mutual melting of the microparticles | fine-particles contained in material M, N is created.

FIG. 34C shows the region of the materials M and N in the intermediate case of FIGS. 34A and 34B with the solvent powder of the material N applied from the back, whereby the material M becomes liquid again. This obscure state is shown. At this time, since the areas mixed with each other are narrow as compared with Fig. 34A, a virtual boundary can be set at the intermediate distance.

In this embodiment, it is important that the material M and N are electrically connected after baking. 34 (a) to 34 (c) are electrically connected to each other, and in the present invention, there is no problem in any state. However, as will be described later, in the case of resistance fabrication by mixing the materials M and N and actively using the intermediate state, the state of FIG. 34 (a) is preferable, and the end of the resistance is shown in FIG. 34 (b) or It is preferable that it is a state of FIG. 34 (c). In addition, only the boundary between the material M and the material N is described here, and since the flatness of the surface during the coating process is not relevant to this description, Fig. 34 is described in a flat state.

By using the present invention, it is possible to adjust the resistance formation and the resistance of the wiring by appropriately combining the wiring material having a low resistance with the wiring material having a low resistance and the alloy. An example thereof will be described below.

In the schematic diagram of the gate wiring in FIG. 35, as the terminal wiring for connecting the terminal electrode and the gate wiring of the driver IC, a short distance between the terminal and the gate wiring in order to match the wiring length, that is, at the center of the driver IC. In the places to be connected, the wiring shape is zigzag-shaped, and in a place where the distance between the driver terminal and the gate wiring is long, that is, at the point connected to the end of the driver IC, it is connected as a straight line.

Here, a zigzag pattern having a length D as shown in Fig. 36A and one wiring length is assumed. In FIG. 36A, since the folding is four times, the total wiring length is approximately 8L. Therefore, compared with the case where distance D is connected in a straight line, resistance is about 8 L / D times.

For example, when D = 600 µm and L = 150 µm, 8 L / D = 2, so that the resistivity of the wiring can be doubled unless the wiring width and film thickness are changed. To adjust the wiring resistance,

(1) formed of materials of desired resistivity

(2) Adjusted by combining materials with different specific resistances

(3) Change the wiring shape film thickness

There can be three kinds of methods.

In the method of (1), as shown in FIGS. 33A and 33B, a material having a low specific resistance, a material M and a material having a high specific resistance, and a material N of the containing metal part are prepared and wired. The resistance can be formed by forming the silver material M and using the material N at the place where the resistance is formed. When the method is applied in the case of D = 600 µm and L = 150 µm in Fig. 36A, the specific resistance when the ratio of indium to silver is 5% by weight is about 6.1 µ? Example 5), and the specific resistance of the indium to silver ratio of 10% by weight is 12.3 μΩ · cm (Example 6), where the material M is an alloy having a ratio of indium to silver of 5% by weight, material N If the ratio of indium to silver is 10% by weight of alloy, if the film thickness and line width are not changed, as shown in Fig. 36B, a resistance can be formed in a straight line without using a zigzag pattern. Will be.

The method of adjusting the intermediate resistance in the material M and the material N of (2) is, for example, as shown in Figs. 37A and 37B, among the ink jet heads 33, which is described above. After the material M is intermittently discharged by the first head 33a, the material N is discharged into the gap by the next second head 33b to mix the material M and the material N to form the material M and the material N. It is possible to obtain a wiring (intermediate) having a resistance value to be made.

At this time, by changing the discharge interval and the discharge ratio between the material M and the material N, the resistance value can adjust the mixing ratio of the material M and the material N.

Below, the example other than forming the intermediate body mentioned above is demonstrated.

38 (a) and 38 (b) and 39 (a) and 39 (b), the discharge ratios of the materials M are different, and thus, FIGS. 38 (a) and 38 (b). Shows an example in which material M is discharged at a rate of three drops, and FIGS. 39A and 39B show an example in which material M is discharged at a rate of two times in three drops. If the same film thickness, the same wiring width, the discharge amount of one drop, and the discharge interval are the same, and are the same as in Fig. 34B, the resistance values are higher in Figs. 38A and 38B. In this manner, the resistance value can be adjusted by the ratio of the number of ejections of the material M and the material N. Of course, the film thickness, line width, discharge amount, and discharge interval can also be changed and adjusted appropriately.

When the state inside the cross section is shown in Fig. 34A, the resistance value is not necessarily an intermediate value proportional to the mixing ratio. In the case of alloys of metals, when different materials are mixed, they sometimes become higher than the resistance values of both. In addition, when a metal becomes the mixing ratio which forms a compound, resistance value may become low. This is because the dissimilar materials are mixed with each other, so that the scattering probability of the conduction electrons contributing to the electrical conduction becomes high when they are simply mixed, and when the compound becomes a compound, the probability is low because it takes a determined crystal structure. . Also in this embodiment, since the fine particles fuse by firing after mixing, a phenomenon similar to that of the metal alloy is considered to occur. In this way, when the resistance value does not become an average value, it is necessary to examine the resistance characteristics in advance.

On the other hand, when the discharged droplets are overlapped after drying, that is, at the boundary as shown in Figs. 34B and 34C, because the materials M and N are in contact with each other, they are not mixed with each other. , The resistance value is close to the average value of both. Therefore, in this case, it can adjust to the intermediate resistance value of material M and material N with ratio of discharge amount. Thus, it is also possible to adjust resistance value in the state after application | coating.

However, in FIG. 34A, since the boundary between the material M and the material N is not clear, the wiring length as the resistance is not clear, and the resistance value is changed, so that the end portion of the portion that becomes the resistance is clear. It is more preferable to dry, as shown in FIG.34 (b) so that a boundary may arise.

38 (b) and 39 (b) show cross-sectional views of FIGS. 38 (a) and 39 (a), respectively. In order to clarify the length of the resistor, the ends of FIG. As shown in b), it is made to dry enough so that a boundary becomes clear, and it discharges between materials M and N, and mixes in a liquid state in the resistance part, as shown to Fig.34 (a). As a result, the boundary between the materials M and N is illustrated as an example.

The case where wiring width and film thickness of (3) are changed is demonstrated below, referring FIG. 40 (a)-FIG. 40 (c).

40A illustrates a case where the discharge interval is narrowed, and in this case, the film thickness is increased unless the concentration of the coating material and the wiring width change.

On the other hand, FIG. 40 (b) shows an example in which the discharge interval is widened, and the place shown by the broken line ellipse is the position where the droplets hit. In FIG. 40, the case where the material N which reached the two places of the area | region where the resistance formation position was hydrophilized (liquidized) by the hydrophilic (hydrophilic liquid) process previously spread along the hydrophilic (liquid) pattern is shown, FIG. 40 The film thickness is thin as compared with the case where the discharge interval of (a) is filled. In this way, it is possible to make the resistance higher by widening the discharge interval and making the film thickness thin.

In this way, it is possible to make a material having different resistance values by appropriately combining the methods (1) to (3).

This is effective when forming IC monolithically on glass. In the IC process of processing a Si wafer, an appropriate resistance is made by ion implantation. In this example, in a panel made from a large substrate such as a panel of a liquid crystal display device, the method of ion implantation is performed. In other words, the size of the device increases, which is not realistic in terms of the device itself or the price of the device. Thus, this method is extremely effective for forming a circuit board which requires a resistance on the substrate as described above.

As the material used as the resistor, as described in the present embodiment, it is also possible to use a material in which the ratio of indium to silver is changed. As a material having a higher resistance, a material having a higher specific resistance in silver, for example, cobalt , Alloys such as nickel and high melting point materials such as tantalum, molybdenum, tungsten, niobium, or the like may be used, or may be used as a material other than an alloy with silver.

In addition, as shown in FIG. 40 (c), when the wiring formation position is hydrophilized (liquid) using the hydrophilic (hydrophilic) solution, it is also possible to narrow the wiring width. In this case, if the film thickness is the same, the resistance becomes high. In this way, it is possible to control the resistance in accordance with the wiring width.

38 (a), 39 (a), and 40 (a) used herein, the part of the resistor is clearly illustrated by clearly showing the droplet shape immediately after the impact for clarity of explanation. Embodiment is not limited to these figures. When it hits the area | region after hydrophilic water (hydrophilic liquid) process, since the droplet shape after impacting spreads over a hydrophilic area (hydrophilic area), it may also arise that the shape immediately after impacting does not remain as shown in a figure. In particular, if it is in the droplet state even after impacting, as shown in FIGS. 38B and 39B, the materials M and N may be mixed with each other to be integrated.

Moreover, in this embodiment, the pattern forming apparatus which discharges fluid droplets similar to the inkjet system was used. However, the silver alloy material of the present invention can be advantageously used similarly without using such a pattern forming apparatus. In this case, the TFT array substrate is manufactured by the most common method using the conventional sputtering method or vapor deposition method and photolithography in a corresponding process. However, wirings, electrodes, and the like formed according to the silver alloy composition of the present invention are obtained using a sputtering target, a vaporization evaporation source, and the like, instead of the fluidic wiring material. In this case, the silver alloy material of the present invention is advantageously used as a material having excellent process resistance such as heat resistance, adhesion, plasma resistance, and low electrical resistance.

In addition, the silver alloy material of the present invention can be advantageously used as one layer of a multilayer wiring structure formed by superposing two or more layers of materials. For example, even if calcined at 300 ° C., the surface smoothness is not lost as in the case of silver alone, and in particular, indium is contained, and when the content thereof is relatively large, for example, 10% by weight relative to silver, a sufficient plasma resistance is obtained. It can be used effectively as a protective metal layer which has the property and protects the wiring of the lower layer. In addition, it can be used as all or part of the source electrode 21 and the drain electrode wiring 22 for directly contacting the semiconductor layer 27 in Embodiment 1 to obtain an electrical connection, and similarly excellent heat resistance, It exhibits an adhesive force and is advantageously used for the manufacturing process of a TFT array substrate.

Alternatively, the silver alloy material of the present invention may be used for a light reflective electrode on a TFT array substrate used for a reflective TFT liquid crystal display device or the like. In this case, due to the excellent heat resistance of the silver alloy material of the present invention, even if it is heat-fired at 300 ° C, for example, the surface smoothness is not lost as in the case of silver alone. Therefore, light scattering other than the design does not occur, and sufficient light reflectance can be maintained as a light reflective electrode, and the characteristics as a TFT array substrate can be fully exhibited.

In addition, the silver alloy material of this invention, the structure of wiring, and the wiring formation method are used also as a bus electrode and the data electrode on the glass substrate which comprises a PDP (plasma display panel). These electrodes are arrange | positioned at the front glass substrate or the back glass substrate in order to drive a PDP, and were conventionally the structure of silver, chromium / copper / chromium, and aluminum / chromium. It was not possible to use it without the structure which sandwiches a chromium layer between glass substrates, etc. from the improvement of the adhesive force of copper and aluminum with respect to the board | substrate, and the countermeasure against the difference of expansion coefficient. On the other hand, the conventional silver had a problem in heat resistance, growth of crystal grains occurred by high temperature baking, and it was a material which is difficult to use.

On the other hand, since the silver alloy material of this invention has the outstanding heat resistance and the adhesive force with respect to a glass substrate, it is advantageously used as a bus electrode and a data electrode instead of these materials, such as conventional silver.

The silver alloy material of this invention, the structure of wiring, and the wiring formation method can also be used also about the display apparatus using EL (electroluminescence). In comparison with the liquid crystal display device, the EL display device sometimes controls the gradation of the light emission luminance by the amount of current. In such a case, a low-resistance material is required for the current supply line for supplying the current to the light emitting element in which the pixel is formed. This is because power is consumed by the wiring resistance, resulting in poor luminous efficiency, heat generation of the display device, and unevenness in the display surface.

In addition, the circuit board for driving the EL element is often formed of a circuit using a TFT array, and may be produced through the same steps as those shown in this embodiment. Therefore, it is possible to apply the contents described in this embodiment to a display device using EL. In particular, a wiring material which becomes a low resistance selectively to the wiring which becomes a current supply line and the current supply line from an external circuit to a drive driver, ie, the silver alloy material whose content of indium with respect to silver is 3 weight%, is used. The material whose content of indium with respect to silver is 10 weight% can be used.

Moreover, the silver alloy material, wiring structure, and wiring formation method of this invention can also be used as a wiring material of a flexible board | substrate or a glass epoxy board | substrate. The connection terminal in these board | substrates increases the content of indium with respect to silver, and it is set as the structure centered on oxidation-resistant, and the internal wiring part uses the content of indium with respect to silver, and uses it as a low resistance wiring. Can be.

Moreover, in the said silver alloy material, especially when the content rate of indium with respect to silver is 0.5 weight% or less, an electrical resistivity is 2.7 microohm cm or less, and the formation of low electrical resistance wiring which cannot be achieved with conventional aluminum wiring is possible. It is beneficial. However, since the content of indium is low, the plasma resistance is not sufficient, and it is generally necessary to laminate another metal film or the like. Regarding the adhesion force to the substrate, since the content of indium is low, it is not sufficient, so a basic treatment or the like may be necessary. Therefore, even if it is the silver alloy material whose content of indium with respect to silver is 0.5 weight% or less, it can be used as a main line of wiring of a circuit board, if basic processing is performed.

Below, the manufacturing method of the circuit board at the time of using as a wiring material the silver alloy material whose content of indium with respect to silver is 0.5 weight% or less is demonstrated.

In the gate wiring forming step 102 shown in FIG. 6, a pattern forming apparatus typified by an ink jet method was used, and the differential coating of wiring materials having different configurations on the TFT array substrate 71 was performed. On the other hand, in the said Embodiment 3, in the source-drain wiring formation process 106, the separate application | coating of the wiring material from which a structure differs was performed.

Here, in the gate wiring forming step 102, the sputtering method is used to form wirings, and the wirings and the like are laminated with the silver alloy material of the present invention and titanium.

41 (a) and 41 (b), 42 (a) and 42 (b) show a state in which the gate wiring forming step 102 is completed in the present embodiment. to be. 41 (a) and 42 (a) are plan views in the pixel formation region 61 and the terminal portion formation region 62 on the glass substrate 12, respectively. 41 (b) and 42 (b) are cross-sectional views taken along the line M-M and cross-sections taken on the line N-N in FIGS. 41 (a) and 42 (a), respectively.

In these figures, the gate wiring 80, the gate electrode 81, the storage capacitor line 82, and the terminal wiring 83 have the same laminated structure and consist of two layers. Each layer 80a, 81a, 82a, 83a of the side close to the glass substrate 12 consists of the silver alloy of this invention, and content of indium with respect to silver is 0.2 weight%. Each layer 80b, 81b, 82b, and 83b on the upper layer side thereof is made of titanium. The film thicknesses of the reference numerals 80a, 81a, 82a, 83a, 80b, 81b, 82b, and 83b were all 0.2 µm.

Here, since each layer 80a, 81a, 82a, and 83a of the side close to the glass substrate 12 is formed of the alloy which consists of silver and indium, it has heat resistance, and baking about 300 degreeC is performed at a later process. Even if the gate wiring 80 or the like is not adversely affected. In the case where these were formed of conventional silver single members, since there was no heat resistance, remarkable surface irregularities occurred, and leak defects with the upper layer occurred.

If the content of indium is a silver alloy of 0.5% by weight or less, as described above, the electrical resistivity is 2.7 µΩcm or less, and the formation of wiring of low electrical resistance, which is not feasible with aluminum, is possible. In this example, the electrical resistivity is very low, about 2.3 mu OMEGA cm. Therefore, when low electrical resistance of wiring is particularly desired, for example, in a liquid crystal display device such as for a liquid crystal TV, the silver alloy material of the present invention is a useful material.

In this description, a method of forming the gate wiring 80 or the like will be described. In the gate wiring forming step 102, since the pattern forming apparatus represented by the ink jet method is not used, the process corresponding to the gate wiring pretreatment step 101 has not been performed.

First, the silver alloy film containing indium 0.2weight% with respect to silver was formed into a film of 0.2 micrometer on the glass substrate 12 by the sputtering method. At this time, as a target for sputter | spatter, the alloy target which made indium into the solid solution was used. Next, titanium was continuously formed into a film by the sputtering method in vacuum. The film thus obtained was processed by photolithography to obtain gate wirings shown in FIGS. 41A and 41B, 42A, and 42B. The dry etching method was used for the etching at this time.

The terminal wiring 83 or the like requires plasma resistance in consideration of the subsequent steps, but in the present description, it is obtained by titanium on the upper layer side.

Thus, this silver alloy material may be used as one layer of a multilayer wiring structure, and by making indium 0.5 weight% or less with respect to silver, the wiring of the low electrical resistance which cannot be realized with conventional aluminum is implement | achieved.

Moreover, in the formation method, although the silver alloy film of this invention was formed into a film directly on the glass substrate 12, when the adhesive force with respect to a board | substrate is not fully acquired, even if the intermediate | middle layer which consists of metals etc. is provided in the middle of both. The adhesion may be obtained by surface-treating the glass substrate with plasma, chemicals, or the like.

In the present invention, the materials of the upper layers 80b, 81b, 82b, and 83b are not limited to titanium, but include chromium, molybdenum, tantalum, tungsten, or nitrogen and oxygen in these materials, or ITO. Metal oxides, such as (indium tin oxide), may be sufficient. In the formation of the gate wiring 80 or the like, as described above, a fluid wiring material may be applied and laminated, or may be formed by deposition and processing by a vapor deposition method using an evaporation source made of silver and indium.

In the present description, in the gate wiring forming step 102, the wiring is formed by a film made of the silver alloy and titanium of the present invention, but as another embodiment of the present invention, in the source / drain wiring forming step 106. Similarly, you may form the wiring which consists of laminated | multilayer film. Even in this case, since the alloy made of silver and indium has heat resistance, no adverse effect is seen even if firing is performed in a later step.

Also in this case, by making indium 0.5 weight% or less with respect to silver, the wiring of the low electrical resistance which cannot be realized with conventional aluminum can be implement | achieved.

In addition, by including indium with respect to silver, a film having a higher reflectance than aluminum can be formed when fired. In particular, when the wiring also serves as a reflecting plate or a reflecting electrode, the wiring may be formed of a silver alloy material having indium of 0.5% by weight or less with respect to silver.

As mentioned above, the silver alloy material of this invention is a material which comprises the wiring and / or electrode formed on an insulated substrate, and has silver as a main component, and is selected from tin, zinc, lead, bismuth, indium, and gallium. It is characterized by including the above element.

According to the material of the said structure, the wiring and / or the electrode which are low electrical resistance, and have high process resistance, such as heat resistance, adhesion to a glass substrate, and plasma resistance, can be formed.

In addition, the said element may contain at least zinc.

In this case, when wiring, an electrode, or the like is formed of a silver alloy material containing silver as a main component and containing at least zinc, heat resistance, adhesion, chlorine gas, or oxygen gas are introduced without largely losing low electrical resistance. The plasma resistance can be improved under the conditions described above.

In addition, the said element may contain at least indium.

In this case, if the wiring, the electrode, or the like is formed of a silver alloy material mainly composed of silver and containing at least indium, significantly improving heat resistance, adhesion, and characteristic plasma resistance without largely losing low electrical resistance. Can be planned.

Moreover, when an appropriate amount of indium is added to silver to form a film, a silver alloy film that maintains a high visible light reflectance can be obtained even at 200 ° C or 300 ° C firing. Such a silver alloy film has a high reflectance even when compared with the case where a conventional aluminum light reflection film is used. Therefore, when used for example, a light reflecting electrode of a reflective liquid crystal display device, brighter display is possible.

In addition, the alloy material of silver and indium can cover a wide range in heat resistance, adhesive force, plasma resistance, high visible light reflectance, etc., if the content of silver of indium is adjusted.

As for content (indium / silver (weight%)) of indium, 0.5 to 28 weight% is preferable. When the content of indium is made low, the plasma resistance is low, but the resistance can be reduced. However, when the content of indium is less than 0.5% by weight, there arises a problem that the plasma resistance becomes low. In addition, if the content of indium is increased, the resistance value is increased, but the plasma resistance is high. However, when the content of indium is more than 28% by weight, there arises a problem that solid solution formation with silver cannot be performed. Thus, only by adjusting the content of indium with respect to silver appropriately, even if it is a site | part to which different characteristics, such as a wiring part and a terminal part on a circuit board, differ, it becomes possible to change a characteristic easily.

The composition range of the said silver and the said element may be set so that the electrical resistivity as a silver alloy may be set to 10 microohm-cm or less.

In this case, in the conventional aluminum and aluminum alloy wiring technology, the electrical resistivity is in the range of approximately 4 mu OMEGA cm to 10 mu OMEGA cm. Therefore, the silver alloy material of this invention can acquire predetermined electric characteristic, and can introduce | transduce it with few changes of the conventional wiring design.

Regarding the silver alloy material, aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, neodymium At least 1 type of element among the elements chosen from may be contained.

Since each element mentioned above is useful as an auxiliary material for further improving heat resistance, adhesive force, and plasma resistance with respect to a silver alloy material, at least 1 type of these elements is included, and therefore, heat resistance, adhesive force, Plasma resistance can be further improved.

The circuit board of this invention has a wiring and / or an electrode comprised from the silver alloy material of the said structure, It is characterized by the above-mentioned.

Since the said circuit board can be set as the structure which has the wiring of a low electrical resistance, manufacture of a large circuit board equivalent to the case of the conventional aluminum and aluminum alloy wiring technology is possible.

The electronic device of the present invention is characterized by using the circuit board.

Examples of the electronic device include a display device and a liquid crystal display device.

In the case of a display device, especially a large circuit board is widely used, the circuit board of the low electrical resistance of this invention is used especially suitably.

Moreover, in the manufacture of the TFT array substrate which is the circuit board which comprises a liquid crystal display device, since the dry etching method is frequently used, heat resistance, adhesive force, and plasma resistance are calculated | required as a material of a wiring and / or an electrode. For this reason, using the circuit board in which wiring and the electrode were formed using the silver alloy material of this invention is very useful in a liquid crystal display device.

The target for sputtering of this invention consists of a silver alloy material which mainly contains silver and contains at least 1 type of element chosen from tin, zinc, lead, bismuth, indium, and gallium.

When such a silver alloy material is used as a target for sputter | spatter, the wiring with high process tolerance is obtained, and it becomes possible to manufacture the circuit board, display apparatus, etc. of this invention with good productivity.

The evaporation source of the present invention is characterized by consisting of a silver alloy material mainly composed of silver and containing at least one element selected from tin, zinc, lead, bismuth, indium and gallium.

When such a silver alloy material is used as an evaporation source, the wiring with high process tolerance is obtained, and it becomes possible to manufacture the circuit board, display apparatus, etc. of this invention with good productivity.

The flowable metal-containing material of the present invention is characterized by including a silver alloy material containing at least one element selected from among silver, tin, zinc, lead, bismuth, indium, and gallium.

By using the fluid metal-containing material having such a configuration, a wiring having high process resistance can be obtained, and the circuit board, the display device and the like of the present invention can be formed or manufactured with good productivity.

In addition, since the silver alloy of this invention can be produced in the primary solid solution formation area which mainly consists of silver, in that case, it is easy to fluidize (ink) like silver, and is used as a material of the wiring formation process using an inkjet head. Corresponds.

The silver alloy material of this invention is a material which comprises the wiring and / or electrode formed on an insulating substrate, or a light reflection film, Comprising: Silver is a main component, It contains at least indium, It is characterized by the above-mentioned.

It is preferable that content of indium with respect to silver is 0.5 weight% or less.

In this case, when the content of indium is less than 0.5% by weight, there is a problem that the plasma resistance becomes low. However, in the silver alloy material, when the indium content is 0.5% by weight or less, even after firing at 200 ° C, the visible light region In almost all, a visible light reflectance higher than that of aluminum is obtained.

In addition, in the case where the content ratio of indium to silver is 0.5% by weight or less, it is possible to form low electrical resistance wiring which cannot be achieved with conventional aluminum wiring. When low electrical resistance of wiring is particularly desired, for example, when it is used in a liquid crystal display device used for a liquid crystal TV or the like, it is preferable to create a circuit board using the silver alloy material of the present invention.

Moreover, it is preferable that content of indium with respect to silver is 0.2 weight% or less.

In this case, in the silver alloy material, when the indium content is 0.2% by weight or less, even after 300 ° C firing, a visible light reflectance higher than that of aluminum is obtained in almost the entire visible light region.

For this reason, it can use for a light reflective electrode (electrode structure which combined an electrode and a reflection film) use, and it becomes possible to display brighter than the case of the conventional aluminum.

The manufacturing method of the circuit board of this invention is characterized by forming a wiring and / or an electrode on an insulating substrate using the said sputtering target or the said evaporation source.

In such a manufacturing method, since the wiring with high process resistance can be formed on the circuit board, the circuit board can be manufactured with good productivity.

You may form a wiring and / or an electrode on an insulating substrate using the said fluid metal containing material.

In the manufacturing method using such a fluid metal-containing material, since the wiring having high process resistance can be formed on the circuit board, it is possible to manufacture the circuit board with good productivity.

Here, as a specific example, a circuit board is a TFT array board used for a liquid crystal display device, an electrode board used for a PDP (plasma display panel), a printed wiring board, a flexible wiring board, etc.

As a specific example of the display apparatus and image input apparatus produced using these circuit boards, display apparatuses, such as a liquid crystal display device, a plasma display panel (PDP), an organic electroluminescent (EL) panel, an inorganic EL panel, a fingerprint, etc. And a two-dimensional image input device represented by a sensor, an X-ray imaging device, or the like.

The insulating substrate used in carrying out the present invention is an insulating substrate such as an alkali glass substrate, an alkali-free glass substrate, a plastic substrate, or the like, for example, a metal substrate coated with an insulating layer on a surface side for forming a wiring or the like. In addition, the board | substrate used for the use similar to an insulating board | substrate is included.

 The circuit board of the invention is characterized in that, in a circuit board having wirings formed on the substrate, characteristics of at least two sites on the same wiring are different from each other.

Here, the same wiring is a shape continuous wiring. In the circuit on a board | substrate, a circuit board | substrate is formed by gathering a plurality of such wirings, and it means one unit of these some wirings.

In order to make the characteristic of one site | part on the same wiring different from the characteristic of another site | part, it can implement | achieve by making the composition ratio of the material of each site | part different, respectively. Moreover, it can also implement | achieve by making each the structure material of each site | part different.

For example, in a TFT array substrate used for a liquid crystal display device as a circuit board, necessary characteristics are different from the wiring portion and the terminal portion on the same wiring. Although the wiring portion needs to be reduced in resistance, since a protective film is formed, it does not need much plasma resistance. On the other hand, the terminal portion also needs to be reduced in resistance, but is not protected by the protective film due to connection with a driver or the like, so that process resistance (particularly, plasma resistance) is required.

Therefore, the wiring of the wiring portion is made to have a characteristic of lowering the resistance, and the wiring of the terminal portion is made of a characteristic of making the plasma resistance important, so that the composition ratio of the wiring material is changed or the constituent material of the wiring is changed. Just do it.

In addition, it is preferable that the same wiring is formed in a single layer.

In this case, the thickness of the circuit board can be reduced, and the step difference with other wirings formed on the wiring can be reduced, so that disconnection of the other wiring due to the step can be prevented, resulting in a higher yield of the circuit board. Improvement can be aimed at.

In addition, the same wiring may be formed in a multilayer.

For example, when the adhesiveness between a wiring material and a board | substrate is bad, even if it is the same wiring which formed the layer which has good adhesiveness with a board | substrate between a board | substrate and a wiring material, and apply | coated a wiring material on it, and layered two layers. do.

Moreover, it is preferable to form the said wiring by the fluid material containing a conductor material.

In addition, since the wiring can be easily formed without laminating other films, it is possible to easily reduce the number of manufacturing steps and the manufacturing cost.

Each of the liquid materials containing the conductor material used for the sites having different characteristics may include a solvent and an organic substance of the same system.

In this case, even if the wiring materials have different characteristics, if the solvents are the same system, the familiarity of the liquids is good, the aggregation is difficult, and the separation is difficult, so that the wiring can be formed efficiently.

In addition, the said wiring may be formed with the metal which made any one of silver, aluminum, and copper the main material.

In this case, since the wiring is formed of a metal containing either silver, aluminum, or copper as a main material having a relatively low resistance value, the overall resistance of the wiring can be reduced. Here, silver which is a main material of wiring can adjust surface smoothness, plasma resistance, and adhesiveness with components other than aluminum and copper.

As such a component, at least aluminum, indium, tin, bismuth, gallium, lead, copper, gold, silver, cobalt, nickel, palladium, platinum, rhodium, vanadium, titanium, zirconium, niobium, tantalum, tungsten, hafnium, osmium, iridium It is preferable that it is at least 1 type of metal chosen from.

In addition, the inventors of the present application or the like have a silver material as a main component, and in the case where a wiring or an electrode is formed on an insulating substrate using an alloy containing indium as a material, the wiring is formed on the insulating substrate using a single silver material. Or compared with the case where an electrode was formed, it discovered that the adhesive force of the wiring and the electrode with respect to an insulating substrate improves, and the heat resistance and the plasma resistance of the wiring and the electrode improved. In addition, it was found that similar effects can be obtained even in the case of an alloy in which tin, zinc, lead, bismuth, and gallium are added to silver as well as the above indium.

Therefore, it is preferable to use such a silver alloy material for the said wiring material.

In particular, it is preferable to use silver indium alloy as a wiring material.

In this case, silver indium alloy material can cover a wide range in surface smoothness, adhesive force, plasma resistance, etc., if the content of silver of indium is adjusted.

As for content (indium / silver (weight%)) of indium, 0.5 to 28 weight% is preferable. When the content of indium is made low, the plasma resistance is low, but the resistance can be reduced. However, when content of indium becomes less than 0.5 weight%, the problem that plasma resistance falls will arise. In addition, if the content of indium is increased, the resistance value is increased, but the plasma resistance is high. However, when the content of indium is more than 28% by weight, there arises a problem that solid solution formation with silver cannot be performed. Thus, only by adjusting the content of indium with respect to silver appropriately, even if it is a site | part to which different characteristics, such as a wiring part, a terminal part, etc. on a wiring, it becomes possible to change a characteristic easily.

In addition, when the wiring material is applied by the ink jet method, wiring materials having different indium contents can be easily distinguished and used, so that wirings having different characteristics can be easily formed according to portions.

Further, if the circuit board having the above-described configuration is applied to a TFT array substrate requiring plasma resistance at the time of channel processing and terminal processing, low resistance at the wiring portion, and surface smoothness at the gate electrode portion, It is possible to improve the yield and reduce the manufacturing cost.

Moreover, when the circuit board of the present invention is applied to the TFT array substrate as described above, there is an advantage such as yield improvement as described above, so it is also suitable for display devices such as other electronic devices, liquid crystal display devices, and plasma display devices. Available.

Specific embodiments or examples made in the detailed description of the invention are intended to clarify the technical contents of the present invention to the last, and are not to be construed as limited only to such specific embodiments. It can change and implement in various ways within the scope of the following patent claims.

According to the present invention, while providing a silver alloy material capable of realizing a material having heat resistance, strong adhesion to a glass substrate, high plasma resistance, and good light reflectivity, the multilayer of the thin film is prevented, A circuit board, a manufacturing method thereof, and an electronic device capable of suppressing an increase in the number of manufacturing steps and an increase in cost of a circuit board can be provided.

Claims (15)

In a circuit board having wiring formed on a substrate, Circuit boards in which the characteristics of at least two sites on the same wiring are different from each other. In a circuit board having wiring formed on a substrate, Circuit boards in which the composition ratios of at least two sites on the same wiring are different from each other. In a circuit board having wiring formed on a substrate, Circuit boards in which the constituent materials of at least two sites on the same wiring are different from each other. The method according to any one of claims 1 to 3, A circuit board in which the same wiring is formed in a single layer. The method according to any one of claims 1 to 3, The circuit board with the same wiring formed in multiple layers. The method according to any one of claims 1 to 3, The said wiring is formed from the metal which made any one of silver, aluminum, and copper the main material. The method of claim 6, The wiring includes at least aluminum, indium, tin, bismuth, gallium, lead, copper, gold, silver, cobalt, nickel, palladium, platinum, rhodium, vanadium, titanium, zirconium, niobium, tantalum, tungsten and hafnium. And a circuit board formed of an alloy containing at least one metal selected from osmium and iridium. The method of claim 7, wherein The circuit board is formed of a silver indium alloy containing indium as a main material of silver. The method of claim 8, The circuit board whose content of indium with respect to silver is 0.5 weight% or more and 28 weight% or less. The method according to any one of claims 1 to 3, The circuit board is formed of a fluid material containing a conductor material. The method of claim 10, The circuit board which contains the solvent and organic substance of the same system in each fluidic material containing the conductor material used for the site | parts from which the said characteristic differs. In the circuit board which has the wiring formed on the board | substrate, the said wiring from which the characteristic of the at least 2 site | parts on the same wiring respectively differs as a manufacturing method of the circuit board formed from the fluid material containing a conductor material, The circuit board manufacturing method which forms the said wiring by the inkjet system. A circuit board having wiring formed on a substrate, wherein the electronic device includes a circuit board having different characteristics of at least two portions on the same wiring, respectively. A circuit board having wiring formed on a substrate, wherein the display device uses a circuit board having different characteristics on at least two sites on the same wiring as circuit boards for display. A circuit board having wiring formed on a substrate, wherein a circuit board having different characteristics of at least two sites on the same wiring is used as a circuit board for liquid crystal display.

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