KR20060002130A - Phase-change random access memory device and method for manufacturing the same - Google Patents

Abstract

The present invention discloses a phase change memory device and a method of manufacturing the same. A phase change memory device according to the present invention is formed in an active region of a semiconductor substrate, and has a word line, a transistor having a drain arranged in an active region on one side of the word line and a source arranged in the active region on the other side of the word line; Each bit line contact connected to the source and drain, each bit line connected to the bit line contact, a bottom electrode contact connected to the bit line portion corresponding to the source, and a respective phase connected to the bottom electrode contact. It includes a change film pattern and an upper electrode.

Description

Phase change memory device and its manufacturing method {PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a graph for explaining a method of programming and erasing a phase change memory device.

2 is a final stereoscopic view for explaining a phase change memory device according to the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a phase change memory device according to the present invention.

4A to 4E are three-dimensional views illustrating a method of manufacturing a phase change memory device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same. More specifically, a phase change memory capable of improving the operating characteristics of a device by making the same channel length by forming the same number of bit line contacts in a source and a drain. An element and a method of manufacturing the same.

Semiconductor memory devices, such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory (SRAM)), are volatile and fast data input / output (RAM) products that lose data over time. Once the data is entered, the status can be maintained, but it can be largely classified as a ROM product having slow input / output data. Such typical memory elements represent logic '0' or logic '1' depending on the stored charge.

Here, the DRAM, which is a volatile memory device, requires high charge storage capability because periodic refresh operation is required, and thus many efforts have been made to increase the surface area of a capacitor electrode. However, increasing the surface area of the capacitor electrode makes it difficult to increase the integration of the DRAM device.

On the other hand, nonvolatile memory devices have almost indefinite storage capacities, and there is an increasing demand for flash memory devices that are electrically input and output such as EEPROM (Elecrtically Erasable and Programmable ROM).

Such flash memory cells generally have a vertically stacked gate structure having a floating gate formed on a silicon substrate. The multilayer gate structure typically includes one or more tunnel oxide or dielectric layers and a control gate formed on or around the floating gate, wherein the principle of writing or erasing data in the flash memory cell is based on the tunnel oxide layer. A method of tunneling charges is used. At this time, a higher operating voltage than the power supply voltage is required. As a result, the flash memory elements require a boosting circuit to form a voltage necessary for writing and erasing operations.

Therefore, many efforts have been made to develop a new memory device having a non-volatile characteristic and random access, and having a simple structure while increasing the integration of devices. A representative example is a phase-change random access memory (PRAM). )to be.

The phase change memory device widely uses a chalcogenide film as a phase change film. In this case, the chalcogenide film is a compound film containing germanium (Ge), stevidium (Sb), and tellurium (Te) (hereinafter referred to as a 'GST film'), wherein the GST film is provided with a current, that is, Joule According to Joule Heat, a reversible phase change occurs between the amorphous state and the crystalline state.

1 is a graph for explaining a method of programming and erasing a phase change memory device, in which the horizontal axis represents time and the vertical axis represents temperature applied to the phase change film.

As shown in FIG. 1, when the phase change film is heated at a temperature higher than the melting temperature (Tm) for a short time (first operating period; t ₁ ) and then cooled rapidly (Quenching), the phase change film is amorphous. Change to Amorphous State (see curve 'A'). On the contrary, the phase change film is heated at a temperature lower than the melting temperature Tm and higher than the crystallization temperature Tc for a longer time than the first operating period t ₁ (second operating period t ₂ ). Upon cooling, the phase change film changes to Crystalline State (see curve 'B').

Here, the resistivity of the phase change film having an amorphous state is higher than that of the phase change film having a crystalline state. Accordingly, by detecting the current flowing through the phase change layer in the read mode, it is possible to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

As described above, Joule heat is required for the phase change of the phase change film. In a conventional phase change memory device, when a high density current flows through an area in contact with a phase change film, the crystal state of the phase change film contact surface changes, and the smaller the contact surface, the smaller the state of phase change material changes. The current density required to make it smaller. At this time, a current of 1 mA or more is required for the phase change of the phase change film. In the case of a transistor using 0.18 μm CMOS, the current must flow from the bit line to the GST cell only when the width is maintained to 1.5 μm or more. However, even if the width of the transistor is increased, since only one bit line contact is formed in the GST cell, the distance from the bit line contact to the bit line contact of the GST cell is different. Since a current path is formed by a bit line formed in the source, current driving is decreased, and current writing is dropped in the GST cell as the drain and the source are changed even when writing.

Accordingly, the present invention has been made to solve the above problems, by forming the same number of bit line contacts in the source and drain, by connecting each bit line contact to the bit line and forming a GST cell thereon It is an object of the present invention to provide a method of manufacturing a phase change memory device capable of improving the operating characteristics of a device by forming the same channel length.

The phase change memory device according to the present invention for achieving the above object is formed in the active region of the semiconductor substrate, the word line, the drain arranged in the active region on one side of the word line and the active region on the other side of the word line A transistor having an arranged source, a respective bit line contact connected to the source and drain, a respective bit line connected to the bit line contact, a lower electrode contact connected to the bit line portion corresponding to the source, and a lower electrode Each phase change film pattern and an upper electrode connected to the contact is characterized in that it is configured.

The word line is formed to have a width of 1 μm or more.

The source and drain are implanted with N-type ions, either of P and As.

The bit line contacts are formed in the same number of sources and drains with respect to the word lines so that the channel lengths are the same.

The bit line contact may use any one of polycrystalline silicon and metal series. The bit line uses any one of polycrystalline silicon and metal series.

The lower electrode contact uses any one of polycrystalline silicon and metal series.

The upper electrode uses any one of polycrystalline silicon and metal series.

Meanwhile, a method of manufacturing a phase change memory device according to the present invention includes the steps of providing a semiconductor substrate having an active region, forming a word line on the substrate, and having an active region arranged under both sides of the word line. Manufacturing a transistor by forming a drain in an active region on one side of a line and a source in the active region on the other side of the word line, forming respective bit line contacts to be connected to a source and a drain, and forming a bit line contact Forming each bit line to be connected, forming a bottom electrode contact to be connected to a bit line portion corresponding to the source, and sequentially forming a phase change layer pattern and an upper electrode to be connected to the bottom electrode contact. It is characterized by including.

The word line is preferably formed to have a width of 1 μm or more.

The source and drain are formed by implanting N-type ions into the active region using the word line as a mask, and implanting any one of P and As into the N-type ions.

The bit line contacts are formed in the same number of sources and drains on the basis of the word lines to make the channel lengths the same.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a final stereoscopic view for explaining a phase change memory device according to the present invention.

As shown in FIG. 2, the phase change memory device according to the present invention is formed in an active region 102 of a semiconductor substrate (not shown), and includes a word line 104 and an active region on one side of the word line 104. A transistor (not shown) having a drain (not shown) and a source (not shown) arranged in an active region on the other side of the word line, and connected to a source and a drain, respectively, A bit line contact 103 formed in the same number of drains to have the same channel length, each bit line 106 connected to the bit line contact 103, and a bit line region 106a corresponding to the drain. And a phase change film pattern 108 and an upper electrode 110 connected to the lower electrode contact 107 connected to the lower electrode contact 1007. At this time, the word line 104 is formed to have a width of 1㎛ or more.

3A to 3E are cross-sectional views illustrating a method of manufacturing the phase change memory device according to the present invention, and FIGS. 4A to 4E are three-dimensional views illustrating the method of manufacturing the phase change memory device according to the present invention.

The method of manufacturing a phase change memory device according to the present invention having the above-described configuration provides a semiconductor substrate having an active region 102, as shown in Figs. 3A and 4A. After the word line 104 is formed in the N-type ion implantation process using the word line as a mask, a drain (not shown) is formed in the active region on one side of the word line, and a source (in the active region on the other side of the word line). Transistors are fabricated by forming respective ones. In this case, the word line 104 is formed to have a width of 1㎛ or more. In addition, any one of P and As is used as said N type ion. Meanwhile, in FIGS. 3A and 4A, a source is formed at an upper portion of the word line 104 and a drain is formed at the lower portion of the word line 104.                     

3B and 4B, each bit connected to a source and a drain by patterning the first conductive film after forming a first conductive film (not shown) on the substrate on which the transistor is manufactured. Line contact 103 is formed. In this case, the bit line contacts 103 are formed in the same number of sources and drains based on the word lines 104 to make the channel lengths the same. In the present invention, the insulating film forming step will be omitted.

3C and 4C, a second conductive film (not shown) is formed on the substrate including the bit line contact, and then each bit connected to the bit line contact is patterned by patterning the second conductive film. Line 106 is formed. In this case, the bit line 106 forms a bit line 106a with a length of an active region in a portion where a GST cell is formed, and writes and reads the bit line 106b by lengthening the bit line 106b. In operation, the amplifier is amplified for the portion of the bit line labeled 106b.

3C and 4C, reference numeral 106a denotes a bit line connected to a drain, and reference numeral 106b denotes a bit line connected to a source.

3D and 4D, a third conductive film (not shown) is formed on the resultant, and then the third conductive film is patterned to form a lower portion connected to the bit line region 106a corresponding to the source. Electrode contact 107 is formed.

3E and 4E, a phase change film (not shown) and a fourth conductive film (not shown) are sequentially formed on the substrate including the lower electrode contact 107, and then the fourth The conductive layer and the phase change layer are patterned to form respective phase change layer patterns 108 and upper electrodes 110 that are connected to the lower electrode contacts 107 in turn. In this case, any one of polysilicon and metal series is used as the first, second, third and fourth conductive films.

According to the present invention, the same number of bit line contacts are formed in the source and drain, each bit line contact is connected to the bit line, and the GST cell is formed thereon, thereby forming the same channel length to improve the operation characteristics of the device. Can be improved.

As described above, in the present invention, the same channel length is formed by forming the same number of bit line contacts 103 in the source and the drain of the word line, thereby improving the operation characteristics of the device.

In addition, in the present invention, by forming a lower electrode contact on the bit line in the GST cell, the current flow is concentrated in the lower electrode contact through the bit line so that the phase change of the phase change material occurs easily, thereby operating the device. There is an advantage of improving the properties.

Claims (14)

A transistor formed in an active region of the semiconductor substrate, the transistor having a word line, a drain arranged in an active region on one side of the word line, and a source arranged in an active region on the other side of the word line; Respective bit line contacts connected to the source and drain, Each bit line connected to the bit line contact; A lower electrode contact connected to the bit line portion corresponding to the source; And a phase change film pattern and an upper electrode connected to the lower electrode contact. The phase change memory device as claimed in claim 1, wherein the word line has a width of 1 µm or more. The phase change memory device as claimed in claim 1, wherein the source and the drain are implanted with N-type ions. The phase change memory device as claimed in claim 3, wherein the N-type ion is any one of P and As. The phase change memory device as claimed in claim 1, wherein the bit line contacts are formed in the same number of sources and drains based on the word lines, and have the same channel length. 2. The phase change memory device as claimed in claim 1, wherein the bit line contact uses any one of polycrystalline silicon and metal series. The phase change memory device as claimed in claim 1, wherein the bit line uses any one of polycrystalline silicon and metal series. The phase change memory device as claimed in claim 1, wherein the lower electrode contact is made of any one of polycrystalline silicon and metal series. The phase change memory device as claimed in claim 1, wherein the upper electrode uses any one of polycrystalline silicon and metal series. Providing a semiconductor substrate having an active region; A word line is formed on the substrate, and active regions are arranged below both sides of the word line, a drain is formed in an active region on one side of the word line, and a source is formed in the active region on the other side of the word line. To do that, Forming respective bitline contacts to be connected to the source and drain; Forming each bit line to be connected to the bit line contact; Forming a bottom electrode contact to be connected to a bit line portion corresponding to the source; And sequentially forming a phase change layer pattern and an upper electrode so as to be connected to the lower electrode contact. The method of claim 10, wherein the word line is formed to have a width of 1 μm or more. The method of claim 10, wherein the source and the drain are formed by performing N-type ion implantation into the active region using the word line as a mask. The method of claim 12, wherein the N-type ion implantation process implants any one of P and As. 12. The method of claim 10, wherein the bit line contacts are formed in the same number of sources and drains with respect to the word lines so as to have the same channel length.

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