KR100650720B1 - Phase-change memory device and method for manufacturing the same - Google Patents

Abstract

The present invention can reduce the amount of current required for the phase change of the phase change film by reducing the contact area between the phase change film and the top electrode, and improve the driving speed capability of the phase change memory device. A phase change memory device and a method of manufacturing the same are disclosed. The disclosed phase change memory device includes a first insulating layer having a first contact hole formed on a semiconductor substrate having a predetermined substructure and exposing a predetermined portion of the substrate, and filling the first contact holes. Conductive plugs; a second contact hole formed to expose a portion of the substrate between the conductive plugs in the first insulating film including the conductive plugs; and a second contact hole formed on the first insulating film. A buried bit line, a second insulating layer formed on the first insulating layer including the conductive plugs and the bit line and having a trench between the third contact holes and the third contact holes exposing the conductive plugs; And an upper electrode formed to cover the bottom and side surfaces of the trench, a third insulating layer to fill the trench including the upper electrode, and a lower electrode to fill the third contact holes. And a phase change layer pattern formed on the second and third insulating layers including the contacts and the upper and lower electrode contacts, and contacting the upper and lower electrode contacts.

Description

Phase change memory device and its manufacturing method {PHASE-CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a graph for explaining a method of programming and erasing a phase change memory device.

2 is a cross-sectional view for explaining a conventional phase change memory element.

3 is a cross-sectional view illustrating a phase change memory device according to an embodiment of the present invention.

4A to 4H are cross-sectional views illustrating processes for manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

Explanation of symbols on main parts of drawing

40: semiconductor substrate 41: first contact hole

42: first insulating film 43: conductive plug

44: second contact hole 45: bit line

46: second insulating film 47: trench

48 conductive film for upper electrode 49 third insulating film

48a: upper electrode 49a: third insulating film remaining after CMP

50: third contact hole 51: lower electrode contact

52: phase change film 53: hard mask film                 

52a: Phase change film pattern 53a: Hard mask film remaining after etching

54: fourth insulating film 55: fourth contact hole

56: upper electrode contact 57: metal pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, by reducing the contact area between the phase change film and the top electrode, thereby reducing the amount of current required for the phase change of the phase change film and the phase change memory. A phase change memory device for improving the drive speed capability of the device and a method of manufacturing the same.

Semiconductor memory devices, such as DRAM (DRAM) and SRAM (Static Random Access Memory), are volatile and lose their data over time. Once the data is entered, it can be maintained, but it can be divided into read only memory (ROM) products that have slow input / output data. Such typical memory elements represent logic '0' or logic '1' depending on the stored charge.

Here, the DRAM, which is a volatile memory device, requires high charge storage capability because periodic refresh operation is required, and thus, many efforts have been made to increase the surface area of the capacitor electrode. However, increasing the surface area of the capacitor electrode makes it difficult to increase the integration of the DRAM device.

On the other hand, nonvolatile memory devices have almost indefinite storage capacities, and in particular, demand for flash memory devices that can be electrically input and output such as EEPROM (elecrtically erasable and programmable ROM) is increasing.

Such flash memory cells generally have a vertically stacked gate structure with a floating gate formed on a silicon substrate. The multilayer gate structure typically includes one or more tunnel oxide or dielectric films and a control gate formed on or around the floating gate, wherein the principle of writing or erasing data in the flash memory cell is based on It uses a method of tunneling charges through. At this time, a higher operating voltage than the power supply voltage is required. As a result, the flash memory elements require a boosting circuit to form a voltage necessary for writing and erasing operations.

Therefore, many efforts have been made to develop a new memory device having a non-volatile characteristic, random access, and a simple structure while increasing the integration of the device. A representative example is a phase change random access memory (PRAM). to be.

The phase change memory device widely uses a chalcogenide film as a phase change film. In this case, the chalcogenide film is a compound film containing germanium (Ge), stevidium (Sb), and tellurium (Te) (hereinafter referred to as a 'GST film'), wherein the GST film is provided with a current, that is, Joule The heat is electrically switched between the amorphous state and the crystalline state according to the joule heat.

1 is a graph for explaining a method of programming and erasing a phase change memory device, in which the horizontal axis represents time and the vertical axis represents temperature applied to the phase change film.

As shown in FIG. 1, when the phase change film is heated at a temperature higher than the melting temperature (Tm) for a short time (first operating period; t ₁ ) and then cooled rapidly (qenching), the phase change film is amorphous. Change to an amorphous state (see curve 'A'). On the contrary, the phase change film is heated at a temperature lower than the melting temperature Tm and higher than the crystallization temperature Tc for a longer time than the first operating period t ₁ (second operating period; t ₂ ). Upon cooling, the phase change film changes to a crystalline state (see curve 'B').

Here, the resistivity of the phase change film having an amorphous state is higher than that of the phase change film having a crystalline state. Therefore, by sensing the current flowing through the phase change film in the read mode, it is possible to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

As described above, Joule heat is required for the phase change of the phase change film. In a conventional phase change memory device, when a high density of current flows through an area in contact with a phase change film, the crystal state of the phase change film contact surface changes, and the smaller the contact surface changes the state of the phase change material. The required current density is small.                         

2 is a cross-sectional view illustrating a conventional phase change memory device.

As shown in FIG. 2, the conventional phase change memory device includes a semiconductor substrate 10 having a bottom electrode 11 formed thereon, and formed on the bottom electrode 11 to form a bottom electrode 11. A first insulating film 12 having a first contact hole 13 exposing a predetermined portion, a bottom electrode contact 14 filling the first contact hole 13, and the bottom electrode contact A second insulating film 15 formed on the first insulating film 12 including the second insulating film 15 having a second contact hole 16 exposing the lower electrode contact 14, and the second contact hole 16. ) And a top electrode 18 formed on the second insulating layer 15 including the phase change layer 17.

In the conventional phase change memory device, when a current flows between the lower electrode 11 and the upper electrode 18, the contact surface 19 between the lower electrode contact 14 and the phase change film 17 passes through. The crystal state of the phase change film of the contact surface 19 changes according to the current intensity (ie, heat). At this time, the heat required to change the state of the phase change film is directly affected by the contact surface 19 of the phase change film 17 and the lower electrode contact 14. Therefore, the contact area between the phase change film 17 and the lower electrode contact 14 should be as small as possible.

However, in the conventional phase change memory device, since the lower electrode 11 and the phase change film 17 are connected through the lower electrode contact 14, the phase change film 17 and the lower electrode contact 14 are connected. The contact area between) is entirely limited by the photo process limits for the contact hole, which makes it difficult to reduce the contact area. As a result, the amount of current required for the phase change is increased, and the driving speed capability of the phase change memory device is degraded.

Accordingly, the present invention has been made to solve the above problems, and by reducing the area of the portion where the phase change occurs, it is possible to lower the amount of current required for the phase change of the phase change film, It is an object of the present invention to provide a phase change memory device capable of improving the driving speed capability and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a phase change memory device including: a first insulating layer formed on a semiconductor substrate having a predetermined substructure and having first contact holes exposing a predetermined portion of the substrate; Conductive plugs filling the first contact holes, a second contact hole formed to expose a portion of the substrate between the conductive plugs in the first insulating film including the conductive plugs, and formed on the first insulating film. And fill the second contact hole and between the third contact holes and the third contact holes formed on the first insulating layer including the conductive plugs and the bit line and exposing the conductive plugs. A second insulating film having a trench, an upper electrode formed to cover the bottom and side surfaces of the trench, a third insulating film filling the trench including the upper electrode, and the third cone A lower electrode contact filling the holes and formed on the second and third insulating layers including the upper electrode and the lower electrode contacts, and each of the phase change layer patterns contacting the upper electrode and the lower electrode contact. It is characterized by.                     

Here, the second insulating film is made of any one selected from the group consisting of HDP, USG, PSG, BPSG, SOG, HLD, and TEOS oxide film. And, the upper electrode has a thickness of less than 500Å. In addition, the phase change layer pattern has a dual structure in which a phase change layer and a hard mask layer are sequentially stacked, wherein the phase change layer is formed of any one of a GeSb 2 Te 4 film and a Ge 2 Sb 2 Te 5 film. And a fourth insulating layer formed on the second and third insulating layers including the phase change layer pattern and having a fourth contact hole exposing a portion of the upper electrode, and an upper electrode filling the fourth contact hole. And a metal pattern connected to the contact and the upper electrode contact.

In addition, in the method of manufacturing a phase change memory device of the present invention for achieving the above object, by forming a first insulating film on a semiconductor substrate provided with a predetermined substructure, by selectively etching the first insulating film Forming first contact holes exposing a portion of the substrate; Filling the first contact holes with a conductive film to form conductive plugs; Selectively etching the first insulating layer to expose a portion of the substrate between the conductive plugs to form a second contact hole; Depositing a metal film on the first insulating layer to fill the second contact hole, and then selectively etching the metal layer to form a bit line; Forming a second insulating layer on the first insulating layer including the conductive plugs and the bit line; Selectively etching the second insulating layer to form a trench on the bit line; Forming an upper electrode conductive film and a third insulating film on the second insulating film including the trench; CMPing the third insulating layer and the conductive layer for the upper electrode until the second insulating layer is exposed to form an upper electrode covering the bottom and side surfaces of the trench; Selectively etching the second insulating layer to expose the conductive plugs to form third contact holes; Forming lower electrode contacts filling the third contact holes; And forming each phase change layer pattern on the resultant in contact with the upper electrode and the lower electrode contact.

Here, the conductive film for the upper electrode is formed to a thickness of less than 500Å. The forming of the phase change layer pattern may include sequentially forming a phase change layer and a hard mask layer on the resultant, selectively etching the hard mask layer and the phase change layer to contact the upper electrode and the lower electrode contact. Forming a phase change film pattern in contact.

Further, after forming a phase change layer pattern, a fourth insulating layer is formed on the second and third insulating layers including the phase change layer pattern, and then the fourth and third insulating layers are selectively etched to form the upper electrode. Forming a fourth contact hole exposing a portion of the second contact hole, and forming a top electrode contact filling the fourth contact hole and a metal pattern connected to the upper electrode contact, respectively. In this case, the upper electrode contact and the metal pattern are simultaneously formed.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view illustrating a phase change memory device according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the phase change memory device according to the exemplary embodiment of the present invention is formed on a semiconductor substrate 40 having a predetermined substructure (not shown), and a predetermined portion of the substrate 40. A first insulating layer 42 having first contact holes 41 exposing the first contact hole 41, conductive plugs 43 filling the first contact holes 41, and the first plugs including the conductive plugs 43. A second contact hole 44 formed in the insulating film 42 to expose a portion of the substrate 40 between the conductive plugs 43 and the second contact hole formed on the first insulating film 42. A third line formed on the first insulating layer 42 including the bit line 45 filling the 44 and the conductive plugs 43 and the bit line 45, and exposing the conductive plugs 43. A second insulating layer 46 having a trench 47 between the contact holes 50 and the third contact holes 50, and an upper portion formed to cover the bottom and side surfaces of the trench 47. A third insulating film 49a filling an electrode 48a, the trench 47 including the upper electrode 48a, lower electrode contacts 51 filling the third contact holes 50, Each of the phase change layers contacting the upper electrode 48a and the lower electrode contact 51 on the second and third insulating layers 46 and 49a including the upper electrode 49a and the lower electrode contacts 51. Pattern 52a.

Here, the second insulating layer 46 is made of any one selected from the group consisting of HDP, USG, PSG, BPSG, SOG, HLD, and TEOS oxide. The upper electrode 48a is made of any one of polysilicon and metal based materials. In addition, the upper electrode 48a has a thickness of 500 Å or less, wherein the thickness of the upper electrode 48a determines the contact area between the phase change film pattern 52a and the upper electrode 48a. . That is, since the upper electrode 48a has a thin thickness of 500 Å or less, the upper electrode 48a is in contact with the phase change film pattern 52a while having a small contact area. In addition, the lower electrode contact 51 is made of one of polysilicon and metal based materials.

On the other hand, a hard mask film 53a is formed on the phase change film pattern 52a. Here, the phase change film pattern 52a is made of a GST film, and any one of the GeSb2Te4 film and the Ge2Sb2Te5 film is used as the GST film.

The phase change memory device according to the embodiment of the present invention is formed on the second and third insulating layers 46 and 49a including the phase change layer pattern 52a and the hard mask layer 53a. A fourth insulating film 54 having a fourth contact hole 55 exposing a portion of the electrode 48a, a top electrode contact 56 filling the fourth contact hole 55; A metal pattern 57 is further connected to the upper electrode contact 56.

Hereinafter, a method of manufacturing the phase change memory device shown in FIG. 3 will be described.

4A to 4H are cross-sectional views illustrating processes of manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

In the method of manufacturing a phase change memory device according to an embodiment of the present invention, as shown in FIG. 4A, a first insulating layer 42 is formed on a semiconductor substrate 40 having a predetermined substructure (not shown). Then, the first insulating layer 42 is selectively etched to form first contact holes 41 exposing predetermined portions of the substrate 40. Subsequently, the first contact holes 41 are filled with a conductive film to form conductive plugs 43.                     

Thereafter, the first insulating layer 42 is selectively etched to expose a portion of the substrate 40 between the conductive plugs 43 to form a second contact hole 44. Subsequently, a metal film is deposited on the first insulating layer 42 to fill the second contact hole 44, and then selectively etched to form a bit line 45.

Subsequently, as illustrated in FIG. 4B, a second insulating layer 46 is formed on the first insulating layer 42 including the conductive plugs 43 and the bit line 45. The second insulating layer 46 may be any one selected from the group consisting of HDP, USG, PSG, BPSG, SOG, HLD, and TEOS oxide. Thereafter, the second insulating layer 46 is selectively etched to form the trench 47 on the bit line 45.

Then, an upper electrode conductive film 48 is formed on the second insulating film 46 including the trench 47. The upper electrode conductive film 48 may be formed of any one of a polysilicon film and a metal film, and the upper electrode conductive film 48 may be formed to a thickness of 500 kPa or less. Subsequently, a third insulating layer 49 is formed on the upper electrode conductive layer 48 to fill the trench 47.

On the other hand, the thickness of the upper electrode conductive film 48 determines the contact area between the upper electrode and the phase change film to be formed later. That is, the contact area between the upper electrode and the phase change film can be reduced by making the thickness of the upper electrode conductive film 48 as thin as possible. Since the thickness of the upper conductive film 48 for determining the contact area is not influenced by the limitation of the photolithography process, the thickness of the upper electrode conductive film 48 may be lower than that of the photolithography process.                     

Next, as shown in FIG. 4C, the trench is formed by chemical mechanical polishing (CMP) of the third insulating layer and the conductive layer for the upper electrode until the second insulating layer 46 is exposed. An upper electrode 48a covering the bottom surface and side surfaces of the 47 is formed. At this time, reference numeral 49a, which is not described in FIG. 4C, indicates the third insulating layer remaining after the CMP.

Next, as illustrated in FIG. 4D, the second insulating layer 46 is selectively etched to expose the conductive plugs 43 to form third contact holes 50.

Subsequently, as shown in FIG. 4E, the third contact holes 50 are filled with a conductive film to form lower electrode contacts 51 electrically connected to the conductive plugs 43. In this case, the lower electrode contact 51 is made of any one of a polysilicon film and a metal film. Next, the phase change film 52 and the hard mask film 53 are sequentially formed on the resultant product. Here, the phase change film 52 is made of a GST film, and in this case, any one of the GeSb 2 Te 4 film and the Ge 2 Sb 2 Te 5 film is used as the GST film.

Thereafter, as illustrated in FIG. 4F, the hard mask layer and the phase change layer are selectively etched to form phase change layer patterns 52a in contact with the upper electrode 48a and the lower electrode contact 51. At this time, reference numeral 53a, which is not described in FIG. 4F, indicates the hard mask layer remaining after etching.

Next, as shown in FIG. 4G, the second and third insulating layers 46 and 49a may be formed to cover the phase change layer pattern 52a and the hard mask layer 53a remaining after etching. After the fourth insulating layer 54 is formed, the fourth insulating layer 54 and the third insulating layer 49a are selectively etched to form a fourth contact hole 55 exposing a part of the upper electrode 48a. .

Thereafter, as shown in FIG. 4H, after forming a metal film on the fourth insulating layer 54 to fill the fourth contact hole 55, the metal layer is selectively etched to selectively etch the fourth contact hole 55. The upper electrode contact 56 and the metal pattern 57 connected to the upper electrode contact 56 are formed.

In the phase change memory device according to the present invention manufactured through the above process, the upper electrode is first formed so that the phase change occurs at the contact surface between the upper electrode and the phase change film pattern, and then the lower electrode contact is formed. A phase change layer pattern is formed in contact with the upper electrode and the lower electrode contact. In this case, the present invention allows the contact area between the upper electrode and the phase change film pattern to be determined by the thickness of the upper electrode, so that the area of the portion where the phase change occurs can be formed to a dimension lower than the limit of the conventional photo process. Can be. Therefore, the present invention can reduce the amount of current required for the phase change of the phase change film pattern.

As described above, according to the present invention, an upper electrode is first formed so that a phase change occurs at the contact surface between the upper electrode and the phase change layer pattern, and then a lower electrode contact is formed, and then the image is in contact with the upper electrode and the lower electrode contact. A change film pattern is formed. Herein, the contact area between the upper electrode and the phase change layer pattern may be determined by the thickness of the upper electrode.

That is, since the thickness of the upper electrode can be formed in a desired dimension by the deposition process, the area of the portion where the phase change occurs can be formed in a dimension lower than the limit of the conventional photo process. Therefore, the present invention can reduce the amount of current required for the phase change, and can improve the drive speed capability of the phase change memory element.

Claims (11)

A first insulating layer formed on a semiconductor substrate having a predetermined substructure and having first contact holes exposing a portion of the substrate; Conductive plugs filling the first contact holes; A second contact hole formed to expose a portion of the substrate between the conductive plugs in the first insulating layer including the conductive plugs; A bit line formed on the first insulating layer to fill the second contact hole; A second insulating layer formed on the first insulating layer including the conductive plugs and the bit line and having a trench between the third contact holes and the third contact holes exposing the conductive plugs; An upper electrode formed to cover the bottom and side surfaces of the trench; A third insulating film filling the trench including the upper electrode; Lower electrode contacts filling the third contact holes; And a phase change layer pattern formed on the second and third insulating layers including the upper electrode and the lower electrode contacts and in contact with the upper electrode and the lower electrode contact. The phase change memory device as claimed in claim 1, wherein the second insulating film is one selected from the group consisting of HDP, USG, PSG, BPSG, SOG, HLD, and TEOS oxide films. The phase change memory device as claimed in claim 1, wherein the upper electrode has a thickness of 500 mW or less. The phase change memory device as claimed in claim 1, wherein the phase change film pattern has a double structure in which a phase change film and a hard mask film are sequentially stacked. The phase change memory device as claimed in claim 4, wherein the phase change film is made of one of a GeSb2Te4 film and a Ge2Sb2Te5 film. The semiconductor device of claim 1, further comprising: a fourth insulating layer formed on the second and third insulating layers including the phase change layer pattern and having a fourth contact hole exposing a portion of the upper electrode, and the fourth contact hole. And a metal pattern connected to the buried upper electrode contact and the upper electrode contact. Forming a first insulating layer on a semiconductor substrate having a predetermined substructure, and then selectively etching the first insulating layer to form first contact holes exposing a portion of the substrate; Filling the first contact holes with a conductive film to form conductive plugs; Selectively etching the first insulating layer to expose a portion of the substrate between the conductive plugs to form a second contact hole; Depositing a metal film on the first insulating layer to fill the second contact hole, and then selectively etching the metal layer to form a bit line; Forming a second insulating layer on the first insulating layer including the conductive plugs and the bit line; Selectively etching the second insulating layer to form a trench on the bit line; Forming an upper electrode conductive film and a third insulating film on the second insulating film including the trench; CMPing the third insulating layer and the conductive layer for the upper electrode until the second insulating layer is exposed to form an upper electrode covering the bottom and side surfaces of the trench; Selectively etching the second insulating layer to expose the conductive plugs to form third contact holes; Forming lower electrode contacts filling the third contact holes; And forming a phase change layer pattern on the resultant in contact with the upper electrode and the lower electrode contact. The method of manufacturing a phase change memory device according to claim 7, wherein the upper electrode conductive film is formed to a thickness of 500 kPa or less. The method of claim 7, wherein the forming of the phase change film pattern comprises: Sequentially forming a phase change film and a hard mask film on the resultant; And selectively etching the hard mask layer and the phase change layer to form a phase change layer pattern in contact with the upper electrode and the lower electrode contact. The method of claim 7, after forming a phase change film pattern, Forming a fourth insulating layer on the second and third insulating layers including the phase change layer pattern, and then selectively etching the fourth and third insulating layers to expose a portion of the upper electrode. Forming step, And forming a metal pattern connected to the upper electrode contact and the upper electrode contact to fill the fourth contact hole, respectively. The method of claim 10, wherein the upper electrode contact and the metal pattern are formed at the same time.

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