KR100650721B1 - Phase-change memory device and method for manufacturing the same - Google Patents

Abstract

According to the present invention, by reducing the contact area between the phase change film and the bottom electrode, the amount of current required for the phase change of the phase change film can be lowered, and the driving speed capability of the phase change memory device can be improved. A phase change memory device and a method of manufacturing the same are disclosed. The disclosed phase change memory device includes a first insulating film having a first contact hole formed on a semiconductor substrate including a predetermined substructure and exposing a predetermined portion of the substrate, and filling the first contact hole. A lower electrode contact, a lower electrode formed on the first insulating layer including the lower electrode contact and connected to the lower electrode contact and having first spacers on both side walls, and formed on the lower electrode to form an upper portion of the lower electrode. A second insulating film pattern having surface edges and having second spacers on both side walls, and a first and a second insulating film formed on the first insulating film and adjacent to an upper surface of the lower electrode and the second insulating film pattern and adjacent to the upper surface. A stepped phase change film pattern covering a spacer, an upper electrode formed on the phase change film pattern, and a portion of the upper electrode formed on a resultant product including the upper electrode; And a third insulating layer having an exposed second contact hole, an upper electrode contact filling the second contact hole, and a word line formed on the third insulating layer and connected to the upper electrode contact. .

Description

Phase change memory device and its manufacturing method {PHASE-CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a graph for explaining a method of programming and erasing a phase change memory device.

2 is a cross-sectional view for explaining a conventional phase change memory element.

3 is a cross-sectional view illustrating a phase change memory device according to an embodiment of the present invention.

4A to 4G are cross-sectional views of processes for explaining a method of manufacturing a phase change memory device according to an embodiment of the present invention.

Explanation of symbols on main parts of drawing

40: semiconductor substrate 41: first insulating film

42: first contact hole 43: lower electrode contact

44: lower electrode 45: second insulating film pattern

45a: second insulating film pattern remaining after etching back 46a: first spacer

46b: second spacer 47: phase change film pattern

48: upper electrode 49: third insulating film

50: second contact hole 51: upper electrode contact

52: word line A: contact portion

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, by reducing the contact area between the phase change film and the lower electrode, thereby reducing the amount of current required for the phase change of the phase change film and improving the driving speed capability of the phase change memory device. A phase change memory device and a method of manufacturing the same.

Semiconductor memory devices, such as DRAM (dynamic random access memory) and SRAM (static random access memory (SRAM)), are volatile and fast data input / output (RAM) products that lose data over time. Once the data is entered, it can be maintained, but it can be divided into read only memory (ROM) products that have slow input / output data. Such typical memory elements represent logic '0' or logic '1' depending on the stored charge.

Here, the DRAM, which is a volatile memory device, requires high charge storage capability because periodic refresh operation is required, and thus, many efforts have been made to increase the surface area of the capacitor electrode. However, increasing the surface area of the capacitor electrode makes it difficult to increase the integration of the DRAM device.

On the other hand, nonvolatile memory devices have almost indefinite storage capacities, and in particular, demand for flash memory devices that can be electrically input and output such as EEPROM (elecrtically erasable and programmable ROM) is increasing.                         

Such flash memory cells generally have a vertically stacked gate structure with a floating gate formed on a silicon substrate. The multilayer gate structure typically includes one or more tunnel oxide or dielectric films and a control gate formed on or around the floating gate, wherein the principle of writing or erasing data in the flash memory cell is based on It uses a method of tunneling charges through. At this time, a higher operating voltage than the power supply voltage is required. As a result, the flash memory elements require a boosting circuit to form a voltage necessary for writing and erasing operations.

Therefore, many efforts have been made to develop a new memory device having a non-volatile characteristic, random access, and a simple structure while increasing the integration of the device. A representative example is a phase change random access memory (PRAM). to be.

The phase change memory device widely uses a chalcogenide film as a phase change film. In this case, the chalcogenide film is a compound film containing germanium (Ge), stevidium (Sb), and tellurium (Te) (hereinafter referred to as a 'GST film'), wherein the GST film is provided with a current, that is, Joule According to joule heat, the switch is electrically switched between an amorphous state and a crystalline state.

1 is a graph for explaining a method of programming and erasing a phase change memory device, in which the horizontal axis represents time and the vertical axis represents temperature applied to the phase change film.                         

As shown in FIG. 1, when the phase change film is heated at a temperature higher than the melting temperature (Tm) for a short time (first operating period; t ₁ ) and then cooled rapidly (quenching), the phase change film is amorphous. Change to an amorphous state (see curve 'A'). On the contrary, the phase change film is heated at a temperature lower than the melting temperature Tm and higher than the crystallization temperature Tc for a longer time than the first operating period t ₁ (second operating period; t ₂ ). Upon cooling, the phase change film changes to a crystalline state (see curve 'B').

Here, the resistivity of the phase change film having an amorphous state is higher than that of the phase change film having a crystalline state. Accordingly, by detecting the current flowing through the phase change layer in the read mode, it is possible to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

As described above, Joule heat is required for the phase change of the phase change film. In a conventional phase change memory device, when a high density of current flows through an area in contact with a phase change film, the crystal state of the phase change film contact surface changes, and the smaller the contact surface changes the state of the phase change material. The required current density is small.

2 is a cross-sectional view illustrating a conventional phase change memory device.

As shown in FIG. 2, the conventional phase change memory device includes a semiconductor substrate 10 having a bottom electrode 11 formed thereon, and formed on the bottom electrode 11 to form a bottom electrode 11. A first insulating film 12 having a first contact hole 13 exposing a predetermined portion, a bottom electrode contact 14 filling the first contact hole 13, and the bottom electrode contact; A second insulating film 15 formed on the first insulating film 12 including the second insulating film 15 having a second contact hole 16 exposing the lower electrode contact 14, and the second contact hole 16. ) And a top electrode 18 formed on the second insulating layer 15 including the phase change layer 17.

In the conventional phase change memory device, when a current flows between the lower electrode 11 and the upper electrode 18, the contact surface 19 between the lower electrode contact 14 and the phase change film 17 passes through. The crystal state of the phase change film of the contact surface 19 changes according to the current intensity (ie, heat). At this time, the heat required to change the state of the phase change film is directly affected by the contact surface 19 of the phase change film 17 and the lower electrode contact 14. Therefore, the contact area between the phase change film 17 and the lower electrode contact 14 should be as small as possible.

However, in the conventional phase change memory device, since the lower electrode 11 and the phase change film 17 are connected through the lower electrode contact 14, the phase change film 17 and the lower electrode contact 14 are connected. The contact area between) is entirely limited by the photo process limits for the contact hole, which makes it difficult to reduce the contact area. As a result, the amount of current required for the phase change is increased, and the driving speed capability of the phase change memory device is degraded.

Accordingly, the present invention has been made to solve the above problems, by reducing the contact area between the phase change film and the lower electrode, thereby reducing the amount of current required for the phase change of the phase change film, and improves the drive speed capability of the phase change memory device. An object of the present invention is to provide a phase change memory device and a method of manufacturing the same.

A phase change memory device of the present invention for achieving the above object is a first insulating film formed on a semiconductor substrate including a predetermined substructure and having a first contact hole for exposing a predetermined portion of the substrate, A lower electrode contact filling the first contact hole, a lower electrode formed on the first insulating layer including the lower electrode contact and connected to the lower electrode contact and having first spacers on both sidewalls, and on the lower electrode. A second insulating layer pattern formed on the first insulating layer to expose an edge portion of the lower surface of the lower electrode and having second spacers on both sidewalls, and formed on the first insulating layer to form an upper surface of the lower electrode and the second insulating layer pattern; A phase change film pattern having a step shape covering the first and second spacers adjacent to the upper surface, an upper electrode formed on the phase change film pattern, and a resultant including the upper electrode; A third insulating layer having a second contact hole exposing a portion of the upper electrode, an upper electrode contact filling the second contact hole, a word line formed on the third insulating layer and connected to the upper electrode contact; It is characterized by including.

The phase change layer pattern may include one of a GeSb2Te4 layer and a Ge2Sb2Te5 layer, and the second insulating layer pattern may include one of a nitride layer and an oxide layer. The first and second spacers may be formed of a nitride film, and the upper electrode contact may be formed of any one of W and TiW.

In addition, in the method of manufacturing a phase change memory device of the present invention for achieving the above object, after forming a first insulating film on a semiconductor substrate including a predetermined substructure, and selectively etching the first insulating film. Forming a first contact hole exposing a predetermined portion of the substrate; Filling the first contact hole with a conductive film to form a lower electrode contact; Sequentially forming a lower electrode and a second insulating layer pattern connected to the lower electrode contact on the first insulating layer including the lower electrode contact; Etching back the second insulating film pattern to expose the upper edge portion of the lower electrode; Forming first and second spacers on both sidewalls of the lower electrode and the second insulating layer pattern remaining after the etch back; Sequentially forming a phase change film and an upper electrode conductive film on the entire surface of the resultant product; A step change phase pattern and an upper step shape covering the first and second spacers adjacent to the upper surface and one side of the lower electrode and the second insulating layer pattern by selectively etching the upper electrode conductive layer and the phase change layer Forming an electrode; Forming a third insulating layer on the resultant including the upper electrode, and selectively etching the third insulating layer to form a second contact hole exposing a portion of the upper electrode; Forming an upper electrode contact to fill the second contact hole; And forming a word line connected to the upper electrode contact.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view illustrating a phase change memory device according to an exemplary embodiment of the present invention.                     

As shown in FIG. 3, a phase change memory device according to an exemplary embodiment of the present invention is formed on a semiconductor substrate 40 including a predetermined substructure (not shown), and thus a predetermined portion of the substrate 40 may be formed. A first insulating layer 41 having a first contact hole 42 to be exposed, a bottom electrode contact 43 filling the first contact hole 42, and the lower electrode contact 43. A bottom electrode 44 formed on the first insulating layer 41 and connected to the lower electrode contact 43 and having first spacers 46a on both side walls thereof; A second insulating layer pattern 45a formed on an electrode 44 and exposing an upper edge portion of the lower electrode 44 and having second spacers 46b on both side walls; and the first insulating layer 41. A top surface of the lower electrode 44 and the second insulating layer pattern 45a and covering the first and second spacers 46a and 46b adjacent to the upper surface. The upper layer 48 formed on the phase change layer pattern 47, the top electrode 48 formed on the phase change layer pattern 47, and the upper electrode 48, A third insulating film 49 having a second contact hole 50 exposing a portion of the electrode 48, a top electrode contact 51 filling the second contact hole 50, and And a word line 52 formed on the third insulating layer 49 and connected to the upper electrode contact 51.

Here, the lower electrode 44 and the upper electrode 48 are both made of one of polysilicon and metal based materials. The phase change film pattern 47 is formed of a GST film. At this time, any one of the GeSb2Te4 film and the Ge2Sb2Te5 film is used as the GST film.                     

In addition, the second insulating layer pattern 45a may be formed of one of a nitride layer and an oxide layer, and the first and second spacers 46a and 46b may be formed of a nitride layer. The upper electrode contact 51 is made of any one material of W and TiW.

On the other hand, a contact surface A of the phase change layer pattern 47 is formed on one side of the lower electrode 44, and when a current flows between the lower electrode 44 and the upper electrode 48, the contact surface ( In A), a phase change of the phase change film pattern 47 occurs.

In this case, the area of the contact surface A is not limited by the photo process limit, and is defined by the second insulating layer pattern 45a and the spacer 46b remaining after the etch back formed on the lower electrode 44. That is, the area of the contact surface (A) is not influenced by the limitation of the photolithography process, but depends on the etch back process, so that the contact surface A may have a dimension lower than the limitation of the photolithography process. Accordingly, the amount of current required for the phase change of the phase change film pattern 47 can be lowered as compared with the related art, and the driving speed capability of the phase change memory device can be improved.

Hereinafter, a method of manufacturing the phase change memory device shown in FIG. 3 will be described.

4A to 4G are cross-sectional views illustrating processes of manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

In the method of manufacturing a phase change memory device according to an embodiment of the present invention, as shown in FIG. 4A, a first insulating layer 41 is formed on a semiconductor substrate 40 including a predetermined substructure (not shown). Thereafter, the first insulating layer 41 is selectively etched to form a first contact hole 42 exposing a predetermined portion of the substrate 40. Subsequently, the first contact hole 42 is filled with a conductive film to form a lower electrode contact 43.

Subsequently, as shown in FIG. 4B, the lower electrode 44 and the second insulating layer pattern connected to the lower electrode contact 43 on the first insulating layer 41 including the lower electrode contact 43 ( 45) are formed in sequence. The lower electrode 44 may be made of any one of polysilicon and metal, and the second insulating pattern 45 may be formed of any one of a nitride film and an oxide film.

Then, as illustrated in FIG. 4C, the second insulating layer pattern is etched back to expose the upper edge portion of the lower electrode 44. At this time, reference numeral 45a, which is not described in FIG. 4C, indicates the second insulating layer pattern remaining after the etch back.

Next, as shown in FIG. 4D, after forming a nitride film (not shown) on the entire surface of the resultant including the second insulating film pattern 45a remaining after the etch back, the nitride film is etched back to the lower electrode 44. ) And first and second spacers 46a and 46b of nitride film materials are formed on both sidewalls of the second insulating layer pattern 45a remaining after the etch back.

Subsequently, as shown in FIG. 4E, a phase change film (not shown) and an upper electrode conductive film (not shown) are sequentially formed on the entire surface of the resultant product. Here, the phase change film is made of a GST film. At this time, any one of the GeSb2Te4 film and the Ge2Sb2Te5 film is used as the GST film. In addition, the conductive film for the upper electrode is made of any one of polysilicon-based and metal-based.                     

Thereafter, the upper electrode conductive layer and the phase change layer are selectively etched so that the first electrode adjacent to the upper surface and the upper surface of one side of the lower electrode 44 and the second insulating layer pattern 45a remaining after the etch back. A stepped phase change film pattern 47 and an upper electrode 48 covering the second spacers 46a and 46b are formed.

In this case, a contact surface A of the phase change layer pattern 47 exists on one side of the lower electrode 44, and when a current flows between the lower electrode 44 and the upper electrode 48, the contact surface is present. In (A), a phase change of the phase change film pattern 47 occurs. Here, the area of the contact surface A is not limited by the photo process limit, and is defined by the second insulating layer pattern 45a and the spacer 46b remaining after the etch back formed on the lower electrode 44. That is, the area of the contact surface (A) is not influenced by the limitation of the photolithography process, but depends on the etch back process, so that the contact surface A may have a dimension lower than the limitation of the photolithography process.

Subsequently, as shown in FIG. 4F, a third insulating layer 49 is formed on the resultant including the upper electrode 48, and then the third insulating layer 49 is selectively etched to form the upper electrode ( A second contact hole 50 exposing a portion of the 48 is formed.

Next, as shown in FIG. 4G, the second contact hole 50 is filled with a conductive film to form an upper electrode contact 51. In this case, the upper electrode contact 51 is made of any one material of W and TiW.

Thereafter, a word line 52 connected to the upper electrode contact 51 is formed on the third insulating layer 49 including the upper electrode contact 51.                     

The phase change memory device according to the present invention manufactured by the above process applies an etch back process to an insulating film pattern formed on a lower electrode, exposing an upper edge portion of the lower electrode, and then By forming the contact surface with the phase change film, the contact area between the lower electrode and the phase change film can be formed in a dimension lower than the limit of the conventional photo process.

As described above, the present invention etches back the insulating layer pattern formed on the lower electrode to partially expose the upper edge portion of the lower electrode, and then forms a contact surface with the phase change layer pattern on the exposed portion. That is, according to the present invention, by applying an etch back process to the insulating layer pattern formed on the lower electrode, the contact area between the lower electrode and the phase change layer pattern can be formed to a lower dimension than in the related art.

Therefore, the present invention can lower the amount of current required for the phase change of the phase change film and can also improve the driving speed capability of the phase change memory element.

Claims (6)

A first insulating film formed on a semiconductor substrate including a predetermined substructure and having a first contact hole exposing a predetermined portion of the substrate; A lower electrode contact filling the first contact hole; A lower electrode formed on the first insulating layer including the lower electrode contact and connected to the lower electrode contact and having first spacers on both side walls thereof; A second insulating layer pattern formed on the lower electrode and exposing an upper edge portion of the lower electrode and having second spacers on both side walls; A stepped phase change layer pattern formed on the first insulating layer and covering upper surfaces of one side of the lower electrode and second insulating layer patterns and adjacent first and second spacers; An upper electrode formed on the phase change layer pattern; A third insulating layer formed on the resultant including the upper electrode and having a second contact hole exposing a portion of the upper electrode; An upper electrode contact filling the second contact hole; And a word line formed on the third insulating layer and connected to the upper electrode contact. The phase change memory device as claimed in claim 1, wherein the phase change film pattern is formed of any one of a GeSb2Te4 film and a Ge2Sb2Te5 film. The phase change memory device as claimed in claim 1, wherein the second insulating pattern includes one of a nitride film and an oxide film. The phase change memory device as claimed in claim 1, wherein the first and second spacers are formed of a nitride film. The phase change memory device as claimed in claim 1, wherein the upper electrode contact is made of one of W and TiW. Forming a first insulating layer on a semiconductor substrate including a predetermined substructure, and then selectively etching the first insulating layer to form a first contact hole exposing a portion of the substrate; Filling the first contact hole with a conductive film to form a lower electrode contact; Sequentially forming a lower electrode and a second insulating layer pattern connected to the lower electrode contact on the first insulating layer including the lower electrode contact; Etching back the second insulating film pattern to expose the upper edge portion of the lower electrode; Forming first and second spacers on both sidewalls of the lower electrode and the second insulating layer pattern remaining after the etch back; Sequentially forming a phase change film and an upper electrode conductive film on the entire surface of the resultant product; A step change phase pattern and an upper step shape covering the first and second spacers adjacent to the upper surface and one side of the lower electrode and the second insulating layer pattern by selectively etching the upper electrode conductive layer and the phase change layer Forming an electrode; Forming a third insulating layer on the resultant including the upper electrode, and selectively etching the third insulating layer to form a second contact hole exposing a portion of the upper electrode; Forming an upper electrode contact to fill the second contact hole; And And forming a word line connected to the upper electrode contact.

Images