KR101038311B1 - Phase-change memory device and method for manufacturing the same - Google Patents

Abstract

The present invention can reduce the amount of current required for the phase change of the phase change film by reducing the contact area between the phase change film and the upper and lower electrodes, and can improve the driving speed capability of the phase change memory device. A phase change memory device and a method of manufacturing the same are disclosed. The disclosed phase change memory device includes a first insulating film having a first contact hole formed on a semiconductor substrate including a predetermined substructure and exposing a predetermined portion of the substrate, and filling the first contact hole. A lower electrode contact, a lower electrode formed to be connected to the lower electrode contact on the first insulating layer including the lower electrode contact, and formed on the first insulating layer including the lower electrode to expose a portion of the lower electrode; A second insulating layer having a second contact hole, a phase change layer pattern filling the second contact hole, and an upper electrode formed to be connected to the phase change layer pattern on the second insulating layer including the phase change layer pattern. It is characterized by including.

Description

Phase change memory device and its manufacturing method {PHASE-CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a graph for explaining a method of programming and erasing a phase change memory device.

2 is a cross-sectional view for explaining a conventional phase change memory element.

3 is a cross-sectional view illustrating a phase change memory device according to an embodiment of the present invention.

4A to 4H are cross-sectional views illustrating processes for manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

Explanation of symbols on main parts of drawing

40: semiconductor substrate 41: first insulating film

42: first contact hole 43: lower electrode contact

44 conductive film for lower electrode 45 second insulating film

46: third insulating film 44a: lower electrode

45a: second insulating film remaining after etching 46a: third insulating film remaining after etching

45b: second insulating film pattern 47: fourth insulating film

48: second contact hole 49: phase change film pattern

50: upper electrode A: contact portion

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, by reducing the contact area between the phase change film and the upper and lower electrodes, thereby reducing the amount of current required for the phase change of the phase change film, A phase change memory device for improving driving speed capability and a method for manufacturing the same.

Semiconductor memory devices, such as DRAM (dynamic random access memory) and SRAM (static random access memory (SRAM)), are volatile and fast data input / output (RAM) products that lose data over time. Once the data is entered, it can be maintained, but it can be divided into read only memory (ROM) products that have slow input / output data. Such typical memory elements represent logic '0' or logic '1' depending on the stored charge.

Here, the DRAM, which is a volatile memory device, requires high charge storage capability because periodic refresh operation is required, and thus many efforts have been made to increase the surface area of a capacitor electrode. However, increasing the surface area of the capacitor electrode makes it difficult to increase the integration of the DRAM device.

On the other hand, nonvolatile memory devices have almost indefinite storage capacities, and in particular, there is an increasing demand for flash memory devices that can be electrically input and output such as EEPROM (elecrtically erasable and programmable ROM).

Such flash memory cells generally have a vertically stacked gate structure with a floating gate formed on a silicon substrate. The multilayer gate structure typically includes one or more tunnel oxide or dielectric films and a control gate formed on or around the floating gate, wherein the principle of writing or erasing data in the flash memory cell is based on It uses a method of tunneling charges through. At this time, a higher operating voltage than the power supply voltage is required. As a result, the flash memory elements require a boosting circuit to form a voltage necessary for writing and erasing operations.

Therefore, many efforts have been made to develop a new memory device having a non-volatile characteristic, random access, and a simple structure while increasing the integration of the device. A representative example is a phase change random access memory (PRAM). to be.

The phase change memory device widely uses a chalcogenide film as a phase change film. In this case, the chalcogenide film is a compound film containing germanium (Ge), stevidium (Sb), and tellurium (Te) (hereinafter referred to as a 'GST film'), wherein the GST film is provided with a current, that is, Joule According to joule heat, the switch is electrically switched between an amorphous state and a crystalline state.

1 is a graph for explaining a method of programming and erasing a phase change memory device, in which the horizontal axis represents time and the vertical axis represents temperature applied to the phase change film.

As shown in FIG. 1, when the phase change film is heated at a temperature higher than the melting temperature (Tm) for a short time (first operating period; t ₁ ) and then cooled rapidly (quenching), the phase change film is amorphous. Change to an amorphous state (see curve 'A'). On the contrary, the phase change film is heated at a temperature lower than the melting temperature Tm and higher than the crystallization temperature Tc for a longer time than the first operating period t ₁ (second operating period; t ₂ ). Upon cooling, the phase change film changes to a crystalline state (see curve 'B').

Here, the resistivity of the phase change film having an amorphous state is higher than that of the phase change film having a crystalline state. Therefore, by sensing the current flowing through the phase change film in the read mode, it is possible to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

As described above, Joule heat is required for the phase change of the phase change film. In a conventional phase change memory device, when a high density of current flows through an area in contact with a phase change film, the crystal state of the phase change film contact surface changes, and the smaller the contact surface changes the state of the phase change material. The required current density is small.

2 is a cross-sectional view illustrating a conventional phase change memory device.

As shown in FIG. 2, the conventional phase change memory device includes a semiconductor substrate 10 having a bottom electrode 11 formed thereon, and a bottom electrode 11 formed on the bottom electrode 11. A first insulating film 12 having a first contact hole 13 exposing a predetermined portion of the substrate, a bottom electrode contact 14 filling the first contact hole 13, and the bottom electrode A second insulating film 15 having a second contact hole 16 formed on the first insulating film 12 including the contact 14 to expose the lower electrode contact 14, and the second contact hole ( And a top electrode 18 formed on the second insulating layer 15 including the phase change layer 17.

In the conventional phase change memory device, when a current flows between the lower electrode 11 and the upper electrode 18, the contact surface 19 between the lower electrode contact 14 and the phase change film 17 passes through. The crystal state of the phase change film of the contact surface 19 changes according to the current intensity (ie, heat). At this time, the heat required to change the state of the phase change film is directly affected by the contact surface 19 of the phase change film 17 and the lower electrode contact 14. Therefore, the contact area between the phase change film 17 and the lower electrode contact 14 should be as small as possible.

However, in the conventional phase change memory device, since the lower electrode 11 and the phase change film 17 are connected through the lower electrode contact 14, the phase change film 17 and the lower electrode contact 14 are connected. The contact area between) is entirely limited by the photo process limits for the contact hole, which makes it difficult to reduce the contact area. As a result, the amount of current required for the phase change is increased, and the driving speed capability of the phase change memory device is degraded.

Accordingly, the present invention has been made to solve the above problems, by reducing the contact area between the phase change film and the upper and lower electrodes, it is possible to lower the amount of current required for the phase change of the phase change film, It is an object of the present invention to provide a phase change memory device capable of improving the driving speed capability and a manufacturing method thereof.

A phase change memory device of the present invention for achieving the above object is a first insulating film formed on a semiconductor substrate including a predetermined substructure and having a first contact hole for exposing a predetermined portion of the substrate, A lower electrode contact filling the first contact hole, a lower electrode formed to be connected to the lower electrode contact on the first insulating layer including the lower electrode contact, and formed on the first insulating layer including the lower electrode; A second insulating layer having a second contact hole exposing a portion of the lower electrode, a phase change layer pattern filling the second contact hole, and the phase change layer pattern on the second insulating layer including the phase change layer pattern It characterized in that it comprises an upper electrode formed to be connected to.

Here, the phase change film pattern is made of any one of a GeSb2Te4 film and a Ge2Sb2Te5 film. In addition, the diameter of the phase change film pattern is 0.1 μm or less.

In addition, a method of manufacturing a phase change memory device according to the present invention for achieving the above object includes a first insulating film having a first contact hole for exposing a predetermined portion of the substrate on a semiconductor substrate including a predetermined substructure. Forming; Filling the first contact hole with a conductive film to form a lower electrode contact; Forming a conductive film for a lower electrode on the first insulating layer including the lower electrode contact; Sequentially forming a second insulating layer and a third insulating layer having different etching rates on the lower electrode conductive layer; Selectively etching the third insulating film, the second insulating film and the conductive film for the lower electrode to form a lower electrode connected to the lower electrode contact; Selectively etching the second insulating layer remaining after the etching to form a second insulating layer pattern; Forming a fourth insulating film over the resulting substrate; CMP of the resultant until the second insulating pattern is exposed; Selectively removing the second insulating layer pattern to form a second contact hole exposing a portion of the lower electrode; Forming a phase change layer pattern filling the second contact hole; And forming an upper electrode on the fourth insulating layer to be connected to the phase change layer pattern.

The second insulating layer may be formed of an oxide layer having a higher etching rate than the third insulating layer, and the second insulating layer may be any one selected from the group consisting of HDP, USG, SOG, TEOS, BPSG, PSG, and HLD oxide. In the forming of the second insulating layer pattern, the second insulating layer remaining after the etching is wet-etched to have a diameter of 0.1 μm or less.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view illustrating a phase change memory device according to an exemplary embodiment of the present invention.

As shown in FIG. 3, a phase change memory device according to an exemplary embodiment of the present invention is formed on a semiconductor substrate 20 including a predetermined substructure (not shown), thereby forming a predetermined portion of the substrate 40. The first insulating layer 41 having the first contact hole 42 to be exposed, the lower electrode contact 23 filling the first contact hole 22, and the first electrode including the lower electrode contact 23. A lower electrode 24a formed on the insulating film 21 to be connected to the lower electrode contact 23, a second insulating film 27 formed on the first insulating film 21 including the lower electrode 24a; A second contact hole 28 formed in the second insulating layer 27 to expose a portion of the lower electrode 24a, a phase change layer pattern 29 filling the second contact hole 28, and The upper electrode 30 is formed on the second insulating layer 27 including the phase change layer pattern 29 to be connected to the phase change layer pattern 29.

Here, the lower electrode contact 23 and the upper electrode 30 are both made of one of polysilicon and metal based materials. The phase change layer pattern 29 is formed of a GST layer, and in this case, any one of the GeSb 2 Te 4 layer and the Ge 2 Sb 2 Te 5 layer may be used as the GST layer.

In addition, the phase change film pattern 29 has a diameter of a small size of 0.1㎛ or less. In addition, contact portions A of the upper electrode 30 and the lower electrode 24a are formed on upper and lower surfaces of the phase change layer pattern 29, and between the lower electrode 24a and the upper electrode 30. When a current flows, a phase change of the phase change layer pattern 29 occurs at a contact surface between the lower electrode 24a and the phase change layer pattern 29.

Meanwhile, a contact area between the phase change film pattern 29 and the upper electrode 30 and the lower electrode 24a on the upper and lower surfaces thereof is proportional to the diameter of the phase change film pattern 29. Since the phase change film pattern 29 has a small diameter of 0.1 μm or less, the contact surface between the phase change film pattern 29 and the lower electrode 24a on the lower surface thereof has a narrow width. . Therefore, the amount of current required for the phase change of the phase change film pattern 29 can be lowered, and the driving speed capability of the phase change memory element can be improved.

Hereinafter, a method of manufacturing the phase change memory device shown in FIG. 3 will be described.

4A to 4H are cross-sectional views illustrating processes of manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

In a method of manufacturing a phase change memory device according to an embodiment of the present invention, as shown in FIG. 4A, a predetermined portion of the substrate 40 is formed on a semiconductor substrate 40 including a predetermined substructure (not shown). The first insulating layer 41 having the first contact hole 42 exposing the light emitting layer is formed. Subsequently, the first contact hole 42 is filled with a conductive film to form a lower electrode contact 43. Here, the lower electrode contact 43 is made of one of polysilicon and metal based materials.

Then, a lower electrode conductive film 44 is formed on the first insulating layer 41 including the lower electrode contact 43. Thereafter, the second insulating layer 45 and the third insulating layer 46 having different etching rates are sequentially formed on the lower electrode conductive layer 44. Here, the second insulating layer 45 is formed of an oxide film having a higher etching rate than the third insulating layer 46, wherein the second insulating layer 45 is made of HDP, USG, SOG, TEOS, BPSG, PSG, and HLD. It is made of any one selected from the group consisting of oxide films.                     

Then, as shown in FIG. 4B, the third insulating layer, the second insulating layer, and the conductive layer for the lower electrode are selectively etched to form a lower electrode 44a connected to the lower electrode contact 43. In this case, reference numerals 45a and 46a, which are not described with reference to FIG. 4B, indicate the second insulating film remaining after etching and the third insulating film remaining after etching, respectively.

Next, as shown in FIG. 4C, the second insulating layer remaining after the etching is selectively etched to form a second insulating layer pattern 45b between the lower electrode 44a and the third insulating layer 46a remaining after the etching. ). At this time, the second insulating film remaining after the etching is wet-etched to have a diameter of a small size of 0.1㎛ or less to form the second insulating film pattern 45b.

Thereafter, as shown in FIG. 4D, a fourth insulating layer 41 is disposed on the first insulating layer 41 including the lower electrode 44a, the second insulating layer pattern 45b, and the third insulating layer 46a remaining after etching. Form 47.

Subsequently, as shown in FIG. 4E, the resultant is subjected to chemical mechanical polishing (CMP) until the second insulating layer pattern 45b is exposed.

Next, as shown in FIG. 4F, the second insulating layer pattern is selectively removed to form a second contact hole 48 exposing a portion of the lower electrode 44a. In this case, since the second insulating layer pattern is formed by removing the second insulating layer pattern, the second contact hole 48 has the same diameter as that of the second insulating layer pattern, that is, a diameter having a small size of 0.1 μm or less.                     

Subsequently, as shown in FIG. 4G, after forming a phase change film (not shown) on the fourth insulating film 47 to fill the second contact hole 48, the fourth insulating film 47 is formed. The phase change layer is etched until it is exposed to form a phase change layer pattern 49 in the second contact hole 48. Here, the phase change film is made of a GST film. At this time, any one of the GeSb2Te4 film and the Ge2Sb2Te5 film is used as the GST film.

On the other hand, since the phase change film pattern 49 is formed to fill the second contact hole 48, the diameter of the second contact hole 48 is the same as the diameter of the second contact hole 48, that is, a diameter of a small size of 0.1 μm or less. Will have

Subsequently, as shown in FIG. 4H, an upper electrode conductive film (not shown) is formed on the fourth insulating film 47 including the phase change film pattern 49. Thereafter, the upper electrode conductive layer is selectively etched to form the upper electrode 50 on the fourth insulating layer 47 so as to be connected to the phase change layer pattern 49. Here, the conductive film for the upper electrode is made of any one of polysilicon-based and metal-based. In addition, contact portions A of the upper electrode 50 and the lower electrode 44a are formed on upper and lower surfaces of the phase change layer pattern 49, and between the lower electrode 44a and the upper electrode 50. When a current flows, a phase change of the phase change layer pattern 49 occurs at a contact surface between the lower electrode 44a and the phase change layer pattern 49. Here, the contact area between the phase change film pattern 49 and the upper electrode 50 and the lower electrode 44a respectively present on the upper and lower surfaces thereof is proportional to the diameter of the phase change film pattern 49. Since the phase change film pattern 49 has a small diameter of 0.1 μm or less, the contact surface between the phase change film pattern 49 and the lower electrode 44a present on the bottom surface thereof has a narrow width. do.

Therefore, the amount of current required for the phase change of the phase change film pattern 49 can be lowered, and the driving speed capability of the phase change memory element can be improved.

As described above, according to the present invention, a phase change layer pattern having a diameter of less than 0.1 μm is disposed between the upper electrode and the lower electrode so as to reduce the contact area between the phase change layer and the upper and lower electrodes. That is, since the contact surface between the phase change film pattern and the upper and lower electrodes has a small size of 0.1 µm or less in diameter, the area of the contact surface can be made smaller.

Therefore, the present invention can lower the amount of current required for the phase change of the phase change film, as well as improve the driving speed capability of the phase change memory element.

Claims (7)

delete delete delete Forming a first insulating film having a first contact hole exposing a predetermined portion of the substrate on a semiconductor substrate including a predetermined substructure; Filling the first contact hole with a conductive film to form a lower electrode contact; Forming a conductive film for a lower electrode on the first insulating layer including the lower electrode contact; Sequentially forming a second insulating layer and a third insulating layer having different etching rates on the lower electrode conductive layer; Selectively etching the third insulating layer, the second insulating layer, and the conductive layer for the lower electrode to form a lower electrode connected to the lower electrode contact; Selectively etching the second insulating layer remaining after the etching to form a second insulating layer pattern; Forming a fourth insulating layer on the entire surface of the substrate product on which the second insulating pattern is formed; CMPing the third and fourth insulating films until the second insulating pattern is exposed; Selectively removing the exposed second insulating layer pattern to form a second contact hole exposing a portion of the lower electrode; Forming a phase change layer pattern filling the second contact hole; And And forming an upper electrode on the fourth insulating layer to be connected to the phase change layer pattern. delete 5. The method of claim 4, wherein the second insulating film is one selected from the group consisting of HDP, USG, SOG, TEOS, BPSG, PSG, and HLD oxide films. The method of claim 4, wherein the forming of the second insulating layer pattern comprises wet etching the second insulating layer remaining after the etching to have a diameter of 0.1 μm or less.

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