KR20060001376A - Method and apparatus for driving plasma display panel - Google Patents

Abstract

An object of the present invention is to reduce the stress of an address driver.

In order to achieve the above object, the present invention has a front substrate and a rear substrate spaced apart from each other, the sustain electrodes and the scan electrodes are formed parallel to each other between the substrate, the address electrode lines and the sustain electrode and For a plasma display panel formed to intersect the scan electrode lines, the unit frame is divided into a plurality of subfields for time division gray scale display, and reset, addressing, and display-holding steps are performed in each of the subfields. In the driving method and driving apparatus of the discharge display panel,

In the addressing step, a scan signal having a scan voltage is sequentially applied to the scan electrode lines for a predetermined time, and the address electrode lines correspond to a time when a scan voltage is applied to the at least two scan electrode lines. Provided are a driving method and a driving apparatus of a plasma display panel, wherein a display data signal having a pulse width is applied to each other.

Description

Driving method and driving apparatus for plasma display panel {Method and apparatus for driving plasma display panel}

1 is a view showing the structure of a conventional three-electrode surface discharge plasma display panel.

FIG. 2 shows a typical driving apparatus of the plasma display panel shown in FIG. 1.

FIG. 3 is a circuit diagram illustrating the address driver shown in FIG. 2.

FIG. 4 is a timing diagram for explaining an example of a drive signal of the panel shown in FIG. 1.

FIG. 5 is a timing diagram illustrating a display data signal applied to a first address electrode with a pulse width corresponding to a time when a scan voltage is applied to two or more scan electrode lines.

FIG. 6 is a timing diagram illustrating a display data signal applied to a second address electrode with a pulse width corresponding to a time when a scan voltage is applied to two or more scan electrode lines according to another exemplary embodiment of the present invention.

FIG. 7 is a timing diagram illustrating a display data signal applied to an m-th address electrode having a pulse width corresponding to a time when a scan voltage is applied to two or more scan electrode lines according to another embodiment of the present invention. to be.

8 is a block diagram schematically illustrating a driving apparatus of a plasma display panel according to the present invention.

Explanation of symbols on main parts of drawing

200 ... Image Processing Unit

202 Logic Controller

204 ... Y drive

206 ... address drive

208 ... X drive

206a ... power regenerative circuit

Vscan ... scan voltage

Va ... address voltage

t ₀ ... scan voltage application time

800 ... load rate detection unit

802 ... switching timing adjustment

The present invention relates to a method and a driving apparatus for a plasma display panel, and more particularly, to a method and a driving apparatus for a plasma display panel for reducing the stress of the address driving apparatus.

1 is a view showing the structure of a conventional three-electrode surface discharge plasma display panel.

Referring to FIG. 1, between the front and rear glass substrates 100 and 106 of a conventional surface discharge plasma display panel 1, the address electrode lines A ₁ ,. A ₂ , ..., A _m ), Dielectric layers 102 and 110, Y electrode lines Y ₁ , ..., Y _n , X electrode lines X ₁ , ..., X _n , fluorescent layer 112, barrier rib 114, and As a protective layer, the magnesium monoxide (MgO) layer 104 is provided, for example.

Address electrode lines A ₁ , A ₂ , ..., A _m ) is formed in a predetermined pattern on the front side of the rear glass substrate 106. The lower dielectric layer 110 includes the address electrode lines A ₁ ,. A ₂ , ..., A _m ) is applied to the front. In front of the lower dielectric layer 110, barrier ribs 114 may include address electrode lines A ₁ ,. A ₂ , ..., A _m ) is formed in a direction parallel to. The partition walls 114 function to partition a predetermined area of each display cell and to prevent optical interference between each display cell. The fluorescent layer 112 is formed between the partition walls 114.

The X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ , ..., Y _n are the address electrode lines A ₁ ,. A ₂ , ..., A _m ) is formed in a predetermined pattern on the back of the front glass substrate 100 to be orthogonal to each other. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) are transparent electrode lines (X _na ) made of a transparent conductive material such as indium tin oxide (ITO). , Y _na ) and metal electrode lines X _nb and Y _nb for increasing conductivity may be formed. The front dielectric layer 102 is formed by applying the entire surface to the rear of the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ ,..., Y _n ). A protective layer 104 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying a front surface to the back of the front dielectric layer 102. The plasma forming gas is sealed in the discharge space 108.

A driving scheme generally applied to such a plasma display panel is a method in which initialization, address, and display holding steps are sequentially performed in a unit sub-field. In the initialization step, the state of charge of the display cells to be driven becomes uniform. In the address step, the charge state of display cells to be selected and the charge state of display cells not to be selected are set. In the display holding step, display discharge is performed in selected display cells. At this time, a plasma is formed from the plasma forming gas of the display cells performing display discharge, and the fluorescent layer 112 of the display cells is excited by ultraviolet radiation from the plasma to generate light.

2 illustrates a general driving device of the plasma display panel of FIG. 1.

Referring to the drawings, a typical driving apparatus of the plasma display panel 1 includes an image processor 200, a logic controller 202, an address driver 206, an X driver 208, and a Y driver. The image processing unit 200 converts an external analog image signal into a digital signal, and internal image signals such as 8-bit red (R), green (G), and blue (B) image data, clock signals, vertical and Generate horizontal sync signals. The address driver 206 processes the address signal SA from the logic controller 202 to generate a display data signal, and applies the generated display data signal to the address electrode lines. The X driver 208 processes the X drive control signal SX from the logic controller 202 and applies it to the X electrode lines. The Y driver 204 processes and applies the Y drive control signal SY from the logic controller 202 to the Y electrode lines.

3 is a circuit diagram illustrating the address driver 206 illustrated in FIG. 2.

The address driver 206 is composed of a power regenerative circuit 206b and an address driver circuit 206a. In general, the address driving circuit may mean the address driving device 206. The power regenerative circuit 206b charges and stores wall charges inside the discharge cells to which the display data signal is applied through the address driver 206 or discharges them into the discharge cells, and switches the switching elements S3 and S4. Power is applied to the address driving circuit. The address driving circuit 206a receives power from the power regenerative circuit 206b and uses the address driving control signal SA to display respective display data signals on the address electrode lines A1, A2, ..., Am. (Sd1, Sd2, ..., Sdm) is applied.

FIG. 4 is a timing diagram for explaining an example of the drive signal of the panel shown in FIG. 1 and is applied to the address electrode A, the sustain electrode X, and the scan electrodes Y1 to Yn in one subfield SF. The drive signal to be displayed. Referring to FIG. 4, one subfield SF includes a reset period PR, an address period PA, and a sustain discharge period PS.

The reset period PR applies a reset pulse to all of the scan lines of all groups and forcibly performs a write discharge, thereby initializing the wall charge states of all cells. The address period PA is performed after the reset period PR is performed. At this time, in the address period PA, the bias voltage Vb is applied to the sustain electrode X, and the scan electrodes Y1 to Yn and the address electrodes A1 to Am are simultaneously turned on at the cell positions to be displayed. Select the cell. After the address period PA is performed, the sustain pulse Vs is alternately applied to the sustain electrodes X and the scan electrodes Y1 to Yn to perform the sustain discharge period PS. During the sustain discharge period PS, a low level voltage Vg is applied to the address electrodes A1 to Am. In PDP, the brightness is adjusted by the number of sustain discharge pulses. If the number of sustain discharge pulses in one subfield or one TV field is large, the luminance increases.

In order to generate the display data signal applied to the address electrode of FIG. 4 using the power regenerative circuit 206b in the address driver 206 of FIG. 3, the switching elements (S3, S4 in FIG. 3) of the power regenerative circuit are generated. Power is supplied to the address driving circuit 206b by turning on / off, and the display data signal is provided for each address electrode line A1, A2, ..., Am using the address driving control signal SA. (Sd1, Sd2, ..., Sdm) is applied. Conventionally, a negative scan voltage is sequentially applied to each scan electrode for a predetermined time, and a display data signal having a pulse width of the predetermined time is applied to the address electrode. As the number of lines of the scan electrodes increases, the predetermined time for applying the scan voltage to the scan electrodes gradually decreases, and accordingly, the pulse width of the display data signal output from the address driver decreases. That is, the switching time of the switching element in the power regenerative circuit is shortened, and as a result, the stress of the power regenerative circuit element of the address driver 206 is increased, such as noise caused by high-speed switching.

An object of the present invention is to provide a driving method and a driving apparatus of a plasma display panel for reducing the stress of the address driving apparatus.

In order to achieve the above object, the present invention has a front substrate and a rear substrate spaced apart from each other, the sustain electrodes and the scan electrodes are formed parallel to each other between the substrate, the address electrode lines are the sustain electrode and the scan For the plasma display panel formed to intersect the electrode lines, the unit frame is divided into a plurality of subfields for time division gray scale display, and discharges in which the reset, addressing, and display-holding steps are performed in each of the subfields are performed. In the driving method of the display panel,

In the addressing step, a pulse width corresponding to a time when a scan signal having a scan voltage is sequentially applied to the scan electrode lines for a predetermined time and the scan voltage is applied to the two or more scan electrode lines to the address electrode lines are sequentially applied. The present invention provides a method of driving a plasma display panel, wherein each of the display data signals is applied.

According to another aspect of the present invention, the display data signal having the pulse width can be applied according to the detected load ratio by detecting the load ratio for each address electrode line.

According to another aspect of the present invention, the display data signal having the pulse width can be applied to the detected load rate by detecting the load rate for each subfield.

According to this still further aspect of the present invention, the display data signal having the pulse width can be applied according to the detected load ratio by detecting the load ratio for each frame.

The present invention also provides a load factor detection unit for detecting a load factor in order to achieve the above object; A switching timing adjusting unit outputting a control signal for adjusting the switching timing of the address driving circuit according to the detected load ratio; And an address driver circuit for switching the pulse width of the display data signal having the address voltage according to a control signal of the switching timing adjusting unit and applying the display data signal to address electrode lines, respectively. do.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

FIG. 5 is a timing diagram illustrating a display data signal applied to a first address electrode with a pulse width corresponding to a time when a scan voltage is applied to two or more scan electrode lines.                     

FIG. 6 is a timing diagram illustrating a display data signal applied to a second address electrode with a pulse width corresponding to a time when a scan voltage is applied to two or more scan electrode lines according to another exemplary embodiment of the present invention.

7 is a timing diagram illustrating a display data signal applied to an m-th address electrode having a pulse width corresponding to a time when a scan voltage is applied to two or more scan electrode lines according to another embodiment of the present invention. .

Referring to FIGS. 5 to 7, first, in FIG. 5A, a discharge cell is partitioned by a scan electrode and a sustain electrode of a plasma display panel and an address electrode disposed to intersect the scan electrode and the sustain electrode. The figure shows the application of a scan signal having a scan voltage Vscan for a predetermined time t ₀ sequentially to (Y1, Y2, ..., Yn).

For example, if discharge is to be performed on all the scan electrodes Y1, Y2, ..., Yn among the first address electrode lines A1, that is, if the load ratio of the first address electrode lines A1 is 100%, Conventionally, as shown in FIG. 5B, a display data signal having a pulse width for a predetermined time t ₀ when a scan voltage Vscan is applied to a scan electrode is applied to the first address electrode A1. . The pulse width of the display data signal is determined according to the switching time of the switching element of the power regenerative circuit included in the address driver. Therefore, as the number of scan electrode lines increases, the switching time of the switching element decreases, so that the stress of the power regenerative circuit element of the address driver 206 increases.

In order to solve this problem, the present invention is characterized in that each of the display data signals having a pulse width corresponding to the time 2t _{0 at} which the scan voltage is applied to two or more scan electrode lines is applied.

As shown in FIG. 5C, the pulse width of the display data signal corresponds to the time 2t ₀ when the scan voltage is applied to the two scan electrode lines so that the scan is performed every two scan electrode lines. . This can be implemented by controlling the switching time of the switching elements (S3, S4 of FIG. 3) of the power regenerative circuit element of the address driver 206, and the switching timing is longer than in the related art. Therefore, the stress of the power regenerative circuit element of the address driver by the high speed switching is reduced.

In addition, the pulse width of the display data signal may be defined as the time 3t ₀ when the scan voltage is applied to the three scan electrode lines.

FIG. 6A illustrates a case where the discharge cells to be turned on at the second address electrode A2 correspond to the third scan electrode Y3 to the sixth scan electrode Y6. In the related art, a display data signal having a pulse width corresponding to the pulse width of FIG. 6 (b), that is, a time t ₀ at which the scan voltage Vscan is applied to the scan electrode is applied. A display data signal having a pulse width of (c), that is, a pulse width corresponding to the sum of the time 2t ₀ when the scan voltage is applied to the two scan electrodes is applied. It is implemented by switching of switching elements (S3, S4 in FIG. 3) of the power regenerative circuit (206b in FIG. 3) in the address driver to generate the display data signal having the pulse width.

FIG. 7A illustrates a case where the discharge cells to be turned on at the mth address electrode Am correspond to the fifth scan electrode Y5 to the sixth scan electrode Y6. Conventionally, a display data signal having a pulse width corresponding to the pulse width of FIG. 7 (b), that is, the time t _{0 at} which the scan voltage is applied to the scan electrode is applied. In connection with the present invention, FIG. A display data signal having a pulse width of, i.e., a pulse width corresponding to the time 2t _{0 at} which the scan voltage is applied to the two scan electrodes is applied. It is implemented by switching of switching elements (S3, S4 in Fig. 3) of the power regenerative circuit in the address driver to generate the display data signal having the pulse width.

As another embodiment of the present invention, if the load rate is detected for each address electrode line, and if the detected load rate is greater than the predetermined load rate, the pulse width corresponds to the time (2t ₀ ) at which the scan voltage is applied to the two scan electrodes. The display data signal can be applied to the address electrode. For example, if the load ratio, which is the ratio of the cells to be turned on among all the cells of the first address electrode A1, is detected in advance and larger than the predetermined load ratio, the display data having the pulse width shown in FIG. Apply a signal. In addition, if the load ratio of the second address electrode A2 is detected in advance and larger than the predetermined load ratio, the display data signal having the pulse width shown in FIG. 6C may be applied. In this manner, the mth address may be applied. The load ratio is detected for each address electrode line up to the electrode Am, and a display data signal having a pulse width shown in FIG. 7C is applied. The display data signal having the above pulse width can be implemented by switching the switching elements (S3 and S4 in FIG. 3) of the power regenerative circuit in the address driver.

According to another embodiment of the present invention, a display data signal having a pulse width corresponding to a time 2t ₀ when a scan voltage is applied to two scan electrodes according to the detected load rate by detecting a load rate for each subfield is applied to the address electrode. Can be authorized. The load ratio for each subfield may be obtained as a ratio of cells to be turned on among all cells of the panel, or may be obtained as an average of the load rates for each address electrode line.

In another embodiment of the present invention, a load rate is detected for each frame and a display data signal having a pulse width corresponding to a time (2t ₀ ) at which a scan voltage is applied to two scan electrodes is applied to the address electrode according to the detected load rate. can do. The load rate for each frame may be obtained as an average of the load rates for each subfield.

8 is a block diagram schematically illustrating a driving apparatus of a plasma display panel according to the present invention.

The present invention provides a driving apparatus of a plasma display panel for reducing the stress of the address driving apparatus. To this end, FIG. 8 includes an image processor 200, a logic controller 202, an X driver 208, an address driver 206, and a Y driver 204.

The image processor 200 receives an external image signal, processes the signal, and outputs the signal as an internal image signal, and the logic controller 202 receives the internal image signal and performs address correction through gamma correction and automatic power control (APC) steps. The control signal SA, the X drive control signal SX, and the Y drive control signal SY are output. In particular, in connection with the present invention, the logic controller 202 adjusts the switching timing for controlling the switching operation of the switch element of the power regenerative circuit of the address driver 206 by the load rate detector 800 for detecting the load rate and the detected load rate. The unit 802 is provided. The detection of the load rate may be a load rate detection for each address electrode line, a load rate detection for each subfield, or a load rate detection for each frame. If it is determined that the detected load ratio is greater than or equal to the predetermined load ratio, the pulse width of the display data signal output through the address driving circuit 206 may be changed in order to reduce the stress of the power regenerative circuit element of the address driving circuit 206. For example, referring to FIG. 5, a display data signal having a pulse width corresponding to a time 2t ₀ when a scan voltage is applied to two scan electrodes may be output from the address driver 206.

 The X driver 208 and the Y driver 204 receive the driving control signals SX and SY and output driving signals to the sustain electrode X and the scan electrode Y of the panel, respectively.

The address driver 206 outputs a display data signal to the address electrode, and in accordance with the present invention, the control signal from the switching timing adjusting unit 802 according to the load ratio detected from the load rate detecting unit 800 in the logic controller 202. The input signal is controlled to control the operation of the switching element in the power regenerative circuit. In order to reduce the stress of the power regenerative circuit element, for example, as shown in FIG. 5C, the display data signal has a pulse width corresponding to the time 2t ₀ when the scan voltage is applied to the two scan electrodes. Therefore, the switching speed of the switching element can be lowered.

According to the present invention as described above, the following effects can be obtained.

By controlling the switching time of the switching element for supplying the address voltage of the power regenerative circuit, in order to apply the display data signal having the pulse width corresponding to the time when the scan voltage is applied to two or more scan lines as in the present invention, The stress of the switching element in the address drive circuit is reduced. In addition, this enables stable circuit driving, thereby improving the reliability of the plasma display panel.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (5)

In a plasma display panel having a front substrate and a rear substrate spaced apart from each other, the sustain electrodes and the scan electrodes are formed parallel to each other between the substrates, and the address electrode lines cross the sustain electrode and the scan electrode lines. In the driving method of the discharge display panel, wherein the unit frame is divided into a plurality of subfields for time division gray scale display, and the reset, addressing, and display-holding steps are performed in each of the subfields. In the addressing step, a scan signal having a scan voltage is sequentially applied to the scan electrode lines for a predetermined time, and the address electrode lines correspond to a time when a scan voltage is applied to the at least two scan electrode lines. And a display data signal having a pulse width, respectively. The display data signal of claim 1, wherein the display data signal having the pulse width comprises: And a load ratio is detected for each of the address electrode lines and applied according to the detected load ratio. The display data signal of claim 1, wherein the display data signal having the pulse width comprises: And detecting a load ratio for each of the subfields and applying the load ratio according to the detected load ratio. The display data signal of claim 1, wherein the display data signal having the pulse width comprises: And detecting a load ratio for each frame and applying the load ratio according to the detected load ratio. A load rate detector for detecting a load rate; A switching timing adjusting unit outputting a control signal for adjusting the switching timing of the address driving circuit according to the detected load ratio; And And an address driver circuit for switching the pulse width of the display data signal having an address voltage by the control signal of the switching timing adjusting unit, and applying the display data signal to address electrode lines, respectively.

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