KR100537627B1 - Driving method of plasma display panel - Google Patents

Abstract

An object of the present invention is to provide a method of driving a plasma display panel for reducing reactive power loss in a plasma display panel having a two-electrode structure.

In order to achieve the above object, the present invention provides a plasma display having a front substrate and a rear substrate that are spaced apart from each other, scan electrode lines are formed between the substrates, and the address electrode lines are crossed with respect to the scan electrode lines. About the panel,

(a) a reset step of applying a reset voltage to the scan electrodes for initializing discharge of all cells; (b) an address step of sequentially applying a negative scan voltage for each scan electrode line and selectively applying a positive address voltage to the address electrode lines to select a cell to be turned on; And (c) applying a sustain pulse having a positive sustain discharge voltage and a ground voltage to the scan electrodes to perform sustain discharge in the cell selected in the address step.

The magnitude of the address voltage is smaller than the magnitude of the sustain discharge voltage.

Description

Driving method of plasma display panel {Driving method of plasma display panel}

The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel having a two-electrode structure.

FIG. 1 is a diagram schematically illustrating scan electrode lines and address electrode lines of a plasma display panel having a two-electrode structure.

Referring to the drawings, in the two-electrode structure of the plasma display panel, a plurality of address electrode lines A1, A2, ..., Am are arranged in the upper direction from the top of the panel to the lower direction. A plurality of scan electrode lines Y1, Y2, ..., Yn are disposed to intersect with (A1, A2, ..., Am). The discharge cell Ce is partitioned in an area where the plurality of address electrode lines A1, A2, ..., Am and the plurality of scan electrode lines Y1, Y2, ..., Yn cross each other. An image is displayed on the panel by the discharge in the discharge cell Ce.

Unlike the three-electrode structure, a plurality of intersecting the plurality of address electrode lines A1, A2, ..., Am, and arranged in parallel to the plurality of scan electrode lines Y1, Y2, ..., Yn The sustain electrode lines are not arranged.

2 is a timing diagram showing a conventional driving signal for driving a plasma display panel having a two-electrode structure.

A unit frame for realizing an image on the plasma display panel is divided into a plurality of subfields for time division gray scale display, and each subfield SB includes a reset period PR, an address period PA, and a sustain discharge period PS. Divided.

In the reset period PR, a reset pulse signal having a reset voltage Vr is applied to all of the plurality of scan electrode lines Y1, Y2,..., And Yn in order to initialize the wall charge state in all cells. . The ground voltage Vg is applied to the address electrode. The initialization discharge is performed by the potential difference between the scan electrode and the address electrode A. FIG.

In the address period PA, an address discharge is performed to select a cell to be turned on among all the cells. Scan signals having a negative scan voltage Vscan are sequentially applied to the scan electrodes along the vertical direction of the panel. A display data signal having a positive address voltage Va is applied to the address electrode A in order to select a cell to be turned on according to a negative scan voltage sequentially applied to the scan electrode. When the potential difference between the address voltage Va and the scan voltage Vscan is higher than the discharge start voltage Vf, the address discharge is performed, whereby wall charges are accumulated in the discharge cell selected as the cell to be turned on.

In the sustain discharge period PS, sustain discharge for luminance display is performed in a cell selected as a cell to be turned on in the address period PA. The luminance of the plasma display panel is determined according to the number of sustain discharges. A sustain pulse having a positive sustain discharge voltage Vs and a negative sustain discharge voltage -Vs is alternately applied to the scan electrode Y, and a ground voltage Vg is applied to the address electrode A. The sustain discharge is started by using the sustain discharge voltage Vs applied to the scan electrode and the wall voltage (not shown, Vw) due to wall charges accumulated inside the discharge cell in the address period PA.

Meanwhile, in order to select a cell to be turned on, a display data signal having an address voltage Va must be applied to the address electrode. For example, if the load ratio indicating the percentage of cells to be turned on among all the cells is 100%, that is, if all the cells are selected as the cells to be turned on, the display data signal is continuously applied to the address voltage Va and the ground voltage Vg. Must be a signal with alternating In order to generate such a display data signal in a driving apparatus (for example, an address driver), an address voltage is applied from a power supply (not shown) to be performed by a switching operation of a switching element. At this time, if the energy recovery circuit is not employed in the address driver, the address voltage is applied to the inside of the discharge cell, and then the energy remaining in the discharge cell is not recovered. Must be applied to the discharge cell, resulting in a large loss of reactive power. This means that the larger the size of the address voltage Va is, the larger the loss of reactive power becomes. Even if the load ratio is not 100%, when the size of the address voltage Va is large, the loss of reactive power occurs when the energy recovery circuit is not employed in the address driver. This is because the larger the size of the address voltage Va is, Occurs more seriously.

In order to solve the above problems, an object of the present invention is to provide a plasma display panel driving method for reducing reactive power loss in a plasma display panel having a two-electrode structure.

In order to achieve the above object, the present invention is a plasma having a front substrate and a rear substrate spaced apart from each other, the scan electrode lines are formed between the substrates, the plasma formed so that the address electrode lines cross with respect to the scan electrode lines A driving method of a plasma display panel in which a unit frame is divided into a plurality of subfields for time division gray scale display, and reset, address, and sustain discharge steps are performed in each of the subfields.

(a) a reset step of applying a reset voltage to the scan electrodes for initializing discharge of all cells;

(b) an address step of sequentially applying a negative scan voltage for each scan electrode line and selectively applying a positive address voltage to the address electrode lines to select a cell to be turned on; And

(c) a sustain discharge step of applying a sustain pulse having a positive sustain discharge voltage and a ground voltage to the scan electrodes to perform sustain discharge in the cell selected in the address step;

The magnitude of the address voltage is smaller than the magnitude of the sustain discharge voltage.

According to another aspect of the present invention, the magnitude of the scan voltage may be greater than the magnitude of the sustain discharge voltage.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a block diagram schematically illustrating a driving apparatus of a plasma display panel for implementing a method of driving a plasma display panel of the present invention.

The driving apparatus of the plasma display panel includes an image processing unit 200, a logic control unit 202, a Y driver 9204, an address driver 206, and a plasma display panel 1.

The image processor 200 receives an external image signal such as a PC signal, a DVD signal, a video signal, or a TV signal from the outside, converts an analog signal into a digital signal, and processes the digital signal into an internal image signal. The internal video signals are 8-bit red (R), green (G), and blue (B) image data, clock signals, and vertical and horizontal sync signals, respectively.

The logic controller 202 receives an internal image signal from the image processor 200 and performs an gamma correction, an automatic power control (APC) step, and the like, to respectively output an address driving control signal SA and a Y driving control signal SY. Output

The Y driving unit 204 receives the Y driving control signal SY from the logic control unit 202, and has an erase pulse having an erase voltage for initialization discharge in the reset period, and the up and down directions of the panel 1 in the address period. Accordingly, a scan signal having a negative scan voltage sequentially and a sustain pulse alternately having a positive sustain discharge voltage and a negative sustain discharge voltage are applied to the scan electrode lines of the plasma display panel 1 during the sustain discharge period. do. In connection with the present invention, the scan signal is output from the Y driver as a signal having a scan voltage larger than the sustain discharge voltage.

The address driver 206 receives the address drive control signal SA from the logic controller 202 and outputs a display data signal having an address voltage to a cell to be turned on among all cells in an address period. Output to the electrode lines. In connection with the present invention, the display data signal is output from the address driver as a signal having an address voltage smaller in magnitude than the sustain discharge voltage.

The plasma display panel 1 is a plasma display panel of a two-electrode structure in accordance with the present invention. It will be described in detail below.

On the other hand, the power supply unit (not shown) of the plasma display panel supplies a reset voltage, a scan voltage, a sustain discharge voltage to the scan electrodes, and an address voltage to the address electrodes.

By using the above-mentioned driving apparatus of the plasma display panel, a driving method of the plasma display panel of the two-electrode structure of the present invention is performed.

4 is an exploded perspective view showing a plasma display panel having a two-electrode structure to which the method for driving a plasma display panel of the present invention is applied.

5 is a cross-sectional view taken along line II-II of FIG. 4.

Referring to FIGS. 4 and 5, the plasma display panel 1 includes an upper panel 10 and a lower panel 20.

The upper panel 10 includes a front substrate 11, a plurality of scan electrodes 16 extending in one direction below the front substrate 11, and an upper dielectric layer 14 filling the scan electrodes 16. And an upper protective layer 15 covering the upper dielectric layer 14. The scan electrodes 16 are formed of a metal material having excellent conductivity. Examples of the metal material include aluminum, copper, and silver.

The lower panel 20 includes a rear substrate 21, a plurality of address electrodes 22 formed on an upper surface of the rear substrate 21, a lower dielectric layer 23 filling the address electrodes 22, and the lower dielectric layer. A partition 24 formed on the 23, a phosphor layer 25 applied on the lower dielectric layer 23 over the partition 24, and a lower protective layer 26 formed on the phosphor layer 25. Equipped. The address electrodes 22 are formed in a stripe pattern extending in one direction, and extend in a direction substantially intersecting with an extending direction of the scan electrodes 16.

As shown in FIG. 4, the partition wall 24 may be formed in a matrix shape extending in two orthogonal directions. The partition wall 24 may have optical and electrical crosstalk between adjacent discharge cells 30. to prevent cross-talk. Here, one discharge cell is a space defined by the partition wall, and means one subpixel among red subpixels, green subpixels, and blue subpixels constituting one pixel.

Referring to FIG. 5, in the two-electrode plasma display panel 1 having the above-described configuration, a scan voltage is applied to the scan electrode 16, and an address voltage is applied to the address electrode 22 so that the scan electrode ( By the potential difference between 16 and the address electrode 22, an address discharge occurs, and as a result of this address discharge, a cell 30 in which a sustain discharge occurs is selected. Subsequently, a sustain pulse having an alternating sustain discharge voltage and a negative sustain discharge voltage is applied to the scan electrode 16 of the selected cell 30, thereby providing a gap between the scan electrode 16 and the address electrode 22. The sustain discharge is started by the wall voltage caused by the wall charges in the discharge cells formed in the potential difference and the address period. Ultraviolet rays are emitted while the energy level of the discharged gas excited by this sustain discharge is lowered. The ultraviolet rays excite the phosphor layer 25 coated in the discharge cell 30. As the energy level of the excited phosphor layer 25 decreases, visible light is emitted, and the emitted visible light forms an image.

6 is a timing diagram illustrating a driving signal for explaining a method of driving a plasma display panel of the present invention.

Referring to FIG. 1, first, a reset signal having a reset voltage is applied to all of the scan electrode lines Y1, Y2,. Apply ground voltage (Vg) to both. As the reset voltage Vr, a voltage greater than the discharge start voltage Vf may be applied to perform the initialization discharge. Initializing discharge is performed by the potential difference between the scan electrode to which the reset voltage Vr is applied and the address electrode to which the ground voltage Vg is applied in each discharge cell, and the wall charges in the discharge cells are uniformly distributed throughout. . That is, the reset period PR is a step of preparing the address period PA and the sustain discharge period PS.

Next, in the address period PA, a scan signal having a scan voltage having a negative voltage is sequentially applied to the plurality of scan electrode lines Y1, Y2, ..., Yn in the vertical direction of the panel. . In order to select a cell to be turned on among all the cells in the address period, a display data signal having a positive address voltage Va is applied to the plurality of address electrode lines A1, A2, ..., Am. In the cell selected as the cell to be turned on, the address discharge is performed by the potential difference between the positive address voltage Va of the address electrode and the negative scan voltage Vscan of the scan electrode. Wall charges are accumulated in the cell by the address discharge, and the accumulated wall charges affect the sustain discharge performed in the sustain discharge period PS after the address period PA.

Here, the magnitude of the address voltage Va is applied smaller than the magnitude of the sustain discharge voltage Vs. In addition, the magnitude of the scan voltage Vscan is greater than that of the sustain discharge voltage Vs. The display data signal applies the selection address voltage Va to a cell to be turned on, and when the load ratio indicating the ratio of cells to be turned on out of all the cells becomes large, the display data signal is generated as a signal having a large number of the selection address voltage Va. Done. For example, if the load ratio is 100%, the display data signal is generated as a signal having the address voltage Va and the ground voltage Vg continuously and applied to the discharge cells of the plasma display panel. In such a case, an energy recovery circuit is employed in the address driver 206 that outputs the display data signal to accumulate the remaining charge in the discharge cell as energy and discharge the accumulated energy again. Otherwise, the loss of reactive power becomes large when it is necessary to continuously supply the address voltage Va. This means that the larger the size of the address voltage Va, the greater the loss of reactive power. In order to prevent this, when the energy recovery circuit is not employed in the address driver 206, it is preferable to generate the display data signal by reducing the size of the address voltage Va. Therefore, the present invention is characterized in that the magnitude of the address voltage Va is smaller than the magnitude of the sustain discharge voltage Vs. On the other hand, when the size of the address voltage Va becomes small, in order to perform the address discharge smoothly, the size of the scan voltage Vscan must be increased. Therefore, the present invention is characterized in that the magnitude of the scan voltage Vscan is greater than the magnitude of the sustain discharge voltage Vs.

 Therefore, the display data signal having the address voltage Va smaller than the sustain discharge voltage Vs is applied to the address electrode, and the scan signal having the scan voltage Vscan greater than the sustain discharge voltage Vs is scanned. Is applied to the electrode.

In the sustain discharge period PS, a sustain pulse having positive sustain discharge voltage Vs and negative sustain discharge voltage (-Vs) in all scan electrode lines Y1, Y2, ..., Yn. Apply. Meanwhile, the ground voltage Vg is applied to all of the address electrode lines A1, A2, ..., Am. In the discharge cells in which the address discharge is performed in the address period PA by the sustain pulses applied to the scan electrodes, wall voltages (not shown, Vw) due to accumulated wall charges and the sustain discharge voltages Vs applied are used. The discharge start voltage (not shown, Vf) is easily reached, whereby the sustain discharge is performed. On the other hand, in a cell in which no address discharge has been performed in the address period PA, even when the sustain pulse having the positive sustain discharge voltage Vs and the negative sustain discharge voltage (-Vs) becomes a sustain pulse, the wall charges accumulated in the cell remain. Therefore, the discharge start voltage Vf cannot be reached, and thus sustain discharge is not performed.

On the other hand, the number of sustain discharges in the sustain discharge period PS is proportional to the luminance of the plasma display panel. Therefore, the number of sustain discharges must be increased to realize high brightness.

The reset voltage Vr, the address voltage Va, the scan voltage Vscan, and the sustain discharge voltage Vs used in the driving signals shown in FIG. 6 are all supplied from a power supply unit (not shown). In this regard, an address voltage Va smaller than the magnitude of the sustain discharge voltage Vs should be supplied from the power supply, and a scan voltage Vcan greater than the magnitude of the sustain discharge voltage Vs should be supplied from the power supply.

According to the present invention as described above, the following effects can be obtained.

First, when the energy recovery circuit is not employed in the address driver for supplying the display data signal, the discharge cell is used by using the size of the address voltage smaller than that of the sustain discharge for the display data signal having the largest energy consumption in the address period. The reactive power consumed internally can be reduced.

 Second, the reactive power consumption can be reduced even without employing the energy recovery circuit in the address driver, thereby reducing the manufacturing cost of the plasma display panel.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

FIG. 1 is a diagram schematically illustrating scan electrode lines and address electrode lines of a plasma display panel having a two-electrode structure.

2 is a timing diagram showing a conventional driving signal for driving a plasma display panel having a two-electrode structure.

3 is a block diagram schematically illustrating a driving apparatus of a plasma display panel for implementing a method of driving a plasma display panel of the present invention.

4 is an exploded perspective view showing a plasma display panel having a two-electrode structure to which the method for driving a plasma display panel of the present invention is applied.

5 is a cross-sectional view taken along line II-II of FIG. 4.

6 is a timing diagram illustrating a driving signal for explaining a method of driving a plasma display panel of the present invention.

Explanation of symbols on the main parts of the drawings

Ce ...

Y1, Y2, ..., Yn ... multiple scan electrode lines,

A1, A2, ..., Am ... multiple address electrode lines,

Vr ... reset voltage,

Vscan ... scan voltage,

Va ... address voltage,

Vs ... Dielectric potential voltage,

1 ... plasma display panel,

200 ...

202 Logic controller,

204 ... Y drive unit,

206 ... address drive.

Claims (2)

For a plasma display panel having a front substrate and a rear substrate spaced apart from each other, scan electrode lines are formed between the substrates, and address electrode lines intersect with the scan electrode lines, a time-division gray scale display of a unit frame A method of driving a plasma display panel, which is divided into a plurality of subfields for and in which reset, address, and sustain discharge steps are performed in each of the subfields, (a) a reset step of applying a reset voltage to the scan electrodes for initializing discharge of all cells; (b) an address step of sequentially applying a negative scan voltage for each scan electrode line and selectively applying a positive address voltage to the address electrode lines to select a cell to be turned on; And (c) a sustain discharge step of applying a sustain pulse having a positive sustain discharge voltage and a ground voltage to the scan electrode to perform sustain discharge in the cell selected in the address step; And the magnitude of the address voltage is smaller than the magnitude of the sustain discharge voltage. The method of claim 1, wherein the scan voltage has a magnitude of: And a method larger than the sustain discharge voltage.