KR100573155B1 - Driving method of plasma display panel - Google Patents

Abstract

SUMMARY OF THE INVENTION An object of the present invention is to improve reduction of darkroom contrast generated by applying a reset signal to all cells in a plasma display panel having a two-electrode structure.

In order to achieve the above object, the present invention provides a plasma display having a front substrate and a rear substrate spaced apart from each other, scan electrode lines are formed between the substrates, and the address electrode lines are crossed with respect to the scan electrode lines. About the panel,

(a) an address step of sequentially applying a negative scan voltage for each scan electrode line and selectively applying a positive address voltage to the address electrode lines to select a cell to be turned on; And

(b) applying sustain pulses alternately having a positive sustain discharge voltage and a negative sustain discharge voltage to the scan electrodes in order to perform sustain discharge in a cell selected in the address step;

And a sustain discharge step of applying a positive erase voltage to initialize a discharge cell at the time of applying the last sustain pulse.

Description

Driving method of plasma display panel {Driving method of plasma display panel}

FIG. 1 is a diagram schematically illustrating scan electrode lines and address electrode lines of a plasma display panel having a two-electrode structure.

2 is a timing diagram showing a conventional driving signal for driving a plasma display panel having a two-electrode structure.

3 is a block diagram schematically illustrating a driving apparatus of a plasma display panel for implementing a method of driving a plasma display panel of the present invention.

4 is an exploded perspective view showing a plasma display panel having a two-electrode structure to which the method for driving a plasma display panel of the present invention is applied.

5 is a cross-sectional view taken along line II-II of FIG. 4.

6 is a timing diagram illustrating a driving signal for explaining a method of driving a plasma display panel of the present invention.

Explanation of symbols on the main parts of the drawings

Ce ...

Y1, Y2, ..., Yn ... multiple scan electrode lines,

A1, A2, ..., Am ... multiple address electrode lines,

Vr ... reset voltage,

Vscan ... scan voltage,

Va ... address voltage,

Vs ... Dielectric potential voltage,

Vx ... clearing voltage,

1 ... plasma display panel,

200 ...

202 Logic controller,

204 ... Y drive unit,

206 ... address drive.

The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel having a two-electrode structure.

FIG. 1 is a diagram schematically illustrating scan electrode lines and address electrode lines of a plasma display panel having a two-electrode structure.

Referring to the drawings, in the two-electrode structure of the plasma display panel, a plurality of address electrode lines A1, A2, ..., Am are arranged in the upper direction from the top of the panel to the lower direction, and the plurality of address electrode lines A plurality of scan electrode lines Y1, Y2, ..., Yn are arranged to intersect with (A1, A2, ..., Am). The discharge cell Ce is partitioned in an area where the plurality of address electrode lines A1, A2, ..., Am and the plurality of scan electrode lines Y1, Y2, ..., Yn cross each other. An image is displayed on the panel by the discharge in the discharge cell Ce.

Unlike the three-electrode structure, a plurality of intersecting the plurality of address electrode lines A1, A2, ..., Am, and arranged in parallel to the plurality of scan electrode lines Y1, Y2, ..., Yn The sustain electrode lines are not arranged.

2 is a timing diagram showing a conventional driving signal for driving a plasma display panel having a two-electrode structure.

A unit frame for realizing an image on the plasma display panel is divided into a plurality of subfields for time division gray scale display, and each subfield SB includes a reset period PR, an address period PA, and a sustain discharge period PS. Divided.

In the reset period PR, a reset pulse signal having a reset voltage Vr is applied to all of the plurality of scan electrode lines Y1, Y2,..., And Yn in order to initialize the wall charge state in all cells. . The ground voltage Vg is applied to the address electrode. The initialization discharge is performed by the potential difference between the scan electrode and the address electrode A. FIG.

In the address period PA, an address discharge is performed to select a cell to be turned on among all the cells. Scan signals having a negative scan voltage Vscan are sequentially applied to the scan electrodes along the vertical direction of the panel. A display data signal having a positive address voltage Va is applied to the address electrode A in order to select a cell to be turned on according to a negative scan voltage sequentially applied to the scan electrode. When the potential difference between the address voltage Va and the scan voltage Vscan is higher than the discharge start voltage Vf, the address discharge is performed, whereby wall charges are accumulated in the discharge cell selected as the cell to be turned on.

In the sustain discharge period PS, sustain discharge for luminance display is performed in a cell selected as a cell to be turned on in the address period PA. The luminance of the plasma display panel is determined according to the number of sustain discharges. A sustain pulse having a positive sustain discharge voltage Vs and a negative sustain discharge voltage -Vs is alternately applied to the scan electrode Y, and a ground voltage Vg is applied to the address electrode A. The sustain discharge is started by using the sustain discharge voltage Vs applied to the scan electrode and the wall voltage (not shown, Vw) due to wall charges accumulated inside the discharge cell in the address period PA.

Meanwhile, in a conventional driving signal for driving a plasma display panel having a two-electrode structure, a reset pulse having a reset voltage Vr is applied to all the cells in the reset period PR, thereby causing strong discharge in the cell. Is performed. Even in a cell that is not selected as a cell to be turned on in the address period PA, light is generated by the strong discharge, thereby affecting a discharge cell in the vicinity selected as the cell to be turned on. Therefore, a problem may occur in which darkroom contrast is deteriorated.

SUMMARY OF THE INVENTION The present invention provides a method of driving a plasma display panel for improving the reduction of darkroom contrast generated by applying a reset signal to all cells in a plasma display panel having a two-electrode structure in order to solve the above problems. It aims to do it.

In order to achieve the above object, the present invention is a plasma having a front substrate and a rear substrate spaced apart from each other, the scan electrode lines are formed between the substrates, the plasma formed so that the address electrode lines cross with respect to the scan electrode lines A driving method of a plasma display panel in which a unit frame is divided into a plurality of subfields for time division gray scale display, and reset, address, and sustain discharge steps are performed in each of the subfields.

(a) an address step of sequentially applying a negative scan voltage for each scan electrode line and selectively applying a positive address voltage to the address electrode lines to select a cell to be turned on; And

(b) applying sustain pulses alternately having a positive sustain discharge voltage and a negative sustain discharge voltage to the scan electrodes in order to perform sustain discharge in a cell selected in the address step;

And a sustain discharge step of applying a positive erase voltage to initialize a discharge cell at the time of applying the last sustain pulse.

According to another aspect of the present invention, the erase voltage may be greater than the difference of the sum of the wall voltage and the dielectric constant voltage of the discharge cell during the sustain discharge at the discharge start voltage at which the discharge of the sustain discharge step starts to be performed.

According to another aspect of the present invention, the erase voltage may be smaller than the difference between the sustain discharge voltage and the discharge start voltage in order to prevent discharge from occurring in a cell that should not be turned on.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a block diagram schematically illustrating a driving apparatus of a plasma display panel for implementing a method of driving a plasma display panel of the present invention.

The driving apparatus of the plasma display panel includes an image processing unit 200, a logic control unit 202, a Y driver 9204, an address driver 206, and a plasma display panel 1.

The image processor 200 receives an external image signal such as a PC signal, a DVD signal, a video signal, or a TV signal from the outside, converts an analog signal into a digital signal, and processes the digital signal into an internal image signal. The internal video signals are 8-bit red (R), green (G), and blue (B) image data, clock signals, and vertical and horizontal sync signals, respectively.

The logic controller 202 receives an internal image signal from the image processor 200 and performs an gamma correction, an automatic power control (APC) step, and the like, to respectively output an address driving control signal SA and a Y driving control signal SY. Output

The Y driving unit 204 receives the Y driving control signal SY from the logic control unit 202, and maintains the scan signal having the negative scan voltage sequentially in the up and down direction of the panel 1 in the address period. In the discharge period, a sustain pulse having an alternating positive sustain discharge voltage and a negative sustain discharge voltage is applied to the scan electrode lines of the plasma display panel.

The address driver 206 receives the address driving control signal SA from the logic controller 202 and applies a display data signal for applying an address voltage to a cell to be turned on among all cells in the address period of the plasma display panel 1. Output to the address electrode lines. In addition, when the last sustain pulse is applied to the scan electrode line in the sustain discharge period, an erase pulse having a positive erase voltage is applied to the address electrode lines.

The plasma display panel 1 is a plasma display panel of a two-electrode structure in accordance with the present invention. It will be described in detail below.

By using the above-mentioned driving apparatus of the plasma display panel, a driving method of the plasma display panel of the two-electrode structure of the present invention is performed.

4 is an exploded perspective view showing a plasma display panel having a two-electrode structure to which the method for driving a plasma display panel of the present invention is applied.

5 is a cross-sectional view taken along line II-II of FIG. 4.

Referring to FIGS. 4 and 5, the plasma display panel 1 includes an upper panel 10 and a lower panel 20.

The upper panel 10 includes a front substrate 11, a plurality of scan electrodes 16 extending in one direction below the front substrate 11, and an upper dielectric layer 14 filling the scan electrodes 16. And an upper protective layer 15 covering the upper dielectric layer 14. The scan electrodes 16 are formed of a metal material having excellent conductivity. Examples of the metal material include aluminum, copper, and silver.

The lower panel 20 includes a rear substrate 21, a plurality of address electrodes 22 formed on an upper surface of the rear substrate 21, a lower dielectric layer 23 filling the address electrodes 22, and the lower dielectric layer. A partition 24 formed on the 23, a phosphor layer 25 applied on the lower dielectric layer 23 over the partition 24, and a lower protective layer 26 formed on the phosphor layer 25. Equipped. The address electrodes 22 are formed in a stripe pattern extending in one direction, and extend in a direction substantially intersecting with an extending direction of the scan electrodes 16.

As shown in FIG. 4, the partition wall 24 may be formed in a matrix shape extending in two orthogonal directions. The partition wall 24 may have optical and electrical crosstalk between adjacent discharge cells 30. to prevent cross-talk. Here, one discharge cell is a space defined by the partition wall, and means one subpixel among red subpixels, green subpixels, and blue subpixels constituting one pixel.

Referring to FIG. 5, in the two-electrode plasma display panel 1 having the above-described configuration, a scan voltage is applied to the scan electrode 16, and an address voltage is applied to the address electrode 22 so that the scan electrode ( By the potential difference between 16 and the address electrode 22, an address discharge occurs, and as a result of this address discharge, a cell 30 in which a sustain discharge occurs is selected. Subsequently, a sustain pulse having an alternating sustain discharge voltage and a negative sustain discharge voltage is applied to the scan electrode 16 of the selected cell 30 so that the scan electrode 16 and the address electrode 22 are applied. The sustain discharge is started by the potential difference of and the wall voltage caused by the wall charges in the discharge cells formed in the address period. Ultraviolet rays are emitted while the energy level of the discharged gas excited by this sustain discharge is lowered. The ultraviolet rays excite the phosphor layer 25 coated in the discharge cell 30. As the energy level of the excited phosphor layer 25 decreases, visible light is emitted, and the emitted visible light forms an image.

6 is a timing diagram illustrating a driving signal for explaining a method of driving a plasma display panel of the present invention.

In the two-electrode plasma display panel 1 of the present invention, by applying a reset pulse having a reset voltage to the scan electrode in a reset period, strong discharge occurs, and adjacent discharge is performed in a cell in which discharge is not performed by the strong discharge. The following driving signal is applied to the two-electrode plasma display panel in order to prevent the darkroom contrast from appearing by affecting the cells.

First, in the address period PA, a scan signal having a scan voltage having a negative voltage is sequentially applied to the plurality of scan electrode lines Y1, Y2, ..., Yn in the vertical direction of the panel. In order to select a cell to be turned on among all the cells in the address period, a display data signal having a positive address voltage Va is applied to the plurality of address electrode lines A1, A2, ..., Am. In the cell selected as the cell to be turned on, the address discharge is performed by the potential difference between the positive address voltage Va of the address electrode and the negative scan voltage Vscan of the scan electrode. Wall charges are accumulated in the cell by the address discharge, and the accumulated wall charges affect the sustain discharge performed in the sustain discharge period PS after the address period PA.

In the sustain discharge period PS, a sustain pulse having positive sustain discharge voltage Vs and negative sustain discharge voltage (-Vs) in all scan electrode lines Y1, Y2, ..., Yn. Apply. Meanwhile, the ground voltage Vg is applied to all of the address electrode lines A1, A2, ..., Am. In the discharge cells in which the address discharge is performed in the address period PA by the sustain pulses applied to the scan electrodes, wall voltages (not shown, Vw) due to accumulated wall charges and the sustain discharge voltages Vs applied are used. The discharge start voltage (not shown, Vf) is easily reached, whereby the sustain discharge is performed. On the other hand, in a cell in which no address discharge has been performed in the address period PA, even when the sustain pulse having the positive sustain discharge voltage Vs and the negative sustain discharge voltage (-Vs) becomes a sustain pulse, the wall charges accumulated in the cell remain. Therefore, the discharge start voltage Vf cannot be reached, and thus sustain discharge is not performed.

On the other hand, the number of sustain discharges in the sustain discharge period PS is proportional to the luminance of the plasma display panel. Therefore, the number of sustain discharges must be increased to realize high brightness.

In connection with the present invention, in the sustain discharge period PS, at the time when the last sustain pulse having the sustain discharge voltage Vs is applied to the scan electrode, a positive erase voltage Vx is applied to the address electrode.

Vf-Vw-Vs <Vx

The erase voltage Vx is applied such that the initialization discharge is performed by the potential difference between the sustain discharge voltage Vs of the scan electrode and the erase voltage Vx of the address electrode and the wall voltage Vw due to the wall charge inside the discharge cell. Should be. Therefore, the erase voltage Vx to be applied must be greater than the difference of the sum of the wall voltage Vw and the sustain discharge voltage Vs of the discharge cell during the sustain discharge at the discharge start voltage Vf. That is, the erase voltage Vw must be applied to establish the relationship of Equation 1 above.

Vf-Vs> Vx

In addition, the applied erase voltage Vx should be smaller than the difference between the sustain discharge voltage Vs and the discharge start voltage Vf in order to prevent discharge from occurring in a cell that should not be turned on. That is, the erase voltage Vx must be applied to establish the relationship of Equation 2 above.

Vf-Vw-Vs <Vx <Vf-Vs

Eventually, the erase voltage Vx applied must be greater than the difference of the sum of the wall voltage Vw and the sustain discharge voltage Vs of the discharge cell during the sustain discharge in the discharge start voltage Vf according to the relationship of Equation 3 above. , The discharge start voltage Vf must be smaller than the difference of the sustain discharge voltage Vs.

When the erase voltage Vx is applied, in the cell selected as the cell to be turned on, within the discharge cell due to the potential difference between the sustain discharge voltage Vs and the erase voltage Vx of the last sustain pulse in the sustain discharge period PS. Initialization discharge is performed, which makes it possible to evenly distribute the wall charge state inside the discharge cell. In addition, in the cell which is not selected as the cell to be turned on, the discharge start voltage Vf is not reached, so that the initialization discharge is not performed. As a result, initialization discharge is selectively performed. Therefore, the initialization discharge is performed for all conventional cells, whereby darkroom contrast can be prevented from worsening by the strong discharge reset.

According to the present invention as described above, the following effects can be obtained.

First, in the sustain discharge period, at the time when the last sustain pulse is applied to the scan electrode, by applying a positive erase voltage to the address electrode, the initialization discharge is performed only in the cell where the sustain discharge is performed, so that the darkroom contrast can be improved. do.

Second, since the reset period in the subfield does not have to be set separately, the period of each subfield constituting the frame can be shortened, so that more subfields can be configured per frame than in the prior art.

third. In addition, since the address period or sustain discharge period in the subfield can be further secured, stable discharge of the plasma display panel can be performed.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (3)

For a plasma display panel having a front substrate and a rear substrate spaced apart from each other, scan electrode lines are formed between the substrates, and address electrode lines intersect with the scan electrode lines, a time-division gray scale display of a unit frame In the method of driving a plasma display panel divided into a plurality of subfields for which the address and sustain discharge steps are performed in each of the subfields, (a) an address step of sequentially applying a negative scan voltage for each scan electrode line and selectively applying a positive address voltage to the address electrode lines to select a cell to be turned on; And (b) applying a sustain pulse alternately having a positive sustain discharge voltage and a negative sustain discharge voltage to the scan electrode lines to perform sustain discharge in the cell selected in the address step; And a sustain discharge step of applying a positive erase voltage to the address electrode lines to initialize a discharge cell when the last sustain pulse having the negative sustain discharge voltage is applied. Way. The method of claim 1, wherein the erase voltage, And a discharge start voltage at which the discharge of the sustain discharge step starts to be performed, which is greater than a difference between the sum of the wall voltage and the sustain discharge voltage of the discharge cell during the sustain discharge. The method of claim 1, wherein the erase voltage, A method of driving a plasma display panel, characterized in that it is smaller than the difference of the sustain discharge voltage in the discharge start voltage so that discharge does not occur in a cell that should not be turned on.

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