KR20060000910A - Method for fabrication of deep contact hole in semiconductor device - Google Patents

Abstract

The present invention is to provide a method for forming a deep contact hole of a semiconductor device that can prevent the attack on the upper insulating film when forming a deep contact hole, and prevent the contact sick opening, for this purpose, Forming an insulating film; Forming a sacrificial pattern connected to the conductive layer through the first insulating layer; Forming a second insulating layer on the sacrificial pattern; Selectively etching the second insulating layer to expose the sacrificial pattern; And forming the contact hole exposing the conductive layer by removing the exposed sacrificial pattern by an isotropic etching process.

In addition, the present invention includes the steps of forming a first and a second conductive layer in the cell region and the peripheral region on the substrate divided into a cell region and a peripheral region, respectively; Forming a first insulating film on an entire surface of the substrate including the first and second conductive layers; Forming a plug contacting the first conductive layer through the first insulating layer in the cell region and forming a sacrificial pattern connected to the second conductive layer through the first insulating layer in the peripheral region; Forming a second insulating layer on the plug and the sacrificial pattern; Selectively etching the second insulating layer to expose the sacrificial pattern in the peripheral region; And forming the contact hole exposing the conductive layer by removing the exposed sacrificial pattern by an isotropic etching process.

Deep contact holes, bit lines, selective isotropic etching, metallization, polysilicon, sacrificial patterns, storage node contact plugs.

Description

Method for forming deep contact hole in semiconductor device {METHOD FOR FABRICATION OF DEEP CONTACT HOLE IN SEMICONDUCTOR DEVICE}             

1A to 1D are cross-sectional views illustrating a bit line metallization process as an example of a deep contact hole formation process according to the prior art.

2A to 2F are cross-sectional views illustrating a contact hole process for forming a bit line metal wiring in a peripheral region of a semiconductor memory device according to an embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a process for forming a bit line metal wiring according to another embodiment of the present invention.

4 is a view for explaining a problem occurring when forming a conventional deep contact hole.

Explanation of symbols on main parts of drawing

200: substrate 201: bit line

202: first insulating film 203: sacrificial pattern

204: second insulating film 208: selective isotropic etching process

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a deep contact hole in a semiconductor device.

In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices become highly integrated, various elements must be formed at a high density on a certain cell area. As a result, unit devices such as transistors and capacitors are gradually decreasing in size. In particular, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), as the design rule is reduced, the size of unit devices formed inside the cell is gradually decreasing. In fact, in recent years, the minimum line width of the semiconductor DRAM device is formed to 0.1㎛ or less, even up to 80nm is required. Therefore, many difficulties have arisen in the manufacturing process of the semiconductor devices forming the cell.

When applying the photolithography process using ArF (argon fluoride) exposure having a wavelength of 193 nm in a semiconductor device having a line width of 80 nm or less, the requirements for the conventional etching process (exact pattern formation and vertical etching profile, etc.) There is a further need for preventing the deformation of photoresist generated during etching. Accordingly, when manufacturing a semiconductor device of 80 nm or less, the development of process conditions for simultaneously satisfying the existing requirements and the new requirements of pattern deformation prevention has become a major problem in terms of etching.

Meanwhile, as the degree of integration of the device increases and the design rule decreases, the distance between adjacent conductive patterns (eg, gate electrodes) decreases. In contrast, as the thickness of the conductive pattern increases, the height of the conductive pattern and the conductive pattern increase. The aspect ratio, which represents the ratio of the distance between them, is gradually increased.

A representative example is a deep contact hole forming process for forming a metal line of a bit line in a peripheral region after forming a bit line and forming a capacitor of a cell region in manufacturing a semiconductor memory device.

1A to 1D are cross-sectional views illustrating a bit line metal wiring forming process according to the prior art, and looks at a deep contact hole forming process for forming a conventional bit line metal wiring with reference to this.

First, as shown in FIG. 1A, a conductive pattern is formed on a conductive layer, and then an insulating film 102 having a plurality of insulating films stacked on the entire structure is formed.

Meanwhile, since the bit line metal wiring forming process is taken as an example, the manufacturing process according to this will be described in more detail.

That is, the bit line 101 is formed on the semiconductor substrate 100 on which various elements for forming a semiconductor device, for example, a transistor including a field insulating layer and a well and a gate electrode, are formed.

The bit line 101 usually has a conductive film, and has an insulating hard mask on the top and an insulating spacer on the sidewall of the bit line 101, but the description is omitted here for the sake of simplicity.

A first insulating layer 102 in which a plurality of insulating layers of an oxide layer and a nitride layer is stacked is formed on the entire surface where the bit line 101 is formed. When the first insulating layer 102 is formed, a cell capacitor is formed in the cell region.

Subsequently, a photoresist pattern 103 defining an open region on the bit line 101 is formed on the first insulating layer 102 to form a metal wiring.

At this time, since the first insulating film 102 includes a capacitor oxide film in the cell region, the deposition thickness thereof is considerably high, which is 20000 GPa or more. Thus, it can be seen that the aspect ratio h / w for the edible target is considerably large in the etching process for the formation of the subsequent bit line rapid interconnection.

Subsequently, as illustrated in FIG. 1B, a plasma etching 104 process is performed using the photoresist pattern 103 as an etching mask.

At this time, CxFy (x, y is 1 to 10) / O ₂ gas is used in an MERIE (Magnetic Enhanced Reactive Ion Etcher) type etching apparatus suitable for high aspect ratio.

At this time, when a large amount of Ar gas is applied to the CxFy / O ₂ gas in the plasma state in the same direction as the dotted line, as shown in FIG. 1C, an open part 105 exposing the bit line 101 is formed.

Subsequently, a cleaning process is performed to remove residue remaining after the open portion 105 is formed.

Subsequently, after removing the photoresist pattern 103, as shown in FIG. 1D, a conductive film is deposited to fill the open part 104 and the bit line 101 through the open part 104 through a planarization process such as CMP. Next, the connecting portion 105 is electrically connected to the first, and then the metal wiring 106 is formed on the connecting portion 105.

On the other hand, in the above-described bit line metal wiring forming process, the etching target in the etching process for forming the deep contact hole is large, which causes a problem to be described later.

4 is a view for explaining a problem occurring when forming a conventional deep contact hole.

Referring to FIG. 4, in the process of FIG. 1C, when the aspect ratio is 15/1 or more in the conventional MERIE type plasma source, contact opening is difficult, and the photoresist is exposed due to exposure for more than a selectivity ratio to the plasma of the photoresist, which is an etching mask. Due to the lack of a margin of the resist pattern, an attack of the insulating layer 102 as shown by reference numeral 108 occurs at an upper end portion of the insulating layer 102 forming the etch profile in which the open portion 105 is formed. On the other hand, as the design rules of semiconductor devices are gradually reduced, a deeper contact hole formation technique with a higher aspect ratio is required, and efforts are being made to use a hard mask as a mask pattern.

There is a risk of bridging with adjacent dozan patterns due to the attack on the upper end of the insulating film 102 caused by the above-mentioned difficulties. In addition, when the etching process is not excessively performed to prevent such bridges, reference numeral ' Contact not open may occur, such as 107 '.

The present invention has been proposed to solve the above problems of the prior art, and provides a method for forming a deep contact hole in a semiconductor device that can prevent the attack on the top of the insulating film and prevent contact sick opening when forming a deep contact hole For that purpose.

The present invention to achieve the above object, forming a first insulating film on the conductive layer; Forming a sacrificial pattern connected to the conductive layer through the first insulating layer; Forming a second insulating layer on the sacrificial pattern; Selectively etching the second insulating layer to expose the sacrificial pattern; And forming the contact hole exposing the conductive layer by removing the exposed sacrificial pattern by an isotropic etching process.

In addition, to achieve the above object, the present invention comprises the steps of forming a first and a second conductive layer in the cell region and the peripheral region on the substrate divided into a cell region and a peripheral region, respectively; Forming a first insulating film on an entire surface of the substrate including the first and second conductive layers; Forming a plug contacting the first conductive layer through the first insulating layer in the cell region and forming a sacrificial pattern connected to the second conductive layer through the first insulating layer in the peripheral region; Forming a second insulating layer on the plug and the sacrificial pattern; Selectively etching the second insulating layer to expose the sacrificial pattern in the peripheral region; And forming the contact hole exposing the conductive layer by removing the exposed sacrificial pattern by an isotropic etching process.                     

The present invention forms a sacrificial pattern when forming a deep contact hole, thereby preventing the attack on the upper deep contact hole due to lack of selection ratio of the mask pattern, and selectively removing only the sacrificial pattern to secure the critical dimension of the bottom of the contact.

In addition, by forming simultaneously with the plug forming step in the cell region instead of performing a separate step of the sacrificial pattern forming step, it can be formed by a relatively simple step.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can more easily implement the present invention.

2A through 2F are cross-sectional views illustrating a contact hole process for forming a bit line metal wiring in a peripheral region of a semiconductor memory device according to an embodiment of the present invention, with reference to the bit according to an embodiment of the present invention. The line metallization forming process will be described in detail.

In the embodiment of the present invention described below, a process of forming a space pattern, for example, a contact hole pattern, of a semiconductor device is described as an example. The contact hole pattern to which the present invention is applied is a metal wiring contact and a bit line. Alternatively, the present invention may be applied to a process for forming a contact pad and contact with an impurity bonding layer in a substrate such as a source / drain junction for a storage node contact of a capacitor.

First, as shown in FIG. 2A, the bit line 201 is formed on the conductive layer, and then an insulating film 202 having a plurality of insulating films stacked on the entire structure is formed.

Meanwhile, in the present embodiment, the bit line metal wiring forming process is taken as an example.

That is, the bit line 201 is formed on the semiconductor substrate 200 on which various elements for forming a semiconductor device, for example, a transistor including a field insulating layer and a well and a gate electrode, are formed.

The bit line 201 usually has a conductive film, and has an insulating hard mask on the top and an insulating spacer on the sidewall of the bit line 201, but is omitted here for the sake of simplicity.

A first insulating layer 202 including a plurality of insulating layers of an oxide film series and a nitride film series is formed on the entire surface where the bit line 201 is formed. When the first insulating layer 202 is formed, a cell capacitor is formed in the cell region.

Here, the oxide-based insulating film may be, for example, an HDP (High Density Plasma) oxide film, a Tetra Ethyl Ortho Silicate (TEOS) film, a Boro Phospho Silicate Glass (BPSG) film, a Boro Silicate Glass (BSG) film, or a Phospho Silicate Glass (PSG) film. , A spin on glass (SOG) film, an advanced planarization layer (APL) film, and the like, and the nitride film-based insulating film is a hard mask used to form a hard mask or storage node contact to prevent an attack such as a bit line 201. Or a nitride film-based insulating film including an etch stop film, for example, a silicon oxynitride film or a silicon nitride film.

Subsequently, the first insulating layer 202 is selectively etched to open the upper part of the bit line 201 corresponding to the contact forming portion for forming the subsequent bit line metal wiring, and then the main portion of the first insulating layer 202 is formed on the entire surface. A material film that can be selectively removed without loss of the oxide film is deposited by having an etching selectivity with the oxide film.

Subsequently, a planarization process using an entire surface etch or a CMP is performed on the target to which the first insulating layer 202 is exposed to planarize the first insulating layer 202 and the upper portion thereof, and the sacrificial pattern 203 connected to the bit line 201 is formed. To form.

Here, the doped or undoped polysilicon film may be exemplified as the material film used as the sacrificial pattern 203 because the etch selectivity with the oxide film can be selectively removed without loss of the oxide film.

Subsequently, a second insulating layer 204 in which an oxide-based insulating film and a nitride-based insulating film are stacked is formed on the entire surface where the sacrificial pattern 203 is formed.

At this time, the cell capacitor forming process will be completed in the cell region during the formation of the second insulating film 204.

A mask pattern 205 is formed on the second insulating layer 204 to define a region to be opened for subsequent bit line metallization, and the pattern formation region defined by the mask pattern 205 is a sacrificial pattern 203 and The metal wiring contact overlaps with the upper portion of the bit line 201 to be made.

Meanwhile, since the sacrificial pattern 203 is included between the bit line 201 and the second insulating layer 204 in the present invention, the etching target is reduced by the thickness of the sacrificial pattern 203 in the etching process for forming the subsequent metal wiring. Can be.

Therefore, the aspect ratio h / w during etching is reduced in comparison with the related art.                     

Here, the mask pattern 205 may be a conventional photoresist pattern, may include a photoresist pattern and a sacrificial hard mask, or may refer to only a sacrificial hard mask.

That is, this indicates that a sacrificial hard mask such as tungsten, polysilicon, or nitride may be used to secure the etching resistance of the photoresist and prevent the pattern deformation due to the limitation of the resolution in the photolithography process.

On the other hand, when forming a photoresist pattern, an anti-reflection film can be used between the lower part and the lower part. The anti-reflection film is used between the photoresist pattern and the lower structure for the purpose of improving the adhesion between the lower structure and the photoresist to prevent unwanted reflections due to high reflectivity of the lower part during exposure for pattern formation and to prevent unwanted reflections. .

In this case, the antireflection film mainly uses an organic-based material having similar etching characteristics to that of the photoresist, and may be omitted depending on a process.

As the sacrificial hard mask, in addition to the above-described material film, an Al film, a WSix (x is 1 to 2) film, a WN film, a Ti film, a TiN film, a TiSix (x is 1 to 2) film, a TiAlN film, a TiSiN film, a Pt film , Ir film, IrO ₂ film, Ru film, RuO ₂ film, Ag film, Au film, Co film, Au film, TaN film, CrN film, CoN film, MoN film, MoSix (x is 1 to 2) film, Al At least one thin film selected from the group consisting of a ₂ O ₃ film, an AlN film, a PtSix (x is 1 to 2) film, a CrSix (x is 1 to 2) film, and an amorphous carbon film can be used.

Next, as shown in FIG. 2C, an open portion 207 exposing the upper portion of the sacrificial pattern 203 is formed by performing a plasma etching 206 process using the mask pattern 205 as an etching mask.

In this case, using a MERIE type etching apparatus which is relatively suitable for etching an insulating film having a high aspect ratio, a mixed gas of CxFy (x, y is 1 to 10) / CaHbFc (a, b, c is 1 to 10) / O ₂ is used. A large amount of Ar gas is applied in a plasma state in the same direction as the dotted line.

In forming the open portion 207, for example, CxFy: CaHbFc: O ₂ : Ar is preferably used in a ratio of 15: 20: 15: 200, and power of 1800 W or more is used at a pressure of 20 mTorr or less.

Subsequently, after removing the mask pattern 205, as shown in FIG. 2D, a plasma is applied along the open portion 207 to selectively etch and remove only the sacrificial pattern 203 under the open portion 207. An etching process 208 is performed.

As described above, the sacrificial pattern 203 uses an oxide film-based material film constituting the first and second insulating films 202 and 204 and a material film that can be selectively removed with an etching selectivity, for example, a polysilicon film. Such selective isotropic etching processes are possible.

Therefore, when the polysilicon film is used as the sacrificial pattern 203, Cl ₂ / HBr / O ₂ is used as the source gas, and the ratio is preferably maintained at about 10: 10: 2.

Inductive Coupled Plasma (ICP) type, Transformer coupled plasma (TCP) type, Decoupled Plasma Source (DPS) type, Micriwave Down Stream (MDS) type equipped with Faraday shield for the plasma reaction with the above isotropic etching characteristics The etching process is performed at a medium temperature of 260 ° C to 300 ° C in a plasma source etching apparatus such as a type, an ECR (Electron Cyclotron Resonance) type, or a helical type. At this time, the pressure of the chamber is maintained at 20 mTorr or less and power of 500 W to 2000 W is used.

Therefore, as shown in FIG. 2E, a deep contact hole having a high aspect ratio while sufficiently securing an open area at the bottom and preventing an attack on the upper portion of the second insulating layer 204 through selective removal of the sacrificial pattern 203. 209 may be formed.

Subsequently, a cleaning process is performed to remove residue remaining after the deep contact hole 209 is formed.

Subsequently, as illustrated in FIG. 2F, a conductive film is deposited to fill the deep contact hole 209 and is electrically connected to the bit line 201 through the deep contact hole 209 through a planarization process such as CMP. After forming the 210, the metal wiring 211 is formed on the connection portion 210.

Herein, the connection part 210 includes polysilicon, Ti, TiN, W, TiSi ₂ , and the like, and the metal wire 211 includes Al or Cu.

Meanwhile, the above-described sacrificial pattern may be formed using a conventionally used process, for example, a storage node contact plug forming process, rather than an additional process.

3A to 3D are cross-sectional views illustrating a process of forming a bit line metal wiring according to another embodiment of the present invention.                     

First, as shown in FIG. 3A, a bit line B / L is formed on a semiconductor substrate 300 on which various elements for forming a semiconductor device, for example, a field insulating layer, a transistor including a well and a gate electrode, are formed.

The bit line B / L has a laminated structure of an insulating hard mask 302 / conductive film 301 and has an insulating spacer 303 on its sidewall.

As the conductive film 301, a structure in which polysilicon and tungsten silicide are laminated or a single structure of tungsten may be used, and the insulating hard mask 302 and the spacer 303 may be formed of a nitride film-based insulation such as a silicon nitride film or a silicon oxynitride film. Membrane can be used.

Here, region A represents a cell region of the semiconductor memory device, and region B represents a peripheral region.

Subsequently, a first insulating film 304 in which a plurality of insulating films of an oxide film series and a nitride film series are stacked is formed on the entire surface where the bit lines B / L are formed.

Here, the oxide-based insulating film includes, for example, an HDP oxide film, a TEOS film, a BPSG film, a BSG film, a PSG film, an SOG film, an APL film, and the like, and the nitride film-based insulating film may contain an attack such as a bit line (B / L). A nitride film-based insulating film, such as a silicon oxynitride film or a silicon nitride film, including a hard mask or an etch stopper film used to form a hard mask or a storage node contact for preventing the film.

Subsequently, the first insulating layer 304 is selectively etched to open the sal contact plug in contact with the impurity diffusion region such as the source / drain of the substrate 300 in the cell region A. FIG. At this time, in the peripheral region B, the conductive film 301 of the bit line B / L corresponding to the contact forming portion for forming the subsequent bit line metal wiring is opened together.

Subsequently, a polysilicon film, which is used as a contact plug for a storage node in the cell region A and has an etch selectivity with an oxide film that forms the main portion of the first insulating film 304, is selectively deposited without loss of the oxide film. .

Subsequently, a planarization process using full etching or CMP is performed on the target to which the first insulating layer 304 is exposed.

Accordingly, the storage node contact plug 305a is formed in the cell region A, and in the peripheral region B, the first insulating layer 304 and the upper portion thereof are planarized, and the conductive layer 301 of the bit line B / L is formed. And a sacrificial pattern 305b connected to each other.

Subsequently, as shown in FIG. 3B, the cell capacitor CAP including the lower electrode 306, the dielectric layer 307, and the upper electrode 308 is formed on the storage node contact plug 305a in the cell region A. FIG. Form.

Subsequently, a second insulating layer 309 is formed on the entire surface of the cell capacitor CAP and the sacrificial pattern 305b in which an insulating layer based on an oxide film and an insulating layer based on a nitride film are stacked.

A mask pattern 310 is formed on the second insulating layer 309 to define a region to be opened for subsequent bit line metallization, and the pattern formation region defined by the mask pattern 310 is a sacrificial pattern 305b and The metal wiring contact is overlapped with the conductive film 301 of the bit line B / L to be made.

Meanwhile, since the sacrificial pattern 305b is included between the bit line B / L and the second insulating layer 309 in the present invention, the etching target is formed by the thickness of the sacrificial pattern 305b in the etching process for forming the subsequent metal wiring. Can be reduced.

Accordingly, the aspect ratio during etching is reduced from 'h1 / w' to 'h2 / w' as compared with the conventional art.

Here, the mask pattern 310 may be a conventional photoresist pattern, may include a photoresist pattern and a sacrificial hard mask, or may refer to only a sacrificial hard mask.

That is, this indicates that a sacrificial hard mask such as tungsten, polysilicon, or nitride may be used to secure the etching resistance of the photoresist and prevent the pattern deformation due to the limitation of the resolution in the photolithography process.

On the other hand, when forming a photoresist pattern, an anti-reflection film can be used between the lower part and the lower part. The anti-reflection film is used between the photoresist pattern and the lower structure for the purpose of improving the adhesion between the lower structure and the photoresist to prevent unwanted reflections due to high reflectivity of the lower part during exposure for pattern formation and to prevent unwanted reflections. .

In this case, the antireflection film mainly uses an organic-based material having similar etching characteristics to that of the photoresist, and may be omitted depending on a process.

As the sacrificial hard mask, in addition to the above-described material film, an Al film, a WSix (x is 1 to 2) film, a WN film, a Ti film, a TiN film, a TiSix (x is 1 to 2) film, a TiAlN film, a TiSiN film, a Pt film , Ir film, IrO ₂ film, Ru film, RuO ₂ film, Ag film, Au film, Co film, Au film, TaN film, CrN film, CoN film, MoN film, MoSix (x is 1 to 2) film, Al At least one thin film selected from the group consisting of a ₂ O ₃ film, an AlN film, a PtSix (x is 1 to 2) film, a CrSix (x is 1 to 2) film, and an amorphous carbon film can be used.

Next, as shown in FIG. 3C, a plasma etching process using the mask pattern 310 as an etching mask is performed to expose the upper portion of the sacrificial pattern 305b.

In this case, using a MERIE type etching apparatus which is relatively suitable for etching an insulating film having a high aspect ratio, a mixed gas of CxFy (x, y is 1 to 10) / CaHbFc (a, b, c is 1 to 10) / O ₂ is used. A large amount of Ar gas is applied in a plasma state.

When exposing the top of the sacrificial pattern 305b, it is preferable to use CxFy: CaHbFc: O ₂ : Ar in a ratio of 15: 20: 15: 200 and to use a power of 1800 W or more at a pressure of 20 mTorr or less.

Subsequently, after the mask pattern 310 is removed, an isotropic etching process is performed to selectively etch and remove only the lower sacrificial pattern 305b by applying a plasma along an etching profile exposing the upper portion of the sacrificial pattern 305b.

As described above, since the sacrificial pattern 305b uses an oxide-based material film constituting the first and second insulating films 304 and 309 and a polysilicon film that can be selectively removed with an etching selectivity, such selective isotropy Etching process is possible.

Therefore, when the polysilicon film is used as the sacrificial pattern 305b, Cl ₂ / HBr / O ₂ is used as the source gas, and the ratio is preferably maintained at about 10: 10: 2.

For the plasma reaction with the isotropic etching characteristic described above, the etching process is performed at an intermediate temperature of 260 ° C to 300 ° C in a plasma source etching apparatus such as an ICP type, an MDS type, an ECR type, or a helical type equipped with a Faraday shield. At this time, the pressure of the chamber is maintained at 20 mTorr or less and power of 500 W to 2000 W is used.

Therefore, through the selective removal of the sacrificial pattern 305b, a deep contact hole 311 having a high aspect ratio can be formed while sufficiently securing an open area at the bottom and preventing an attack on the upper portion of the second insulating layer 309.

Subsequently, a cleaning process is performed to remove residue remaining after the deep contact hole 311 is formed.

Subsequently, as illustrated in FIG. 3D, the conductive film is deposited to fill the deep contact hole 311 and the bit line (B / L) conductive film 301 through the deep contact hole 311 through a planarization process such as CMP. The connection part 312 electrically connected to the connection part 312 is formed, and the metal wiring 313 is formed on the connection part 312.

Herein, the connection part 312 includes polysilicon, Ti, TiN, W, TiSi ₂ , and the like, and the metal wire 313 includes Al, Cu, or the like.

In another embodiment of the present invention described above, a process of simultaneously forming a sacrificial pattern and a storage node contact plug is used as an example. In addition, the bit line contact, the cell contact, or the via contact and the sacrificial pattern of the cell region may be simultaneously formed. In the peripheral area, it may be applicable to forming metal wirings for gate electrodes, sources / drains, etc. as well as bit lines.

According to the present invention, a sacrificial pattern is formed during deep contact hole formation to prevent an attack on the upper part of the deep contact hole due to lack of selectivity of the mask pattern, while selectively removing only the sacrificial pattern so that the critical dimension of the bottom surface of the contact ( CD) can be secured to prevent contact sick opening.

In addition, the present invention has been found that the present invention can be formed by a relatively simple process by simultaneously forming the plug formation process in the cell region instead of performing a separate process of the sacrificial pattern forming process.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can sufficiently secure a critical dimension in forming a deep contact hole by a relatively simple process, and can suppress the occurrence of bridges between metal wirings due to an upper attack, thereby improving the yield and productivity of the semiconductor device. There is an effect that can be improved.

Claims (16)

Forming a first insulating film on the conductive layer; Forming a sacrificial pattern connected to the conductive layer through the first insulating layer; Forming a second insulating layer on the sacrificial pattern; Selectively etching the second insulating layer to expose the sacrificial pattern; And Forming a contact hole exposing the conductive layer by removing the exposed sacrificial pattern by an isotropic etching process Deep contact hole forming method of a semiconductor device comprising a. The method of claim 1, And the second insulating layer is an oxide-based insulating layer, and the sacrificial pattern comprises a polysilicon layer. The method of claim 2, Forming a contact hole, using a Cl ₂ / HBr / O ₂ gas. The method of claim 3, wherein And forming the Cl ₂ / HBr / O ₂ gas at a ratio of 10: 10: 2. The method of claim 2 or 3, In the forming of the contact hole, A method for forming a deep contact hole in a semiconductor device, characterized in that it is carried out in any one type of equipment of TCP, ICP, DPS, MERIE, MDS, ECR or helical. The method of claim 5. In the forming of the contact hole, A method for forming a deep contact hole in a semiconductor device, using a power of 500W to 2000W at a temperature of 260 ℃ to 300 ℃. The method of claim 1, The conductive layer may include any one of a gate electrode, a bit line, an impurity diffusion region, and a metal wiring. Forming first and second conductive layers in the cell region and the peripheral region on the substrate partitioned into a cell region and a peripheral region, respectively; Forming a first insulating film on an entire surface of the substrate including the first and second conductive layers; Forming a plug contacting the first conductive layer through the first insulating layer in the cell region and forming a sacrificial pattern connected to the second conductive layer through the first insulating layer in the peripheral region; Forming a second insulating layer on the plug and the sacrificial pattern; Selectively etching the second insulating layer to expose the sacrificial pattern in the peripheral region; And Forming a contact hole exposing the conductive layer by removing the exposed sacrificial pattern by an isotropic etching process Deep contact hole forming method of a semiconductor device comprising a. The method of claim 8, And the second insulating layer is an oxide-based insulating layer, and the sacrificial pattern and the plug comprise a polysilicon layer. The method of claim 9, Forming a contact hole, using a Cl ₂ / HBr / O ₂ gas. The method of claim 10, And forming the Cl ₂ / HBr / O ₂ gas at a ratio of 10: 10: 2. The method of claim 10 or 11, In the forming of the contact hole, A method for forming a deep contact hole in a semiconductor device, characterized in that it is carried out in any one type of equipment of TCP, ICP, DPS, MERIE, MDS, ECR or helical. The method of claim 12. In the forming of the contact hole, A method for forming a deep contact hole in a semiconductor device, using a power of 500W to 2000W at a temperature of 260 ℃ to 300 ℃. The method of claim 8, The second conductive layer may include any one of a gate electrode, a bit line, an impurity diffusion region, and a metal wiring. The method of claim 8, The second conductive layer may include any one of an impurity diffusion region, a bit line, and a gate electrode, and the plug may include a storage node contact plug. The method of claim 15, After forming the plug and the sacrificial pattern, And forming a cell capacitor in the cell region.

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