KR20050123406A - Method for driving plasma display panel wherein subsidiary reset pulse is applied - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel for smoothly performing addressing when an auxiliary reset pulse is applied. According to the present invention, the main reset pulse is applied to the Y electrode lines in the reset step of the first subfield, and the auxiliary reset pulse is applied to the Y electrode lines in the reset step of the second subfield. Smooth addressing is performed by applying the length of the negative pulse of the pulse longer than the length of the negative pulse of the main reset pulse.

Description

Method for driving plasma display panel where subsidiary reset pulse is applied}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel using a main reset pulse and an auxiliary reset pulse in order to prevent the contrast of the plasma display panel from being lowered.

1 is a waveform diagram of signals applied to electrode lines of a conventional plasma display panel. The unit frame applied to the plasma display panel is divided into a plurality of sub-fields for time division gray scale display.

Referring to FIG. 1, the unit subfield SF is divided into a reset step R, an addressing step A, and a display-sustain step S. Referring to FIG. In FIG. 1, reference numerals Sa1 to San denote address driving signals applied to the address electrode lines, reference numerals Sx1 to Sxn denote X driving signals applied to the X electrode lines, and reference numerals Sy1 to Syn denote Y electrode lines. Indicates Y drive signals applied.

In the reset step R, the address drive signals Sa1 to San are held at the ground potential Vg. The X driving signals Sx1 to Sxn rise from the initial t0 to the potential Vs and then lower to the ground potential Vg at the time t1 and rise back to the potential Vs at the time t2. The Y driving signals Sy1 to Syn are initially maintained at the ground potential Vg at the time t0, and then rapidly rise to the potential Vs at the time point t1, and then continuously rise to the potential Vset, and the time point t2. After abruptly lowering to the potential Vs at, it is continuously lowered from the time point t3 to the ground potential Vg and maintained at the ground potential Vg at the time interval t4 to t5.

In the addressing step A, the address driving signals Sa1 to San are applied as pulse signals Sa1, Sa2, San with positive potential Va to the address electrode lines, and the Y driving signals Sy1 to San. Syn is sequentially applied to the Y electrode lines as scan signals having a potential Vscl lower than the potential Vnf. Thus, smooth addressing can be performed. The address driving signals Sa1 to San are applied as the positive potential Va to the address electrode lines corresponding to the display cell selection, and as the ground potential Vg otherwise.

In the sustain discharge step S, the Y drive signals Sy1 to Syn and the X drive signals Sx1 to Sxn are applied alternately as pulse signals having a potential Vs, and accordingly the corresponding addressing step A Discharge occurs for display-holding in the display cells in which wall charges are accumulated.

However, conventionally, the contrast of the plasma display panel is reduced by applying main reset pulses to the reset step R of all subfields.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of driving a plasma display panel for improving contrast and performing smooth addressing.

The present invention to achieve the above technical problem

A method of driving a plasma display panel in which X electrode lines and Y electrode lines are alternately arranged to form XY electrode line pairs, and display cells are set in regions where the XY electrode line pairs and the address electrode lines cross each other. The unit frame applied to the plasma display panel is composed of a plurality of subfields, each of which consists of a reset step, an addressing step, and a sustain discharge step, and (a) the Y in the reset step of the first subfield. Applying a main reset pulse to the electrode lines; And (b) applying an auxiliary reset pulse to the Y electrode lines in the reset step of the second subfield, and applying a length of the negative pulse of the auxiliary reset pulse to be longer than the length of the negative pulse of the main reset pulse. It provides a method of driving a plasma display panel comprising.

According to the present invention, smooth addressing is performed in the reset step in which the auxiliary reset pulse is applied.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a perspective view illustrating a three-electrode surface discharge plasma display panel according to the present invention, and FIG. 3 is a cross-sectional view illustrating one of a plurality of display cells included in the plasma display panel shown in FIG. 2. 2 and 3, address electrode lines AR1 to ARm, dielectric layers 211 and 215, and Y are formed between the front and rear glass substrates 210 and 213 of the conventional surface discharge plasma display panel 201. Electrode lines Y1 to Yn, X electrode lines X1 to Xn, phosphor 216, partition 217, and magnesium monoxide (MgO) layer 212 as a protective layer are provided.

The address electrode lines AR1 to ARm are formed in a predetermined pattern on the front side of the rear glass substrate 213. The lower dielectric layer 215 is entirely coated on the front side of the address electrode lines AR1 to ARm. The barrier ribs 217 are formed in a direction parallel to the address electrode lines AR1 to ARm in front of the lower dielectric layer 215. These partitions 217 define a discharge area of each display cell and prevent optical cross talk between each display cell. The fluorescent layer 216 is applied between the partitions 217.

The X electrode lines X1 to Xn and the Y electrode lines Y1 to Yn are formed in a predetermined pattern on the back of the front glass substrate 210 so as to intersect the address electrode lines AR1 to ARm. Each intersection sets a corresponding display cell. The X electrode lines X1 to Xn and the Y electrode lines Y1 to Yn are transparent electrode lines Xna and Yna made of a transparent conductive material such as indium tin oxide (ITO), and metal electrode lines for increasing conductivity. (Xnb, Ynb) is formed by combining. The front dielectric layer 211 is formed by coating the entire surface on the back of the X electrode lines X1 to Xn and the Y electrode lines Y1 to Yn. A protective layer 212 for protecting the panel 201 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 211. The plasma forming gas is sealed in the discharge space 214.

In the driving method basically applied to such a discharge display panel, the resetting, addressing, and display-sustain steps are sequentially performed in the unit subfield. In the reset phase, the charge states of all display cells are uniform. In the addressing step, a predetermined wall voltage is generated in the selected display cells. In the sustain discharge step, a predetermined alternating voltage is applied to all the XY electrode line pairs so that the display cells to which the wall voltage is applied in the addressing step cause display-maintain discharge. In this sustain discharge step, plasma is formed in the discharge space 214, i.e., the gas layer, of the selected display cells causing the display-hold discharge, and the fluorescent layer 216 is excited by the ultraviolet radiation to generate light.

4 is a block diagram of a driving device for driving the plasma display panel shown in FIG. 2. Referring to FIG. 4, a typical driving apparatus of the plasma display panel 201 includes an image processor 451, a logic controller 441, an address driver 411, an X driver 421, and a Y driver 431. .

The image processing unit 451 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The logic controller 441 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 451. The address driver 411 generates the display data signal by processing the address signal S _A among the driving control signals S _A , S _Y , and S _X from the logic controller 441, and generates the display data signal. Is applied to the address electrode lines. The X driver 421 processes the X driving control signal S _X from the driving control signals S _A , S _Y , and S _X from the logic controller 441, and applies the X driving control signal S _X to the X electrode lines. The Y driver 431 processes the Y driving control signal S _Y from the driving control signals S _A , S _Y , and S _X from the logic controller 441, and applies the Y driving control signal S _Y to the Y electrode lines.

FIG. 5 is a timing diagram illustrating a driving method for Y electrode lines of the plasma display panel illustrated in FIG. 2. Referring to FIG. 5, each of all unit frames is divided into _eight subfields SF ₁ to SF 8 to realize time division gray scale display. In addition, the subfields SF ₁ to SF ₈ are divided into a reset time R ₁ to R ₈ , an addressing time A _{1 to} A ₈ , and a display-holding time S _{1 to} S ₈ .

The discharge conditions of all the display cells become uniform in the reset steps R ₁ to R ₈ while being suitable for the addressing to be performed in the next step. At the addressing times A _{1 to} A ₈ , the display data signal is applied to the address electrode lines AR1 to ARm in FIG. 1, and the scan pulses corresponding to the Y electrode lines Y1 to Yn are sequentially applied. . Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are generated by the addressing discharge in the corresponding discharge cell, and wall charges are not generated in the discharge cell that is not.

In the display-holding steps S1 to S8, a display-holding pulse is alternately applied to all the Y electrode lines Y1 to Yn and all the X electrode lines X1 to Xn, so that the corresponding addressing step ( In A), display discharges occur in discharge cells in which wall charges are accumulated. Therefore, the luminance of the plasma display panel is proportional to the length of the display-hold time S1 to Sn occupied in the unit frame. The length of the display-hold time (S1 to Sn) in the unit frame is 255T (T is the unit time). Therefore, it can be displayed in 256 gray scales, even if it is not displayed once in a unit frame.

Here, the first sub-field (SF ₁₎ displays - a holding time (S1), the time (1T) corresponding to ^20, the second display of the sub-fields (SF ₂₎ -, the holding time (S2) 2 ¹ The time 2T corresponding to the display-holding time S2 of the third subfield SF ₃ corresponds to the time 4T corresponding to 2 ² , and the display-holding time of the fourth subfield SF ₄ . In operation S4, the time 8T corresponding to 2 ³ is represented, and in the display-hold time S5 of the fifth subfield SF ₅ , the time 16T corresponding to 2 ⁴ is represented by the sixth subfield SF _6. In the display-holding time (S6) of (), the time 32T corresponding to 2 ⁵ , the display-holding time (S7) of the seventh subfield (SF ₇ ), the time (64T) corresponding to 2 ⁶ , and In the display-hold time S8 of the eighth subfield SF ₈ , a time 128T corresponding to 2 ⁷ is set.

Accordingly, if a subfield to be displayed among the eight subfields is appropriately selected, 256 gray levels may be displayed including all zero (zero) grays not displayed in any subfields.

6 is a waveform diagram illustrating driving signals for describing a method of driving a plasma display panel according to an exemplary embodiment of the present invention. Specifically, FIG. 6 illustrates driving signals applied to electrode lines Y1 to Yn, X1 to Xn, and AR1 to ABm of FIG. 5 while the unit frame of FIG. 5 is applied to the plasma display panel 201 of FIG. 2. The waveforms of (Sy1-Syn, Sx1-Sxn, Sa1-San) are shown. In Fig. 6, the signals Sa1 to San are address driving signals applied to the address electrode lines AR1 to ABm in Fig. 2, and the signals Sy1 to Syn are Y electrode lines (Y1 to Yn in Fig. 2). Are Y driving signals applied to the signal lines, and the signals Sx1 to Sxn are driving signals applied to the X electrode lines (X1 to Xn in FIG. 2).

7 to 11 are wall charge distributions in the reset steps shown in FIG. A driving method of the plasma display panel 201 of FIG. 2 will be described with reference to FIGS. 6 to 11.

First, an operation of the first subfield SF1 to which the main reset pulse P1 is applied will be described.

During the initial time t0 to t1 of the reset step R1, the X driving signals Sx1 to Sxn, the Y driving signals Sy1 to Syn and the address driving signals Sa1 to San are all ground potential Vg. Is maintained. After the sustain discharge of the subfield before the first subfield SF1 ends, as shown in FIG. 7, positive (+) wall charges are accumulated in the X electrode lines (X1 to Xn of FIG. 2), and the Y electrode. Negative wall charges are accumulated in the lines (Y1 to Yn in FIG. 2), and a lot of positive wall charges are stored in the address electrode lines (AR1 to ABm in FIG. 2).

During the wall charge accumulation time t1 to t2 of the reset step R1, a positive pulse of the main reset pulse P1 is applied to the Y electrode lines Y1 to Yn in FIG. 2. That is, the Y driving signals Sy1 to Syn increase rapidly from the ground potential Vg to the potential Vs and then continuously rise to the potential Vset. The X driving signals Sx1 to Sxn and the address driving signals Sa1 to San are kept at the ground potential Vg. Accordingly, between the Y electrode lines (Y1 to Yn in FIG. 2) and the X electrode lines (X1 to Xn in FIG. 2), and the Y electrode lines (Y1 to Yn in FIG. 2) and the address electrode lines (FIG. A strong discharge occurs between AR1 to ARm of 2. Therefore, as shown in FIG. 8, many negative wall charges are accumulated in the Y electrode lines (Y1 to Yn in FIG. 2), and the X electrode lines (X1 to Xn in FIG. 2) and the address electrode lines (FIG. Positive wall charges are accumulated in AR1 to ABm) of 2.

During the wall charge distribution time t2 to t6 of the reset step R1, the potential Vs is applied to the X electrode lines X11 to Xn in FIG. 2, and the address electrode lines AR1 to ABm in FIG. The ground potential Vg is continuously applied to the gate electrode, and a potential Vnf lower than the ground potential Vg is applied to the Y electrode lines Y1 to Yn of FIG. 2. That is, a negative pulse Vnf is applied to the Y electrode lines (Y1 to Yn in FIG. 2). Then, discharge occurs between the X electrode lines (X1 to Xn in FIG. 2) and the Y electrode lines (Y1 to Yn in FIG. 2). Therefore, as shown in FIG. 9, the negative wall charges accumulated in the Y electrode lines (Y1 to Yn in FIG. 2) are greatly reduced, and the X electrode lines (X1 to Xn in FIG. 2) are inverted in polarity. Weak negative wall charges are accumulated, and positive wall charges accumulated in the address electrode lines (AR1 to ABm in FIG. 2) are slightly reduced.

In this way, the contrast of the plasma display panel 201 of FIG. 2 can be reduced by applying a high positive potential Vset during the wall charge accumulation times t1 to t2 of the reset step R1. In order to prevent this, in the reset step R2 of the second subfield SF2, the auxiliary reset pulse P2 is applied to the Y electrode lines Y1 to Yn of FIG. 2.

In the addressing step A1, pulses having a positive potential Va are applied to the address electrode lines AR1 to ARm in FIG. 2, and a negative potential Vnf to the Y electrode lines Y1 to Yn in FIG. As pulses with s are applied sequentially, an addressing operation is performed. Address driving signals Sa1 to San applied to the address electrode lines AR1 to ARm of FIG. 2 are applied as pulses having a positive potential Va to selected display cells, and a ground potential to unselected display cells. Vg).

During the subsequent sustain discharge step S1, the Y drive signals Sy1 to Syn and the X drive signals Sx1 to Sxn are applied alternately with sustain discharge pulses of the potential Vs, so that the corresponding addressing step A ) Causes sustain discharge in the accumulated display cells.

Next, an operation of the second subfield SF2 to which the auxiliary reset pulse P2 is applied will be described.

During the initial time t10 to t11 of the reset step R2, a positive pulse of the auxiliary reset pulse P2 is applied to the Y electrode lines Y1 to Yn in FIG. 2, and the X electrode lines X1 in FIG. The ground potential Vg is applied to ˜Xn and the address electrode lines AR1 to ABm in FIG. 2. At this time, the potential Vs of the positive pulse is much lower than the potential Vset of the positive pulse of the main reset pulse P1. Then, as shown in FIG. 10, negative wall charges are further increased in the Y electrode lines (Y1 to Yn in FIG. 2), and the X electrode lines (X1 to Xn in FIG. 2) and the address electrode lines ( In AR1 to ABm of FIG. 2, the positive wall charges are further increased. That is, the wall charges accumulated in the Y electrode lines (Y1 to Yn in FIG. 2) do not increase much compared to FIG. 7.

During the wall charge distribution time t11 to t13 of the reset step R2, a negative pulse of the auxiliary reset pulse P2 is applied to the Y electrode lines Y1 to Yn in FIG. 2, and the X electrode lines (FIG. 2). The positive potential Vs is applied to X1 to Xn. At this time, the length tb of the negative pulse of the auxiliary reset pulse P2 is longer than the length ta of the negative pulse of the main reset pulse P1, and the potential Vnh of the negative pulse is the main reset pulse P1. Is applied higher than the potential Vnf of the negative pulse. Thus, as shown in Fig. 11, the negative wall charges accumulated in the Y electrode lines (Y1 to Yn in Fig. 2) decreases little. The polarity of the X electrode lines (X1 to Xn in FIG. 2) is reversed to accumulate negative wall charges, and the positive wall charges accumulated in the address electrode lines (AR1 to ABm in FIG. 2) decrease.

As such, the wall charge distribution in the state where the reset step R2 of the second subfield SF2 is finished and the wall charge distribution in the state where the reset step R1 of the first subfield SF1 is finished are similar to each other. Therefore, when the auxiliary reset pulse is applied, smooth addressing can be performed while preventing the contrast of the plasma display panel 201 of FIG. 2 from being lowered.

When the length tb of the negative pulse of the auxiliary reset pulse P2 is longer than the length ta of the negative pulse of the main reset pulse P1, the number of display cells that are normally discharged is shown in Table 1 below.

K One 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 J 0 One 7 9 9 9 9 9 9 9 8 3 2

In Table 1, K represents the length (tb) of the negative pulse of the auxiliary reset pulse O2 when the length ta of the negative pulse of the main reset pulse P1 is 1, and J represents the number of display cells discharged. Indicates.

That is, when the length tb of the negative pulse of the auxiliary reset pulse O2 is equal to the length ta of the negative pulse of the main reset pulse P1, the number of display cells discharged is zero, and the auxiliary reset pulse O2 When the length tb of the negative pulse is 1.1 times the length ta of the negative pulse of the main reset pulse P1, the number of display cells discharged is one, and the length of the negative pulse of the auxiliary reset pulse O2 ( When tb is 1.32 times the length ta of the negative pulse of the main reset pulse P1, the number of discharged display cells is seven, and the length (tb) of the negative pulse of the auxiliary reset pulse O2 is the main reset pulse. The number of display cells discharged when 1.5 to 2.7 times the length ta of the negative pulse of (P1) is nine, and the length (tb) of the negative pulse of the auxiliary reset pulse O2 is equal to that of the main reset pulse P1. The number of display cells discharged when 2.9 times the length (ta) of the negative pulse is eight When the length tb of the negative pulse of the auxiliary reset pulse O2 is 3.1 times the length ta of the negative pulse of the main reset pulse P1, the number of display cells discharged is three, and the auxiliary reset pulse ( The number of display cells discharged is two when the length tb of the negative pulse of O2) is 3.3 times the length ta of the negative pulse of the main reset pulse P1.

In this way, when the length tb of the negative pulse of the auxiliary reset pulse O2 is 1.5 to 2.7 times the length ta of the negative pulse of the main reset pulse P1, the number of display cells discharged is the highest (9). to be. Therefore, it is most preferable that the length tb of the negative pulse of the auxiliary reset pulse O2 is 1.5 to 2.7 times the length ta of the negative pulse of the main reset pulse P1.

In addition, the slope where the main reset pulse P1 of the first subfield SF1 falls from the positive pulse to the negative pulse is the slope where the auxiliary reset pulse P2 of the second subfield SF2 falls from the positive pulse to the negative pulse. It is desirable to make it equal to the slope.

In addition, it is effective to apply the auxiliary reset pulse P2 only when sustain discharge is performed in the first subfield SF1.

In the addressing step A2, pulses having a positive potential Va are applied to the address electrode lines AR1 to ARm in FIG. 2, and a negative potential Vnf to the Y electrode lines Y1 to Yn in FIG. 2. As pulses with s are sequentially applied, the addressing operation A2 is performed. At this time, the X driving signals Sx1 to Sxn are kept at the potential Vs.

During the sustain discharge step S2, sustain discharge pulses of the potential Vs are alternately applied to the Y electrode lines Y1 to Yn in FIG. 2 and the X electrode lines X1 to Xn in FIG. In the addressing step A2, sustain discharge occurs in the display cells in which the wall charges are accumulated.

The best embodiments have been disclosed in the drawings and the specification, and the terminology used herein is for the purpose of describing the invention only and is not intended to be limiting of the scope of the invention as defined in the appended claims or claims. Therefore, those skilled in the art will be capable of various modifications and other equivalent embodiments from this, and therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

As described above, according to the present invention, the main reset pulse P1 is applied during the reset step R1 of the first subfield SF1, and the auxiliary reset is performed during the reset step R2 of the second subfield SF2. The application of the pulse P2 prevents the contrast of the plasma display panel 201 in FIG. 2 from being lowered and at the same time reduces the power consumption.

Here, by applying the length tb of the negative pulse of the auxiliary reset pulse P2 to be longer than the length ta of the negative pulse of the main reset pulse P1, the following addressing operation A2 is smoothly performed.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a waveform diagram of signals applied to electrode lines of a conventional plasma display panel.

2 is an internal perspective view of a three-electrode surface discharge plasma display panel for implementing the present invention.

3 is a cross-sectional view illustrating one of a plurality of display cells included in the plasma display panel illustrated in FIG. 2.

4 is a block diagram of driving devices for driving the plasma display panel shown in FIG. 2.

FIG. 5 is a timing diagram illustrating a driving method for Y electrode lines of the plasma display panel illustrated in FIG. 2.

6 is a waveform diagram illustrating driving signals for describing a method of driving a plasma display panel according to an exemplary embodiment of the present invention.

7 to 9 are wall charge distribution diagrams in the reset step of the first subfield illustrated in FIG. 6.

10 and 11 are wall charge distribution diagrams in the reset step of the second subfield illustrated in FIG. 6.

<Explanation of symbols for the main parts of the drawings>

201; A plasma display panel 210; Front glass substrate

211/215; Dielectric layer, 212; Protective layer

213; Rear glass substrate, 214; Discharge space

216; Fluorescent layer, 217; septum

X1 to Xn; X electrode lines, Y1 to Yn; Y electrode lines

AR1-ARm; Address electrode lines, X _na / Y _na ; Transparent electrode lines

X _nb / Y _nb ; Metal electrode lines, 411; Address driver

421; X driver 431; Y drive

441; Logic controller 451; Image processor

SF _{1 to} SF ₈ ; Subfields, Sy1-Syn; Y drive signals

Sa1-San; Address driving signals Sx1 to Sxn; X drive signals

Claims (5)

A method of driving a plasma display panel in which X electrode lines and Y electrode lines are alternately arranged to form XY electrode line pairs, and display cells are set in regions where the XY electrode line pairs and the address electrode lines cross each other. The unit frame applied to the plasma display panel includes a plurality of subfields, and the subfields each include a reset step, an addressing step, and a sustain discharge step. (a) applying a main reset pulse to the Y electrode lines in a reset step of a first subfield; And (b) applying an auxiliary reset pulse to the Y electrode lines in a reset step of a second subfield, and applying a length of a negative pulse of the auxiliary reset pulse to be longer than a length of a negative pulse of the main reset pulse. And a plasma display panel driving method. The method of claim 1, wherein the resetting of the first and second subfields comprises a positive pulse and a negative pulse, respectively. And a slope in which the auxiliary reset pulses of the two sub-fields fall from the positive pulses to the negative pulses. The method of claim 1, wherein the potential of the negative pulse of the auxiliary reset pulse is higher than the potential of the negative pulse of the main reset pulse. The method of claim 1, wherein the auxiliary reset pulse is applied only when sustain discharge is generated in the first subfield. The method of claim 1, wherein the length of the negative pulse of the auxiliary reset pulse is 1.2 times or more than the negative pulse of the main reset pulse.