KR20050122072A - Method of manufacturing capacitor for semiconductor device - Google Patents
Method of manufacturing capacitor for semiconductor device Download PDFInfo
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- KR20050122072A KR20050122072A KR1020040047220A KR20040047220A KR20050122072A KR 20050122072 A KR20050122072 A KR 20050122072A KR 1020040047220 A KR1020040047220 A KR 1020040047220A KR 20040047220 A KR20040047220 A KR 20040047220A KR 20050122072 A KR20050122072 A KR 20050122072A
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- Prior art keywords
- capacitor
- film
- semiconductor device
- insulating film
- metal
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- 239000003990 capacitor Substances 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 239000010410 layer Substances 0.000 claims abstract description 27
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 238000006243 chemical reaction Methods 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 19
- 239000010936 titanium Substances 0.000 claims description 15
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 10
- 229910052719 titanium Inorganic materials 0.000 claims description 10
- 239000007791 liquid phase Substances 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- -1 titanium-silicon-aluminum Chemical compound 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000012071 phase Substances 0.000 claims description 2
- 239000007788 liquid Substances 0.000 claims 1
- 238000007669 thermal treatment Methods 0.000 claims 1
- 238000003860 storage Methods 0.000 abstract description 5
- 229910021341 titanium silicide Inorganic materials 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 7
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- 229910008484 TiSi Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910020776 SixNy Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 MIM 구조의 캐패시터에서 하부전극과 스토리지노드콘택(SNC) 플러그 사이의 오믹콘택을 가능케하여 소자 패일을 방지하는데 그 목적이 있다.An object of the present invention is to prevent ohmic contact between a lower electrode and a storage node contact (SNC) plug in a capacitor of a MIM structure.
본 발명은 상부에 층간절연막에 의해 분리된 콘택 플러그가 형성된 반도체 기판을 준비하는 단계; 기판 전면 상에 캐패시터 절연막을 형성하는 단계; 캐패시터 절연막을 식각하여 콘택 플러그를 노출시키는 캐패시터용 홀을 형성하는 단계; 홀을 포함하는 캐패시터 절연막 상에 실리사이드용 금속막을 증착하는 단계; 금속막과 콘택 플러그를 반응시켜 콘택 플러그 표면에 금속실리사드층을 형성하는 단계; 반응 시 미반응된 금속막을 제거하는 단계; 금속실리사이드층 표면을 세정하는 단계; 및 홀 표면에 하부전극을 형성하는 단계를 포함하는 반도체 소자의 캐패시터 제조방법에 의해 달성될 수 있다. The present invention includes the steps of preparing a semiconductor substrate having a contact plug formed thereon separated by an interlayer insulating film; Forming a capacitor insulating film on the front surface of the substrate; Etching the capacitor insulating film to form a hole for the capacitor exposing the contact plug; Depositing a silicide metal film on a capacitor insulating film including a hole; Reacting the metal film with the contact plug to form a metal silicide layer on the contact plug surface; Removing the unreacted metal film during the reaction; Cleaning the surface of the metal silicide layer; And forming a lower electrode on the hole surface.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 캐패시터의 상부 및 하부전극으로 금속막을 사용하는 반도체 소자의 캐패시터 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device using a metal film as the upper and lower electrodes of the capacitor.
일반적으로, 메모리셀에 사용되는 캐패시터는 스토리지(storage)용 하부 전극, 유전막, 및 플레이트(plate)용 상부전극으로 이루어진다.In general, a capacitor used in a memory cell includes a lower electrode for storage, a dielectric layer, and an upper electrode for a plate.
또한, 제한된 면적 내에서 큰 커패시턴스를 얻기 위해서는 얇은 유전체막 두께를 확보하거나, 3차원적인 캐패시터의 구조를 통해서 유효 면적을 증가시키거나, 탄탈륨산화물(Ta2O5)과 같은 고유전율의 유전막을 적용하는 등의 몇 가지 조건이 만족되어야 하는데, 이 중 Ta2O5와 같은 고유전율의 유전막을 적용하는 경우에는 캐패시터의 상부 및 하부 전극을 TiN, W, WN, Ru, RuO2, Ir, IrO2 등의 금속을 사용한 금속-절연체-금속(Metal-Insulator-Metal; MIM) 구조로 캐패시터를 형성한다.In addition, in order to obtain a large capacitance within a limited area, a thin dielectric film thickness is secured, an effective area is increased through a three-dimensional capacitor structure, or a high dielectric constant dielectric film such as tantalum oxide (Ta 2 O 5 ) is applied. Some conditions must be satisfied. Among them, when applying a dielectric constant of high dielectric constant such as Ta 2 O 5 , the upper and lower electrodes of the capacitor may be TiN, W, WN, Ru, RuO 2 , Ir, IrO 2. The capacitor is formed of a metal-insulator-metal (MIM) structure using a metal such as the like.
한편, 이러한 MIM 구조의 캐패시터에서는 하부전극과 하부전극 콘택층인 스토리지노드콘택(storage node contact; SNC) 플러그와의 오믹(ohmic) 콘택을 위한 실리사이드 공정의 안정화가 가장 중요하다.Meanwhile, in the capacitor of the MIM structure, stabilization of the silicide process for ohmic contact between a storage node contact (SNC) plug, which is a lower electrode and a lower electrode contact layer, is most important.
그런데, SNC 플러그 형성 후 실리사이드층 형성을 위해 티타늄(Ti)과 같은 실리사이드용 금속막을 증착하고, 급속열처리(Rapid Thermal Annealing; RTA)에 의한 실리사이드 공정을 수행하게 되면, 티타늄실리사이드(TiSi2)층이 형성되는 과정에서 확산된 실리콘(Si)이 티타늄실리사이드층 표면에 극미세 산화층으로 존재하게 되고, 이러한 산화층이 후속 미반응 티타늄 제거를 위한 세정공정에서 질화막(SixNy)으로 변질되어, 도 1과 같이 티타늄실리사이드(TiSi2)층과 하부전극의 계면에서 백색의 띠 형상으로 존재하게 된다.However, after the SNC plug is formed, a silicide metal film such as titanium (Ti) is deposited to form a silicide layer, and when the silicide process is performed by rapid thermal annealing (RTA), the titanium silicide (TiSi 2 ) layer is formed. The silicon (Si) diffused during the formation process is present as a very fine oxide layer on the surface of the titanium silicide layer, and the oxide layer is changed into a nitride film (SixNy) in a subsequent cleaning process for removing unreacted titanium. White stripe exists at the interface between the silicide (TiSi 2 ) layer and the lower electrode.
이에 따라, SNC 플러그와 하부전극 사이의 콘택 저항이 높아지게 되어, 결국 소자 패일을 초래하게 된다. As a result, the contact resistance between the SNC plug and the lower electrode becomes high, resulting in device failure.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 상부 및 하부전극으로서 금속막을 사용하는 MIM 구조의 캐패시터에서 하부전극과 스토리지노드콘택(SNC) 플러그 사이의 오믹콘택을 가능케하여 소자 패일을 방지하는데 그 목적이 있다. The present invention has been proposed to solve the above problems of the prior art, and in the MIM structure of the capacitor using a metal film as the upper and lower electrodes enable the ohmic contact between the lower electrode and the storage node contact (SNC) plug device The purpose is to prevent failure.
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 상부에 층간절연막에 의해 분리된 콘택 플러그가 형성된 반도체 기판을 준비하는 단계; 기판 전면 상에 캐패시터 절연막을 형성하는 단계; 캐패시터 절연막을 식각하여 콘택 플러그를 노출시키는 캐패시터용 홀을 형성하는 단계; 홀을 포함하는 캐패시터 절연막 상에 실리사이드용 금속막을 증착하는 단계; 금속막과 콘택 플러그를 반응시켜 콘택 플러그 표면에 금속실리사드층을 형성하는 단계; 반응 시 미반응된 금속막을 제거하는 단계; 금속실리사이드층 표면을 세정하는 단계; 및 홀 표면에 하부전극을 형성하는 단계를 포함하는 반도체 소자의 캐패시터 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention comprises the steps of preparing a semiconductor substrate having a contact plug separated by an interlayer insulating film thereon; Forming a capacitor insulating film on the front surface of the substrate; Etching the capacitor insulating film to form a hole for the capacitor exposing the contact plug; Depositing a silicide metal film on a capacitor insulating film including a hole; Reacting the metal film with the contact plug to form a metal silicide layer on the contact plug surface; Removing the unreacted metal film during the reaction; Cleaning the surface of the metal silicide layer; And forming a lower electrode on the hole surface.
여기서, 세정은 HxPOy를 이용하여 수행하는데, 이때 HxPOy는 액상을 함유하는 상태 또는 액상과 기상을 함유하는 상태를 가질 수 있는데, HxPOy가 액상의 상태를 가질 경우 온도를 120 내지 500℃ 정도로 조절하는 것이 바람직하다. 또한, HxPOy에서 x는 1 내지 4, y는 1 내지 5 정도로 각각 조절하는 것이 바람직하며, HxPOy가 약 20% 이하의 H2O를 함유할 수도 있다.Here, the cleaning is performed using H x PO y , where H x PO y may have a state containing a liquid phase or a state containing a liquid phase and a gaseous phase, when H x PO y has a liquid phase temperature It is preferable to adjust to about 120-500 degreeC. In addition, in H x PO y , x is preferably 1 to 4 and y is preferably adjusted to about 1 to 5, and H x PO y may contain about 20% or less of H 2 O.
또한, 금속막은 티타늄(Ti)막, 코발트(Co)막, 티타늄-알루미늄(Ti-Al)막, 티타늄-실리콘-알루미늄(Ti-Si-Al)막 중 선택되는 어느 하나이다.The metal film is any one selected from a titanium (Ti) film, a cobalt (Co) film, a titanium-aluminum (Ti-Al) film, and a titanium-silicon-aluminum (Ti-Si-Al) film.
또한, 금속실리사이드층은 N2, NH3, Ar, Ne 등을 사용하여 500 내지 1000℃의 온도범위에서 램프업 속도를 10 내지 300℃/초 정도로 유지하여 급속열처리로 수행한다.In addition, the metal silicide layer is performed by rapid heat treatment using N 2 , NH 3 , Ar, Ne and the like while maintaining a ramp-up rate of about 10 to 300 ° C./sec in a temperature range of 500 to 1000 ° C.
또한, 금속막의 제거는 NH4OH+H2O2를 이용한 습식식각으로 수행하는데, 이때 NH4OH+H2O2의 온도는 약 100℃ 이하로 조절한다.In addition, the metal film is removed for carrying out a wet etching using a NH 4 OH + H 2 O 2, the temperature of NH 4 OH + H 2 O 2 is adjusted to not more than about 100 ℃.
또한, 하부전극은 TiN, W, WN, Ru, RuO2, Ir, IrO2 등의 금속막으로 이루어진다.The lower electrode is made of a metal film such as TiN, W, WN, Ru, RuO 2 , Ir, IrO 2, or the like.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 2a 내지 도 2e를 참조하여 본 발명의 실시예에 따른 반도체 소자의 캐패시터 제조방법을 설명한다.A method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2E.
도 2a를 참조하면, 필드산화막(11), 게이트(12a)/하드마스크(12a)의 게이트 구조(12) 및 게이트 스페이서(13)가 형성되고, 제 1 층간절연막(14)에 의해 게이트(12a)와 절연되면서 제 1 층간절연막(14)에 구비된 제 1 콘택홀에 매립되어 제 1 층간절연막(14) 상에 비트라인(15)이 형성된 반도체 기판(10)을 준비한다. 그 다음, 비트라인(15)을 덮도록 제 1 층간절연막(14) 상에 제 2 층간절연막(16)을 형성하고, 기판(10)의 일부가 노출되도록 제 2 층간절연막(16)과 제 1 층간절연막(14)을 식각하여 제 2 콘택홀을 형성한다. 그 다음, 제 2 콘택홀을 매립하도록 폴리실리콘막을 증착하고, 화학기계연마(Chemcial Mechanical Polishing; CMP) 또는 에치백 공정에 의해 폴리실리콘막을 분리시켜 기판(10)과 콘택하는 SNC 플러그(17)를 형성한다.Referring to FIG. 2A, the field oxide film 11, the gate structure 12 of the gate 12a / hard mask 12a, and the gate spacer 13 are formed, and the gate 12a is formed by the first interlayer insulating film 14. ) And a semiconductor substrate 10 having a bit line 15 formed on the first interlayer insulating layer 14 by filling in the first contact hole provided in the first interlayer insulating layer 14. Next, a second interlayer insulating film 16 is formed on the first interlayer insulating film 14 to cover the bit line 15, and the second interlayer insulating film 16 and the first interlayer insulating film 16 are exposed to expose a portion of the substrate 10. The interlayer insulating layer 14 is etched to form a second contact hole. Next, a polysilicon film is deposited to fill the second contact hole, and the polysilicon film is separated by chemical mechanical polishing (CMP) or etch back process to contact the substrate 10 with the SNC plug 17. Form.
도 2b를 참조하면, 기판 전면 상에 캐패시터 절연막(18)으로서 질화막(18a)과 산화막(18b)을 순차적으로 증착한다. 여기서, 질화막(18a)은 후속 산화막(18b)제거시 식각정지막으로 작용한다. 그 다음, SNC 플러그(17) 및 그 주변의 제 2 층간절연막(16)이 일부 노출되도록 캐패시터 절연막(18)을 식각하여 캐패시터용 홀(19)을 형성한다. 그 후, 홀(19)을 포함하는 캐패시터 절연막(18) 상에 실리사이드용 금속으로서 티타늄(Ti)막(20)을 증착한다. 바람직하게, 티타늄막(20)은 물리기상증착(Physical Vapor Deposition; PVD), 화학기상증착(Chemical Vapor Deposition; CVD) 또는 원자층증착(Atomic Layer Deposition; ALD)에 의해 1 내지 200Å의 두께로 증착한다. 또한, 티타늄막(20)은 코발트(Co)막, 티타늄-알루미늄(Ti-Al)막, 티타늄-실리콘-알루미늄(Ti-Si-Al)막 등으로 대체될 수 있다.Referring to FIG. 2B, the nitride film 18a and the oxide film 18b are sequentially deposited as the capacitor insulating film 18 on the entire substrate. Here, the nitride film 18a acts as an etch stop film when the subsequent oxide film 18b is removed. Next, the capacitor insulating film 18 is etched to partially expose the SNC plug 17 and the surrounding second interlayer insulating film 16 to form the capacitor hole 19. After that, a titanium (Ti) film 20 is deposited on the capacitor insulating film 18 including the holes 19 as a silicide metal. Preferably, the titanium film 20 is deposited to a thickness of 1 to 200 kPa by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD). do. In addition, the titanium film 20 may be replaced with a cobalt (Co) film, a titanium-aluminum (Ti-Al) film, a titanium-silicon-aluminum (Ti-Si-Al) film, or the like.
도 2c를 참조하면, 이후 형성될 하부전극과 SNC 플러그(17)와의 오믹콘택을 위해 RTA로 실리사이드 공정을 수행하여, SNC 플러그(17)의 Si와 티타늄막(20)의 Ti를 서로 반응시켜 SNC 플러그(17) 표면에 티타늄실리사이드(TiSi2)층(21)을 형성한다. 여기서, RTA는 N2, NH3, Ar, Ne 등을 사용하여 500 내지 1000℃의 온도범위에서 램프업 속도(lamp up rate)를 10 내지 300℃/초 정도로 유지하여 수행한다. 그 후, NH4OH+H2O2를 이용한 습식식각을 수행하여 미반응된 티타늄을 완전히 제거한다. 바람직하게, NH4OH+H2O2의 온도는 100℃ 이하로 조절한다. 이때, 도 2c에 도시된 바와 같이, 티타늄실리사이드층(21)이 형성되는 과정에서 확산된 실리콘(Si)에 의해 발생된 극미세 산화층이 질화막(SixNy; 100)으로 변질되어 티타늄실리사이드층(21) 표면에 존재하게 된다.Referring to FIG. 2C, a silicide process is performed by RTA for ohmic contact between the lower electrode to be formed and the SNC plug 17, and the Si of the SNC plug 17 and Ti of the titanium film 20 react with each other. The titanium silicide (TiSi 2 ) layer 21 is formed on the surface of the plug 17. Here, RTA is performed using N 2 , NH 3 , Ar, Ne, and the like while maintaining a ramp up rate at a temperature range of 500 to 1000 ° C. at about 10 to 300 ° C./sec. Thereafter, wet etching using NH 4 OH + H 2 O 2 is performed to completely remove unreacted titanium. Preferably, the temperature of NH 4 OH + H 2 O 2 is adjusted to 100 ° C. or less. At this time, as shown in Figure 2c, the ultra-fine oxide layer generated by the silicon (Si) diffused in the process of forming the titanium silicide layer 21 is changed to the nitride film (SixNy; 100) to the titanium silicide layer 21 It exists on the surface.
도 2d를 참조하면, HxPOy를 이용하여 세정을 수행하여 질화막(100)을 완전히 제거하여 티타늄실리사이드층(21) 표면을 완전히 노출시킨다. 이때, HxPOy는 액상을 함유하는 상태를 가질 수도 있고, 액상과 기상을 함유하는 상태를 가질 수 도 있는데, 액상의 상태를 가질 경우에는 온도를 120 내지 500℃ 정도로 조절하는 것이 바람직하고, x는 1 내지 4, y는 1 내지 5 정도로 각각 조절하는 것이 바람직하다. 또한, HxPOy가 H2O를 함유할 수도 있는데, 이 경우 H2O의 함유율은 약 20% 이하로 유지하는 것이 바람직하다.Referring to FIG. 2D, cleaning is performed using H x PO y to completely remove the nitride film 100 to completely expose the surface of the titanium silicide layer 21. At this time, H x PO y may have a state containing a liquid phase, or may have a state containing a liquid phase and a gas phase, when having a liquid phase, it is preferable to adjust the temperature to about 120 to 500 ℃, It is preferable to adjust x to 1-4 and y to 1-5, respectively. In addition, although H x PO y may contain H 2 O, in this case, the content of H 2 O is preferably maintained at about 20% or less.
도 2e를 참조하면, 캐패시터용 홀(19)을 포함하는 캐패시터 절연막(18) 상부에 TiN, W, WN, Ru, RuO2, Ir, IrO2 등의 금속막을 증착하고, CMP 또는 에치백 공정에 의해 금속막을 분리시켜 하부전극(22)을 형성한다. 그 후, 하부전극(22) 및 캐패시터 절연막(18) 상에 고유전율의 유전막(23)을 형성하고, 유전막(23) 상에 TiN, W, Ru, Ir 등의 금속막으로 상부전극(24)을 형성하여 MIM 구조의 캐패시터(200)를 완성한다. 이때, 유전막(23)으로서는 탄탈륨산화물(Ta2O5), 알루미늄산화물(Al2 O3), 하프늄산화물(HfO2), 실리콘산화물(SiO2), 지르코늄산화물(ZrO3)의 단일막 또는 이들의 복합막을 사용한다.Referring to FIG. 2E, a metal film such as TiN, W, WN, Ru, RuO 2 , Ir, IrO 2, and the like is deposited on the capacitor insulating film 18 including the capacitor hole 19 and subjected to a CMP or etch back process. The metal film is separated to form the lower electrode 22. Thereafter, a dielectric film 23 having a high dielectric constant is formed on the lower electrode 22 and the capacitor insulating film 18, and the upper electrode 24 is formed of a metal film such as TiN, W, Ru, Ir, or the like on the dielectric film 23. To form the capacitor 200 of the MIM structure. At this time, as the dielectric film 23, a single film of tantalum oxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), silicon oxide (SiO 2 ), zirconium oxide (ZrO 3 ), or these Uses a composite membrane.
상기 실시예에 의하면, 하부전극(22)을 형성하기 전에 티타늄실리사이드층 (21) 표면의 질화막(100)을 완전히 제거함에 따라, 티타늄실리사이드층(21)에 의해 하부전극(22)과 SNC 플러그(17) 사이의 오믹콘택이 가능해지므로 우수한 콘택 저항을 얻을 수 있게 된다.According to the above embodiment, as the nitride film 100 on the surface of the titanium silicide layer 21 is completely removed before the lower electrode 22 is formed, the lower electrode 22 and the SNC plug (eg, by the titanium silicide layer 21) are removed. 17) Since ohmic contact is possible, excellent contact resistance can be obtained.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다. The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 상부 및 하부전극으로서 금속막을 사용하는 MIM 구조의 캐패시터에서 하부전극과 스토리지노드콘택(SNC) 플러그 사이의 오믹콘택이 가능해져 우수한 콘택저항을 얻을 수 있으므로 소자의 수율 및 신뢰성을 향상시킬 수 있다.The present invention described above enables the ohmic contact between the lower electrode and the storage node contact (SNC) plug in the MIM structure capacitor using the metal film as the upper and lower electrodes, thereby obtaining excellent contact resistance, thereby improving device yield and reliability. You can.
도 1은 종래 SNC 플러그와 하부전극 사이에서 발생되는 문제를 나타낸 도면.1 is a view showing a problem occurring between the conventional SNC plug and the lower electrode.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위한 단면도.2A to 2E are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
10 : 반도체 기판 11 : 필드산화막10 semiconductor substrate 11 field oxide film
12a : 게이트 12b : 하드마스크12a: Gate 12b: Hard Mask
12 : 게이트 적층구조 13 : 게이트 스페이서 12: gate stack structure 13: gate spacer
14, 16 : 제 1 및 제 2 층간절연막14, 16: first and second interlayer insulating film
15 : 비트라인 17 : SNC 플러그15 bit line 17 SNC plug
18a : 질화막 18b : 산화막18a: nitride film 18b: oxide film
18 : 캐패시터 절연막 19 : 캐패시터용 홀 18: capacitor insulating film 19: capacitor hole
20 : 티타늄 21 : 티타늄실리사이드층 20: titanium 21: titanium silicide layer
22 : 하부전극 23 : 유전막22: lower electrode 23: dielectric film
24 : 상부전극 200 : 캐패시터24: upper electrode 200: capacitor
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