KR20050110740A - Circuit board of driving discharge display panel wherin noise shielding is effectively performed - Google Patents

Abstract

The driving circuit board of the discharge display panel according to the present invention includes field effect transistor pairs whose output terminals correspond to the electrode lines of the discharge display panel. In this board, the gate drive lines of the field effect transistor pairs form a double layer in parallel with the source drive common-line of the bottom field effect transistors of the field effect transistor pairs.

Description

Circuit board of driving discharge display panel wherin noise shielding is effectively performed

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit board of a discharge display panel, and more particularly, to a drive circuit board of a discharge display panel whose output terminal includes field effect transistor pairs corresponding to electrode lines of the discharge display panel.

1 shows the structure of a three-electrode surface discharge type plasma display panel as a conventional discharge display panel. FIG. 2 shows an example of one display cell of the panel of FIG. 1. 1 and 2, between the front and rear glass substrates 10 and 13 of the conventional plasma display panel 1, the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm ), dielectric layers 11 and 15, Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), fluorescent layer 16, partition wall ( 17) and a magnesium monoxide (MgO) layer 12 as a protective layer are provided.

The address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is entirely applied in front of the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . These partitions 17 function to partition the discharge area of each display cell and to prevent optical cross talk between each display cell. The fluorescent layer 16 is formed between the partition walls 17.

The X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ) are the address electrode lines (A _R1 , A _G1 , ..., A _Gm , A _Bm ) is formed in a predetermined pattern on the back of the front glass substrate 10 to be orthogonal to each other. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) is a transparent electrode line of a transparent conductive material such as indium tin oxide (ITO) or the like (FIG. 2). X _na , Y _na ) and a metal electrode line (X _nb , Y _nb of FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ..., Y _n . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

In the driving method (see US Pat. No. 5,541,618) basically applied to such a plasma display panel, the resetting, addressing, and sustaining-discharge steps are sequentially performed in the unit subfield. Is performed. In the resetting phase, the charge states of all display cells are uniform. In the addressing step, a predetermined wall voltage is generated in the selected display cells. In the sustain-discharge step, a predetermined alternating voltage is applied to all the XY electrode line pairs so that the display cells in which the wall voltage is formed in the addressing step cause sustain-discharge. In this sustain-discharge step, a plasma is formed in the discharge space 14 of the selected display cells causing the sustain-discharge, that is, the gas layer, and the fluorescent layer 16 is excited by the ultraviolet radiation to generate light.

FIG. 3 illustrates a conventional address-display separation driving method for the Y electrode lines Y ₁ ,..., Y _n of the plasma display panel 1 of FIG. 1. Referring to FIG. 3, a unit frame is divided into eight subfields SF1, ..., SF8 to realize time division gray scale display. Further, each subfield SF1, ..., SF8 is divided into addressing periods A1, ..., A8 and sustain-discharge periods S1, ..., S8.

At the beginning of each addressing period A1, ..., A8 there is a resetting period (PR in FIG. 5) in which the charge states of all display cells are uniform.

In each addressing period A1, ..., A8, a display data signal is applied to the address electrode lines (A _R1 , A _G1 , ..., A _Gm , A _{Bm in} FIG. 1) and each Y electrode line Scan pulses corresponding to (Y ₁ , ..., Y _n ) are applied sequentially. Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are formed by the address discharge in the corresponding discharge cell, and wall charges are not formed in the discharge cell that is not.

In each sustain-discharge period S1, ..., S8, all Y electrode lines Y ₁ , ..., Y _n and all X electrode lines X ₁ , ..., X _n The display discharge pulses are alternately applied to cause display discharge in discharge cells in which wall charges are formed in corresponding addressing periods A1, ..., A6. Therefore, the brightness of the discharge display panel is proportional to the length of the sustain-discharge periods S1, ..., S8 occupied in the unit frame. The length of the sustain-discharge periods S1, ..., S8 occupied in the unit frame is 255T (T is the unit time). Therefore, it can be displayed in 256 gray scales, even if it is not displayed once in a unit frame.

Here, the time 1T corresponding to 2 ⁰ in the sustain-discharge period S1 of the first subfield SF1 corresponds to 2 ¹ in the sustain-discharge period S2 of the second subfield SF2. In the sustaining-discharging period S3 of the third subfield SF3, the time 2T corresponds to 2 ² in the sustaining-discharging period S4 of the fourth subfield SF4. The time 8T corresponding to 2 ³ is the sustaining-discharging period S5 of the fifth subfield SF5. The time 16T corresponding to 2 ⁴ is the sustaining-discharging period of the sixth subfield SF6. A time 32T corresponding to 2 ⁵ in S6, a time 64T corresponding to 2 ⁶ in the sustain-discharge period S7 of the seventh subfield SF7, and an eighth subfield SF8. In the sustaining-discharging cycle S8 of, time 128T corresponding to 2 ⁷ is set, respectively.

Accordingly, if the subfield to be displayed among the eight subfields is appropriately selected, the display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed in any of the subfields.

In the driving circuit board of the discharge display panel operating as described above, most output terminals include field effect transistor pairs corresponding to the electrode lines of the discharge display panel. Here, the gate drive lines of the field effect transistor pairs are sensitive to noise of potentials generated around them, so it is necessary to shield the noise to be applied to the gate drive lines.

Accordingly, in a conventional driving circuit board, the gate driving lines of the field effect transistor pairs form a double layer while being parallel to the common ground line as the reference potential line. Accordingly, since the noise to be applied to the gate driving lines is bypassed through the common ground line, the noise to be applied to the gate driving lines may be shielded.

However, according to the conventional driving circuit board as described above, since there is a significant difference between the average potential and the ground potential of the gate driving lines, the ground noise generated from the common ground line acts on the gate driving lines, so that the screen shaking phenomenon is caused. There is a problem that occurs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a driving circuit board of a discharge display panel which can prevent screen shaking due to effective noise shielding.

The present invention for achieving the above object is a drive circuit board of a discharge display panel whose output terminal includes field effect transistor pairs corresponding to the electrode lines of the discharge display panel. In this board, the gate drive lines of the field effect transistor pairs form a double layer in parallel with the source drive common-line of the bottom field effect transistors of the field effect transistor pairs.

According to the driving circuit board of the present invention, since noise to be applied to the gate driving lines is bypassed through the source driving common line, noise to be applied to the gate driving lines may be shielded. In addition, since the difference between the average potential of the gate driving lines and the average potential of the source driving common line is relatively small, noise generated in the source driving common line does not act on the gate driving lines, resulting in screen shaking. The phenomenon can be prevented.

Hereinafter, preferred embodiments according to the present invention will be described in detail. For reference, the prior art of FIGS. 1 to 3 is equally applied to this embodiment.

4 shows a functional configuration of a driving circuit board according to the present invention for the plasma display panel 1 of FIG.

Referring to FIG. 4, the driving circuit board of the plasma display panel 1 according to the present invention includes an image processor 66, a logic controller 62, an address driver 63, an X driver 64, and a Y driver 65. It includes. The image processor 66 converts an external video signal into an internal video signal as a digital signal. Here, the internal video signal includes 8 bits of red (R), green (G), and blue (B) image data, a clock signal, and vertical and horizontal sync signals, respectively. The logic controller 62 generates data signals S _A , X control signals S _X , and Y control signals S _Y according to an internal image signal from the image processor 66. The address driver 63 performs address electrode lines (A _R1 , A _G1 ,..., A _Gm , in FIG. 1) of the plasma display panel 1 according to data signals S _A from the logic controller 62. A _Bm ). The X driver 64 drives the X electrode lines (X ₁ ,..., X _n of FIG. 1) according to the X control signals S _X from the logic controller 62. The Y driver 65 drives the Y electrode lines (Y ₁ ,..., Y _{n in} FIG. 1) according to the Y control signals S _Y from the logic controller 62.

5 illustrates driving signals applied to the plasma display panel 1 of FIG. 1 in the unit sub-field of FIG. 3 by the driving circuit board of FIG. 4.

In FIG. 5, reference numeral S _{AR1 ..ABm} denotes a driving signal applied to each address electrode line (A _R1 , A _G1 ,..., A _Gm , A _{Bm in} FIG. 1), and S _{X1 .. Xn} denotes an X electrode. The driving signal applied to the lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are the respective Y electrode lines (Y ₁ , ... Y _{n in} FIG. 1). Indicates a drive signal applied to. FIG. 6 illustrates a wall charge distribution of one display cell immediately after a gradual rising potential is applied to the Y electrode lines Y ₁ , ... Y _n in the reset period PR of FIG. 5. FIG. 7 illustrates wall charge distribution of one display cell at the end of the reset period PR of FIG. 6. 6 and 7 the same reference numerals as used in FIG. 2 indicate the object of the same function.

Referring to FIG. 5, in the resetting period PR of the unit sub-field SF, first, the potential applied to the X electrode lines X ₁ ,..., X _n is set from the ground potential V _G. The second potential V _S is continuously raised to, for example, 155 volts (V). Here, the ground potential V _G is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, between the X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), and the X electrode lines (X ₁ , ..., X) A weak discharge occurs between _n ) and the address electrode lines A ₁ , ..., A _m , and negative wall charges are formed around the X electrode lines X ₁ , ..., X _n . .

Next, the potential applied to the Y electrode lines Y ₁ ,..., Y _n is third from the second potential V _S , for example, from 155 volts V to the second potential V _S. It is continuously raised to the highest potential (V _SET + V _S ), which is as high as the potential (V _SET ), for example 355 volts (V). Here, the ground potential V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n ), while the Y electrode lines (Y ₁ , A weaker discharge occurs between ..., Y _n ) and the address electrode lines A _R1 , ..., A _Bm . Here, Y electrode lines (Y _1, ..., Y _n) and the address electrode lines _{(A R1, ..., A Bm} ) than the discharge electrode line Y between the (Y _1, ..., Y _n) and the X-electrode lines (X _1, ..., X _n) because the discharge is stronger between is, the X electrode lines (X _1, ..., X _n) of negative polarity wall around Because the charges were formed. Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ , ..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 7).

Next, in the state where the potential applied to the X electrode lines X ₁ ,..., X _n is maintained at the second potential V _S , the Y electrode lines Y ₁ ,..., Y _n The potential applied to) is continuously lowered from the second potential V _S to the ground potential V _G. Here, the ground potential V _G is applied to the address electrode lines A _R1 ,..., A _Bm . Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,. Some of the negative wall charges around..., Y _n ) move around the X electrode lines X ₁ ,..., X _n (see FIG. 7). In addition, since the address electrode lines (A _R1, ..., A _Bm) is applied with the ground potential (V _G), the address electrode lines positive wall charges around the (A _R1, ..., A _Bm) are Slightly increased.

Accordingly, in a subsequent addressing period PA, the display data signal is applied to the address electrode lines, and the Y electrode lines Y ₁ biased to the fourth potential V _SCAN lower than the second potential V _S. , ..., Y _n ), as the scan signals of the ground potential V _G are sequentially applied, smooth addressing may be performed. The display data signal applied to each of the address electrode lines A _R1 , ..., A _Bm is applied with the positive address potential V _A when the display cell is selected and the ground potential V _G when the display cell is not selected. do. Accordingly, when the display data signal of the positive address potential V _A is applied while the scan pulse of the ground potential V _G is applied, wall charges are formed by the address discharge in the corresponding display cell. Wall charges do not form. Here, for more accurate and efficient address discharge, the second potential V _S is applied to the X electrode lines X ₁ , ... X _n .

In the following sustain-discharge period PS, the maintenance of the second potential V _{S at} all the Y electrode lines Y ₁ , ... Y _n and the X electrode lines X ₁ , ... X _n . The discharge pulses are alternately applied, causing a discharge for sustain-discharge in the display cells in which wall charges are formed in the corresponding addressing period PA.

FIG. 8 illustrates a scan driving circuit AC and a switching output circuit SIC in the Y driver 65 of FIG. 4. FIG. 9 shows that the gate drive lines L ₁ to L ₅ of FIG. 8 form a double layer while being parallel to the source drive common-line 84 of FIG. 8.

8 and 9, the Y driver 65 includes a reset holding circuit RSC, a scan driving circuit AC, a switching output circuit SIC, and a gate driving circuit 81. The reset / sustain circuit RCS generates drive signals to be applied to the Y electrode lines Y ₁ ,... Y _n in the reset period PR and the sustain-discharge period PS. The scan driving circuit AC generates driving signals to be applied to the Y electrode lines Y ₁ ,... Y _n in the addressing period PA. In the switching output circuit SIC, the upper field effect transistors YU1, ..., YUn and the lower field effect transistors YL1, ..., YLn are arranged so that each upper field effect transistor and each lower electric field are arranged. The common output lines of the effect transistors are connected so as to correspond to the respective Y electrode lines Y ₁ , ..., Y _n . The gate driving circuit 81 drives the gates of the field effect transistors according to the Y control signals S _X from the logic controller 62 of FIG. 4.

The capacitor C _SP included in the scan driving circuit AC is connected to the drain driving common line 85 of all the upper field effect transistors YU1,..., And YUn of the switching output circuit SIC. Are connected between the source driving common-line 84 of all the lower field effect transistors YL1, ..., YLn. Here, the capacitor C _SP is applied as a potential by the charging of the capacitor C _SP is applied to the drain driving common line 85 of the upper field effect transistors YU1,..., YUn of the switching output circuit. The constant voltage can always be maintained.

In the scan driving circuit AC, the drain driving common line 85 of all the upper field effect transistors YU1, ..., YUn of the switching output circuit SIC and the scanning bias potential V _SCAN A diode D _U as a one-way current control element is connected between the terminals. Accordingly, the capacitor C _SP is charged through the diode D _U , and the scanning bias potential V _SCAN due to the charging is applied to the field effect transistors YU1, ... YUn) is applied to the drain drive common-line 85. In addition, a large power field effect transistor S _SCL is connected between the source driving common line 84 and the ground line of all the lower field effect transistors YL1,..., YLn of the switching output circuit SIC. .

Referring to FIGS. 1, 5, and 8, the operation process of the Y driver of FIG. 8 will be described.

At times other than the scan time (addressing time, PA), i.e., the reset period PR and the sustain-discharge period PS, the high power field effect transistor S _SCL is turned off to reset / hold The drive signals O _RS from the circuit RSC are applied to the source drive common-line 84 of all the bottom field effect transistors YL1,... YLn of the switching output circuit SIC. In addition, all the lower field effect transistors YL1, ..., YLn of the switching output circuit SIC are turned on and all the upper field effect transistors YU1, ..., YUn are turned off. (turn off). Accordingly, the drive signals O _RS from the reset / sustain circuit RCS are transferred through all the lower field effect transistors YL1,..., YLn to all Y electrode lines Y ₁ ,... Y _n ).

In the scanning time, that is, the addressing period PA, the scanning bias potential V _SCAN by the charging of the capacitor C _SP is determined by the field effect transistors YU1,..., YUn of the switching output circuit SIC. Is applied to the drain drive common line 85. In addition, since the large power field effect transistor S _SCL is turned on, the ground potential V _G of FIG. 5 is _passed through the large power field effect transistor S _SCL to the lower electric field of the switching output circuit SIC. It is applied to the effect transistors YL1, ..., YLn. Here, the bottom field effect transistor connected to one Y electrode line to be scanned is turned on and the top field effect transistor is turned off. In addition, the bottom field effect transistors connected to all remaining Y electrode lines that are not to be scanned are turned off and the top field effect transistors are turned on. Accordingly, the scan ground potential V _G is applied to one Y electrode line to be scanned, and the scan bias potential V _SCAN is applied to all the other Y electrode lines that are not to be scanned.

In the addressing period PA, when the scanning ground potential V _G is applied to one Y electrode line to be scanned, the display data signal is applied to the address electrode lines A _R1 ,..., A _Bm . At the time point, when the application of the display data signal to the address electrode lines A _R1 ,..., A _Bm ends, and when the scanning ground potential V _G is applied to the Y electrode line to be scanned ends. The current paths at the time point are as follows.

First, at the time when the scanning ground potential V _G is applied to one Y electrode line to be scanned, one lower transistor of the switching output circuit SIC from display cells (electric capacitors) connected to the one Y electrode line to be scanned and The current flows to the ground terminal through the high power transistor S _SCL of the scan driving circuit AC.

Second, at the time when the display data signal is applied to the address electrode lines A _R1 , ..., A _Bm , the discharge current flows from the address electrode lines to which the selection potential V _A is applied to one Y electrode line being scanned. In addition to all the non-scanned Y electrode lines, the upper field effect transistors of the switching output circuit SIC, the capacitor C _SP of the scan driving circuit AC, and the high power field effect transistor S _SCL . Current flows through the terminal to the ground terminal.

Third, at the time when the application of the display data signal to the address electrode lines A _R1 , ..., A _Bm is terminated, the upper portion of the switching output circuit SIC from the capacitor C _SP of the scan driving circuit AC. Current flows through the field effect transistors, the Y electrode lines, to the address electrode lines A _R1 ,..., A _Bm .

Fourth, when the scanning ground potential V _G is applied to the Y electrode line to be scanned, the field effect of the upper side of the switching output circuit SIC is increased from the capacitor C _SP of the scan driving circuit AC. Current flows through the transistors and the Y electrode lines to the display cells (electric capacitors).

Here, the gate driving lines L ₁ to the gate driving circuit 81 are formed. L ₉₆₀ is sensitive to noise of potentials generated around it, so it is necessary to shield the noise to be applied to these gate drive lines. Accordingly, the gate driving lines L ₁ to L ₉₆₀ forms a double layer in parallel with the source drive common-line 84 (see FIG. 9).

Therefore, the gate driving lines L ₁ to Since the noise to be applied to L ₉₆₀ is bypassed through the source driving common line 84, the gate driving lines L ₁ to L ₉₆₀ . Noise to be applied to L ₉₆₀ may be shielded. In addition, the gate driving lines L ₁ to Since the difference between the average potential of L ₉₆₀ and the average potential of the source driving common-line 84 is relatively small, the noise generated in the source driving common-line 84 is reduced to the gate driving lines L ₁ to ₁ . L ₉₆₀ ), the screen shake phenomenon can be prevented.

On the other hand, the average potential of the gate of the high power transistor S _SCL of the scan driving circuit AC is lower than the average potential of the source driving common line 84. Accordingly, the line 831 connected from the gate driving circuit 81 to the gate of the high power transistor S _SCL preferably forms a double layer while being parallel to the common ground line.

As described above, according to the driving circuit board of the discharge display panel according to the present invention, since the noise to be applied to the gate driving lines is bypassed through the source driving common line, the noise to be applied to the gate driving lines. Can be shielded. In addition, since the difference between the average potential of the gate driving lines and the average potential of the source driving common line is relatively small, noise generated in the source driving common line does not act on the gate driving lines, thereby preventing the screen shaking. Can be.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

1 is a perspective view showing an internal structure of a plasma display panel of a three-electrode surface discharge method as a conventional discharge display panel.

FIG. 2 is a cross-sectional view illustrating an example of one display cell of the panel of FIG. 1.

FIG. 3 is a timing diagram illustrating a conventional address-display separation driving method for Y electrode lines of the plasma display panel of FIG. 1.

4 is a block diagram illustrating a functional configuration of a driving circuit board according to the present invention for the plasma display panel of FIG. 1.

FIG. 5 is a timing diagram illustrating driving signals applied to the plasma display panel of FIG. 1 in the unit sub-field of FIG. 3 by the driving circuit board of FIG. 4.

FIG. 6 is a cross-sectional view illustrating a wall charge distribution of one display cell immediately after a gradual rising potential is applied to the Y electrode lines in the resetting period of FIG. 5.

FIG. 7 is a cross-sectional view illustrating a wall charge distribution of one display cell at the end of the reset period of FIG. 5.

FIG. 8 is a view illustrating a scan driving circuit and a switching output circuit in the Y driver of FIG. 4.

FIG. 9 is a plan view illustrating that the gate drive lines of FIG. 8 form a double layer while being parallel to the source drive common-line of FIG. 8.

<Explanation of symbols for the main parts of the drawings>

1 ... discharge display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 fluorescent layers, 17 bulkheads,

X ₁ , ..., X _n ... X electrode line, Y ₁ , ..., Y _n ... Y electrode line,

A ₁ , ..., A _m ... address electrode line, X _na , Y _na ... transparent electrode line,

X _nb , Y _nb ... metal electrode line, SF ₁ , ... SF ₈ ... sub-field,

S _Y1 , ..., S _Yn ... Y electrode drive signal, V _G ... ground potential,

S _X1 , ..., S _Xn ... X electrode drive signal, SF ... unit sub-field,

S _AR1 .. _ABm ... display data signal, 62 ... logical control,

63..Address drive, 64 ... X drive,

65 ... Y drive unit, 66 ... image processing unit,

RSC ... reset / hold circuit, AC ... scan drive circuit,

SIC ... switching output circuit.

Claims (6)

A drive circuit board of a discharge display panel having an output terminal including field effect transistor pairs corresponding to electrode lines of the discharge display panel, And the gate driving lines of the field effect transistor pairs are parallel to the source driving common line of the lower field effect transistors of the field effect transistor pairs and form a double layer. The method of claim 1, An image processor converting an external image signal into an internal image signal as a digital signal; A controller configured to generate data signals, X control signals, and Y control signals according to an internal image signal from the image processor; An address driver for driving address electrode lines of the discharge display panel according to data signals from the controller; An X driver for driving X electrode lines of the discharge display panel formed to intersect the address electrode lines according to X control signals from the controller; And And a Y driver for driving Y electrode lines parallel and alternating with the X electrode lines according to Y control signals from the controller. The method of claim 2, The Y drive unit, A switching output circuit connected to each of the top transistors and the bottom transistors of the field effect transistor pairs so as to correspond to the respective Y electrode lines; And A capacitor coupled between the drain drive common-line of all upper transistors of the switching output circuit and the source drive common-line of all lower transistors, And a voltage applied by the charging of the capacitor is applied to the drain driving common line of the upper transistors of the switching output circuit. The method of claim 3, wherein in the Y drive unit, The one-way current control element is connected between the common power supply line of all the upper transistors of the switching output circuit and the terminal of the scan bias voltage, and the capacitor is charged through the one-way current control element, and the scan bias voltage by the charging And a driving circuit board of a three-electrode discharge display panel applied to the drain driving common line of the upper transistors of the switching output circuit. The method of claim 4, wherein And a driving circuit board of the discharge display panel wherein the one-way current control element is a diode. The switching transistor of claim 4, wherein a switching transistor is connected between a common power line and a ground line of all the lower transistors of the switching output circuit. A driving circuit board of a discharge display panel in which the switching transistor is turned off at a time other than a scanning time.