KR20050090679A - Method of manufacturing thin film transistor substrate - Google Patents

Abstract

The present invention relates to a method of manufacturing a thin film transistor substrate, comprising: depositing a first metal layer etched by a first etching solution; Depositing a second metal layer etched by a second etching solution on the first metal layer; Forming a photoresist pattern on the second metal layer; First etching the second metal layer with the second etching solution; Etching the first metal layer with the first etching solution to form a first metal layer pattern; And second etching the first etched second metal layer with the second etching solution to form a second metal layer pattern. As a result, in the method of manufacturing a thin film transistor substrate in which a double layer wiring is formed using different etching solutions, it is possible to prevent the occurrence of defects by removing undercuts caused by etching the lower layer more than the upper layer.

Description

Method of Manufacturing Thin Film Transistor Substrate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor substrate, and more particularly, to a method for manufacturing a thin film transistor substrate in which the method for forming a double layer wiring is improved.

In general, the thin film transistor substrate is used as a circuit board for driving each pixel independently in a liquid crystal display (LCD), an organic luminescence (EL) display, or the like. In the thin film transistor substrate, scan signal lines or gate lines for transmitting scan signals and image signal lines or data lines for transmitting image signals are formed. The thin film transistor is connected to the gate wiring and the data wiring, the pixel electrode connected to the thin film transistor, the gate insulating film covering and insulating the gate wiring, and the protective film covering and insulating the thin film transistor and the data wiring. The thin film transistor includes a semiconductor layer pattern forming a gate electrode and a channel which are part of the gate wiring, a source electrode and a drain electrode which is a part of the data wiring, a gate insulating film and a protective film. Here, the thin film transistor is a switching element that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

The wirings such as the gate wiring and the data wiring may be made of a single layer of metal or alloy, but are often formed of multiple layers to compensate for the disadvantages of each metal or alloy and to obtain desired physical properties. For example, aluminum or an aluminum alloy is used as the lower layer, and chromium or molybdenum is used as the upper layer. The lower layer uses aluminum or aluminum alloy with low specific resistance to prevent signal resistance due to wiring resistance, and the upper layer uses chemicals to compensate for the shortcomings of aluminum or aluminum alloy where corrosion resistance by chemicals is weak and easily oxidized to cause disconnection. The upper layer is formed of chromium or molybdenum, which is highly resistant to chemicals.

In forming multi-layer wiring, when aluminum or aluminum alloy is used as the lower layer and chromium is used as the upper layer, different etching solutions must be used for etching.

However, when the multiple layers are etched using different etching solutions, undercuts are etched more than the upper layers etched later, which is why the lower layer to be etched later is caused by a defect in which horizontal lines are generated in the liquid crystal panel of the liquid crystal display. do.

In particular, in the case of high-resolution products, even if the minimum undercut is generated in the wet etching process, it is difficult to overcome the horizontal line defect.

Accordingly, an object of the present invention, in the method of manufacturing a thin film transistor substrate in which a double layer wiring is formed using different etching solutions, the undercut caused by the etching of the lower layer more than the upper layer can be removed to prevent the occurrence of defects. It is to provide a method for manufacturing a thin film transistor substrate.

According to the present invention, there is provided a method of manufacturing a thin film transistor substrate, comprising: depositing a first metal layer etched by a first etching solution; Depositing a second metal layer etched by a second etching solution on the first metal layer; Forming a photoresist pattern on the second metal layer; First etching the second metal layer with the second etching solution; Etching the first metal layer with the first etching solution to form a first metal layer pattern; And second etching the first etched second metal layer with the second etching solution to form a second metal layer pattern.

The first metal layer preferably includes aluminum, and the first etching solution may include phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), and acetic acid (CH ₃ COOH).

The second metal layer is preferably characterized in that it comprises chromium, the second etching solution is nitric acid (HNO ₃ ) and the citric ammonium nitrate ((NH ₄ ) ₂ Ce (NO ₃ ) ₆ ) It is preferable to include.

In the method of manufacturing the thin film transistor substrate, the first and second metal layers may be gate wiring layers. In addition, the first and second metal layers may be data wiring layers.

According to the manufacturing method of the thin film transistor substrate, it is possible to prevent the occurrence of defects by removing the undercut that the lower layer is etched more than the upper layer in the process of forming the wiring of the double layer.

Hereinafter, a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

Prior to the description, in various embodiments, components having the same configuration will be representatively described in the first embodiment using the same reference numerals, and in other embodiments, only the configuration different from the first embodiment will be described. do.

In addition, a method of manufacturing a thin film transistor (TFT) substrate shown in the present specification is schematically illustrated by highlighting the features of the method of manufacturing an amorphous silicon thin film transistor (a-Si TFT) substrate for a liquid crystal display device as an example. Let's do it.

First, a structure of a thin film transistor substrate formed by a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 as follows.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II ′ of the thin film transistor substrate illustrated in FIG. 1.

Gate wirings 22, 24, and 26 formed of a double layer of first gate wiring layers 221, 241, and 261 and second gate wiring layers 222, 242, and 262 are formed on the substrate material 10. The first gate wiring layers 221, 241, and 261 include aluminum or an aluminum alloy, and the second gate wiring layers 222, 242, and 262 include chromium.

The material of the first and second gate wiring layers 221, 222, 241, 242, 261, and 262 is not limited to the above-described embodiment, and may be made of a material of a metal which is etched by different etching solutions. Do.

The gate wires 22, 24, and 26 are connected to the gate line 22 and the ends of the gate line 22, and the gate pad 24 and the gate line which receive a gate signal from the outside and transfer the gate signal to the gate line 22. A gate electrode 26 of the thin film transistor connected to 22; The gate pad 24 is widened for easy connection with an external circuit.

The substrate material 100 is an insulating substrate made of a material such as glass, quartz, or plastic. The gate insulating film 30 made of silicon nitride (SiN ^x ) is formed on the substrate material to form the gate wirings 22, 24, and 26. Covering.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30 of the gate electrode 26, and a silicide or n-type impurity is doped with high concentration on the semiconductor layer 40. Intermediate layers 55 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the intermediate layers 55 and 56 and the gate insulating layer 30, data wirings 62, 65, 66, which consist of a double layer of first data wiring layers 651, 661, 681 and second data wiring layers 652, 662, 682, 68) is formed. The first data wiring layers 651, 661, and 681 include aluminum or an aluminum alloy, and the second data wiring layers 652, 662, and 682 include chromium.

The materials of the first and second data wiring layers 651, 652, 661, 662, 681, and 682 are not limited to the above-described embodiments, and may be made of a material of metal etched by different etching solutions. Do.

The data lines 62, 65, 66, and 68 are branched lines of the data line 62 and the data line 62 defining the pixel by crossing the gate line 22 and extending to the upper portion of the intermediate layer 55 ( 65, which is separated from the source electrode 65 and connected to the ends of the drain electrode 66 and the data line 62 formed on the intermediate layer 56 opposite to the source electrode 65 with the gate electrode 26 as a center. And a data pad 68 that receives an image signal from the outside and transfers the image signal to the data line 62. The data pad 68 is extended in width for easy connection with an external circuit.

A-Si: C: O film or a deposited on the data lines 62, 65, 66, 68 and on the semiconductor layer 40 which is not covered by silicon nitride (SiNx) or plasma enhanced chemical vapor deposition (PECVD) A protective film 70 made of a -Si: O: F film (low dielectric constant CVD film), an arcle-based organic insulating film, and the like is formed. The a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a dielectric constant of 4 or less (the dielectric constant has a value between 2 and 4). The dielectric constant is very low. Therefore, even a thin thickness does not cause a parasitic capacity problem. In addition, it is excellent in adhesion with other films and step coverage. Moreover, since it is an inorganic CVD film, heat resistance is excellent compared with an organic insulating film. In addition, the a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a 4 to 10 times faster process time than the silicon nitride film in terms of deposition rate and etching rate. It is also very advantageous in terms of.

In the passivation layer 70, contact holes 76 and 78 are formed to expose portions of the drain electrode 66 and the data pad 68, respectively, and the contacts exposing a portion of the gate line pat 24 together with the gate insulating layer 30. A hole 74 is formed. In this case, the contact holes 74 and 78 exposing portions of the gate pad 24 and the data pad 68 may have a tapered structure, and may be formed in various shapes having an angle or a circle.

The pixel electrode 82, which is electrically connected to the drain electrode 66 and positioned in the pixel region, is formed on the passivation layer 70 through the contact hole 76. Further, on the passivation layer 70, contact auxiliary members 86 and 88, which are connected to the gate pad 24 and the data pad 68, respectively, are formed through the contact holes 74 and 78, respectively. The pixel electrode 82 and the contact assistants 86 and 88 are made of indium tin oxide (ITO) or indium zinc oxide (IZO).

4 and 5, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate lines 22, 24, and 26. It is also possible to add a storage capacitor wiring.

In addition, the pixel electrode 82 may also be formed to overlap the data line 62 to maximize the aperture ratio. Even if the pixel electrode 82 is formed to overlap the data line 62 in order to maximize the aperture ratio, if the low dielectric constant CVD film or the like of the protective film 70 is formed, the parasitic capacitance formed therebetween will be small. I can keep it.

According to a first embodiment of the present invention, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 1 and 2 will be described in detail as follows.

First, as shown in FIG. 3, the first gate metal layer 201 made of aluminum or an aluminum alloy having excellent physicochemical properties on the substrate material 10 and the corrosion resistance by chemicals are weak and easily oxidized to cause disconnection. In order to compensate for the disadvantages of the aluminum or aluminum alloy generated, the second gate metal layer 202 made of chromium having a high corrosion resistance to chemicals is successively stacked.

Next, as shown in FIG. 4, a photosensitive film is coated on the second gate metal layer 202 and patterned by a photolithography process using a mask to form a first photosensitive film pattern 901 for forming a gate wiring.

Next, as shown in FIG. 5, the second gate metal layer 202 is first etched with the second etching solution. The second etching solution includes nitric acid (HNO ₃ ) and cyclic ammonium nitrate ((NH ₄ ) ₂ Ce (NO ₃ ) ₆ ).

Next, as shown in FIG. 6, the first gate metal layer 201 is etched with the first etching solution to form first gate wiring layers 221, 241, and 261. In this case, the first gate wiring layers 221, 241, and 261 are etched more than the first gated second metal layer 202 to be in an undercut state. The first etching solution includes nitric acid (HNO ₃ ) and cyclic ammonium nitrate ((NH ₄ ) ₂ Ce (NO ₃ ) ₆ ).

Next, as shown in FIG. 7, the second gate metal layer 202 firstly etched with the second etching solution is secondly etched to form second gate wiring layers 222, 242, and 262. Subsequently, as shown in FIG. 8, when the first photoresist layer pattern 901 is removed, the first gate wiring layers 221, 241, and 261 have a step shape wider than that of the second gate wiring layers 222, 242, and 262. Gate wirings 22, 24, and 26 having vertical cross sections are formed.

Next, as shown in FIG. 9, the three-layer film of the gate insulating film 30 made of silicon nitride, the semiconductor layer 40 made of amorphous silicon, and the doped amorphous silicon layer 50 is successively stacked, and the semiconductor layer 40 ) And the doped amorphous silicon layer 50 are photo-etched to form an island-like semiconductor layer 40 and an intermediate layer 50 on the gate insulating layer 30 on the gate electrode 24.

Next, the first data metal layer made of aluminum or aluminum alloy having excellent physicochemical properties, and chemical resistance in order to compensate for the weaknesses of aluminum or aluminum alloys, which are easily oxidized due to weak corrosion resistance by chemicals and cause disconnection. The second data metal layer made of this strong chromium material is successively laminated.

Subsequently, patterning is performed through a photolithography process in the same manner as the above-described gate wiring is formed, and as shown in FIG. 10, the data line 62 and the data line 62 intersecting with the gate line 22 are connected. And a source electrode 65 extending to an upper portion of the gate electrode 26, and separated from the source electrode 65 and having a drain electrode 66 facing the source electrode 65 around the gate electrode 26. A data wiring is formed.

Here, the method of forming the double data wiring layers 651, 652, 661, 662, 681, and 682 by etching the double data metal layer may include the first and second gate wiring layers 221, 222, 241, 242, and 261. , 262).

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIG. 11, the silicon nitride film, the a-Si: C: O film, or the a-Si: O: F film is grown by chemical vapor deposition (CVD) or an organic insulating film is applied to the protective film 70. ).

Subsequently, the passivation layer 70 is patterned together with the gate insulating layer 30 by a photolithography process, thereby forming contact holes 74 and 76 exposing a part of the gate pad 24, a drain electrode 66, and a part of the data pad 68. , 78).

Next, as shown in FIGS. 1 and 2, the ITO or IZO film is deposited and photo-etched to contact the pixel electrode 82 and the contact holes 74 and 78 connected to the drain electrode 66 through the contact hole 76. The contact auxiliary members 86 and 88 which are connected to the end portion 24 of the gate line and the end portion 68 of the data line are respectively formed therethrough. It is preferable to use nitrogen as the gas used in the pre-heating process before laminating ITO or IZO.

In the above-described embodiment, the gate wirings 22, 24, 26 and the data wirings 62, 65, 66, and 68 are all formed in a double layer. However, the gate wirings 22, 24, 26 and the data wiring 62 are formed as necessary. , Double layer may be used for any one of the two layers 65, 66, and 68, and only one of the gate lines 22, 24, and 26 and the data lines 62, 65, 66, and 68 may form the double layer according to the present invention. Of course, it can be formed using a method.

In addition, in the above-described embodiment, both the gate wirings 22, 24, 26 and the data wirings 62, 65, 66, and 68 include aluminum or an aluminum alloy in the first metal layer and chromium in the second metal layer. As a matter of course, only one of the gate wirings 22, 24, 26 and the data wirings 62, 65, 66, and 68 may apply the above-described double layer material.

As described above, according to the method of manufacturing a thin film transistor substrate using five masks according to the first exemplary embodiment of the present invention, the lower layer of the double layer wiring, which is etched by using different etching solutions, is etched more than the upper layer. It is possible to prevent the occurrence of defects by removing the undercut that occurs.

The first embodiment described above is a case where five masks are used in the manufacture of the thin film transistor substrate. Next, a manufacturing method of the thin film transistor substrate manufactured using four masts according to the second embodiment of the present invention. Explain.

First, a structure of a thin film transistor substrate formed by a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention will be described in detail with reference to FIGS. 12, 13A, and 13B.

12 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 13A and 13B are taken along lines XIIIa-XIIIa 'and XIIIb-XIIIb' of the thin film transistor substrate shown in FIG. 12. This is a cross section.

On the substrate material 10, the gate wirings 22, 24, and 26 are formed of the double layers of the first gate wiring layers 221, 241, and 262 and the second gate wiring layers 222, 242, and 262, as in the first embodiment. Is formed. The first gate wiring layers 221, 241 and 262 include aluminum or an aluminum alloy, and the second gate wiring layers 222, 242 and 262 include chromium.

In addition, the storage electrode line 28 is formed on the substrate material 10 in parallel with the gate line 22. The storage electrode line 28 also includes a double layer of the first gate wiring layer 281 and the second gate wiring layer 282. The storage electrode line 28 overlaps with the conductor 64 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves charge storage capability of the pixel. The pixel electrode 82 and the gate line (to be described later) It may not be formed if the holding capacity resulting from the overlap of 22) is sufficient. The same voltage as that of the common electrode of the upper substrate is usually applied to the storage electrode line 28.

The material of the first and second gate wiring layers 221, 222, 241, 242, 261, 262, 281, and 282 is not limited to the above-described embodiment, and is made of a material of a metal which is etched by different etching solutions. It may be anything.

A gate insulating film 30 made of silicon nitride (SiNx) is formed on the gate wirings 22, 24, 26 and the storage electrode line 28 to cover the gate wirings 22, 24, 26 and the storage electrode line 28.

Semiconductor layer patterns 42 and 48 made of a semiconductor such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and n-type impurities such as phosphorus (P) are formed on the semiconductor layer patterns 42 and 48. Interlayer patterns 55, 56, 58 made of highly doped amorphous silicon are formed.

On the intermediate layer patterns 55, 56, and 58, the data line 62 including the double layers of the first data wiring layers 621, 641, 651, 661, and 681 and the second data wiring layers 622, 642, 652, 662, and 682. 64, 65, 66, 68) are formed. The first data wiring layers 621, 641, 651, 661, and 681 include aluminum or an aluminum alloy, and the second data wiring layers 622, 642, 652, 662, and 682 include chromium.

The material of the first and second data wiring layers 621, 622, 641, 642, 651, 652, 661, 662, 681, and 682 is not limited to the above-described embodiments, and the metals are etched by different etching solutions. If the material is made of any one.

The data line is formed in the vertical direction and is a branch of the data line 62 and the data line 62 which are connected to one end of the data line 62 and have an end portion 68 of the data line to which an image signal from the outside is applied. Data line portions 62 and 68 connected to the source electrode 65 and the data line 62 of the thin film transistor and made of a data pad 68 for receiving an image signal from the outside and transferring the image signal to the data line 62. And a drain of the thin film transistor, which is separated from the data line portions 62, 68, and 65, and is located opposite the source electrode 65 with respect to the gate electrode 26 or the channel portion E of the thin film transistor. It also includes a conductor 64 for a storage capacitor located on the electrode 66 and the storage electrode line 28. When the storage electrode line 28 is not formed, the storage capacitor conductor 64 is also not formed.

The intermediate layer patterns 55, 56, and 58 lower the contact resistance between the semiconductor layer patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the intermediate layer pattern 55 of the data line portion is the same as the data line portions 62, 68, and 65, and the intermediate layer pattern 56 for the drain electrode is the same as the drain electrode 66, and the intermediate layer pattern 58 for the storage capacitor is formed. Is the same as the conductor 64 for the storage capacitor.

The semiconductor layer patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66 and 68 and the intermediate layer patterns 55, 56 and 58 except for the channel portion E of the thin film transistor. have. Specifically, the semiconductor capacitor pattern 48 for the storage capacitor, the conductor 64 for the storage capacitor, and the intermediate layer pattern 58 for the storage capacitor have the same shape, but the semiconductor layer pattern 42 for the thin film transistor has the data wiring and the intermediate layer pattern. Slightly different from the rest of it. That is, the data line parts 62, 68, 65, in particular, the source electrode 65 and the drain electrode 66 are separated from the channel portion E of the thin film transistor, and the data line portion intermediate layer pattern 55 and the intermediate layer pattern for the drain electrode are separated. Although 56 is also separated, the semiconductor layer pattern 42 for thin film transistors is connected here without disconnection to generate a channel of the thin film transistor.

On the data lines 62, 64, 65, 66 and 68, an a-Si: C: O film or a-Si: O: F film (low dielectric constant CVD) deposited by silicon nitride or plasma enhanced chemical vapor deposition (PECVD) method Film) or an organic insulating film is formed. The protective film 70 has contact holes 76, 78, 72 exposing the drain electrode 66, a part of the data pad 68 and the conductor 64 for the storage capacitor, and also together with the gate insulating film 30. It has a contact hole 74 that exposes a portion of the gate pad 24.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from the thin film transistor and generates an electric field together with the common electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as ITO or indium tin oxide (IZO), and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor 64 through the contact hole 72 to transmit an image signal to the storage capacitor conductor 64. On the other hand, contact auxiliary members 86 and 88 are formed on the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively. These contact auxiliary members 86 and 88 complement the adhesion between the end portions 24 and 68 and the external circuit device and protect the gate pad 24 and the data pad 68, but are not essential. Their application is optional.

According to a second embodiment of the present invention, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structures of FIGS. 12, 13A, and 13B will be described in detail as follows.

First, as shown in FIGS. 14A and 14B, similarly to the first embodiment, a first gate metal layer 201 made of aluminum or an aluminum alloy and a material made of chromium are formed on the substrate material 10. After the two gate metal layers 202 are successively stacked, a photoresist film is coated on the second gate metal layer 202 and patterned by a photolithography process using a mask to form a first photoresist pattern 901 for forming a gate wiring. Form.

Next, as shown in FIGS. 15A and 15B, the second gate metal layer 202 is first etched with the second etching solution. The second etching solution includes nitric acid (HNO ₃ ) and cyclic ammonium nitrate ((NH ₄ ) ₂ Ce (NO ₃ ) ₆ ).

Next, as illustrated in FIGS. 16A and 16B, the first gate metal layer 201 is etched with the first etching solution to form first gate wiring layers 221, 241, 261, and 281. In this case, the first gate wiring layers 221, 241, 261, and 281 are etched more than the first gated second gate metal layer 202 to be in an undercut state. The first etching solution includes nitric acid (HNO ₃ ) and cyclic ammonium nitrate ((NH ₄ ) ₂ Ce (NO ₃ ) ₆ ).

Next, as shown in FIGS. 17A and 17B, the second gate metal layer 202 firstly etched with the second etching solution may be secondly etched to form second gate pattern layers 222, 242, 262, and 282. do. 18A and 18B, when the first photoresist layer pattern 901 is removed, the first gate wiring layers 221, 241, 261, and 281 may be larger than the second gate wiring layers 222, 242, 262, and 282. Gate wirings 22, 24, 26 and sustain electrode lines 28 having wide vertical cross-sections are formed.

Next, as illustrated in FIGS. 19A and 19B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. 증착, 300 Å to 600 연속 continuous deposition, and then the first data metal layer 601 and the second data metal layer 602 are deposited by sputtering or the like to form a data line, thereby forming the data metal layer 60. Next, a photosensitive film 900 is applied thereon with a thickness of 1 µm to 2 µm.

Thereafter, the photosensitive film 900 is irradiated with light through a mask and then developed to form second photosensitive film patterns 912 and 914 for forming data wirings, as shown in FIGS. 20A and 20B. In this case, among the second photoresist patterns 912 and 914, the channel portion E of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, may be the data wiring portion C, That is, the thickness is smaller than the second portion 112 positioned at the portion where the data lines 62, 64, 65, 66, and 68 are to be formed, and all the photoresist of the other portion D is removed. At this time, the ratio of the thickness of the photoresist film 914 remaining in the channel portion E and the thickness of the photoresist film 912 remaining in the data wiring portion C should be different depending on the process conditions in the etching process described later. It is preferable that the thickness of the first portion 914 be 1/2 or less of the thickness of the second portion 912, for example, 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist film according to the position, and in order to control the light transmittance in the C region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all the polymer molecules are decomposed, so it should not be so.

This thin film 914 is developed by using a photoresist film made of a reflowable material and exposed with a conventional mask that is divided into a part that can completely transmit light and a part that cannot completely transmit light. It may be formed by reflowing a portion of the photosensitive film to a portion where the photosensitive film does not remain.

Subsequently, etching of the second photoresist pattern 914 and the underlying layers, that is, the dual data metal layers 601 and 602, the intermediate layer 50, and the semiconductor layer 40 is performed. In this case, the data line and the layers under the data line remain in the data line C, and only the semiconductor layer remains in the channel part E, and the four layers 601, 602, Both the 50 and 40 should be removed to expose the gate insulating film 30.

Here, the method of forming the double data wiring layers 621, 622, 641, 642, 651, 652, 661, 662, 681, and 682 by etching the double data metal layer may include the first and second gate wiring layers 221 described above. , 222, 241, 242, 261, 262, 281, and 282.

First, as shown in FIGS. 21A and 21B, the exposed data metal layers 601 and 602 of the other portion B are removed to expose the lower intermediate layer 50. As shown in FIGS. In this process, both a dry etching method and a wet etching method may be used. In this case, the data metal layers 601 and 602 may be etched and the second photoresist pattern 912 and 914 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the data metal layers 601 and 602 are etched and the second photoresist pattern 912 and 914 is not etched, so the second photoresist pattern 912 and 914 is also etched together. Can be. In this case, the thickness of the first portion 914 is thicker than that of the wet etching so that the first portion 914 is removed in this process so that the lower data metal layers 601 and 602 are not exposed.

In this case, as shown in FIGS. 21A and 21B, only the data metal layer of the channel portion E and the data wiring portion D, that is, the data wiring layer 67 for the source / drain and the conductor 64 for the storage capacitor, remains. The data metal layers 601, 602 in part B are all removed to reveal the underlying intermediate layer 50. The remaining data wiring layers 67 and 64 have the same shape as the data wirings 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the second photoresist patterns 912 and 914 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 22A and 22B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 914 of the photosensitive film by a dry etching method. do. At this time, the second photoresist pattern 912 and 914, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. It is preferable to perform the etching under the conditions, in particular, the etching conditions for the second photoresist pattern 912, 914 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etch ratios of the second photoresist patterns 912 and 914 and the semiconductor layer 40 are the same, the thickness of the first portion 914 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50. .

In this way, as shown in FIGS. 22A and 22B, the first portion 914 of the channel portion E is removed to reveal the source / drain wiring layer 67, and the intermediate layer 50 and the semiconductor of the other portion D. The layer 40 is removed to reveal the gate insulating film 30 thereunder. On the other hand, since the second portion 912 of the data line part C is also etched, the thickness becomes thin. In this step, the semiconductor layer patterns 42 and 48 are completed. Reference numerals 55 and 58 designate an intermediate layer pattern under the source / drain wiring layer 67 and an intermediate layer pattern under the storage capacitor conductor 64, respectively.

Subsequently, ashing of the photoresist film remaining on the surface of the source / drain wiring layer 67 of the channel portion E is removed.

Next, as shown in FIGS. 23A and 23B, the source / drain interconnection layer 67 of the channel portion E and the source / drain interlayer pattern 55 thereunder are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain wiring layer 67 and the intermediate layer pattern 57. The etching may be performed by wet etching with respect to the source / drain wiring layer 67 and with respect to the intermediate layer pattern 57. It can also be performed by dry etching. In the former case, it is preferable to perform etching under a condition where the etching selectivity of the source / drain wiring layer 67 and the intermediate layer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor layer pattern 42 remaining in the. In the latter case of alternating between wet etching and dry etching, the side surfaces of the source / drain wiring layer 67 to be wet etched are etched, but the dry layered intermediate layer pattern 57 is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor layer pattern 42 may be a mixed gas of the mixed gas of CF ₄ and HCl and CF ₄ and O _2, the CF ₄ and O ₂ When used, the semiconductor layer pattern 42 can be left in a uniform thickness. In this case, as shown in FIG. 23B, a portion of the semiconductor layer pattern 42 may be removed to reduce the thickness, and the second portion 912 of the second photoresist pattern may also be etched to some extent. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the second portion 912 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. Of course, it is preferable that 2 photosensitive film patterns are thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist portion 912 remaining in the data line part C is removed. However, the removal of the second portion 112 may be performed after removing the channel portion E source / drain wiring layer 67 and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

Next, as shown in FIGS. 24A and 24B, a silicon nitride, an a-Si: C: O film, or an a-Si: O: F film is grown by chemical vapor deposition (CVD) or an organic insulating film is applied to the protective film. Form 70.

Next, as shown in FIGS. 25A to 25B, the protective film 70 is photo-etched together with the gate insulating film 30 to drain the electrode 66, the end portion 24 of the gate line, the end portion 68 of the data line, and the like. Contact holes 76, 74, 78 and 72 are respectively formed to expose the conductor 64 for the storage capacitor.

Finally, as shown in FIGS. 13A and 13B, a pixel electrode connected to the drain electrode 66 and the storage capacitor conductor 64 by depositing and photo-etching an ITO layer or IZO layer having a thickness of 400 μs to 500 μs ( 82, contact auxiliary members 86 and 88 connected to the gate pad 24 and the data pad 68, respectively.

On the other hand, as a gas used in the pre-heating process before laminating ITO or IZO, it is preferable to use nitrogen, which is the metal film 24 exposed through the contact holes 72, 74, 76, and 78. This is to prevent the metal oxide film from being formed on the upper portions of 64, 66 and 68.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48 may be formed using a single mask, and the manufacturing process may be simplified by separating the source electrode 65 and the drain electrode 66 in this process.

On the other hand, in the second embodiment of the present invention, the gate wirings 22, 24, 26, 28 and the data wirings 62, 64, 65, 66, 68 are all formed in a double layer. The double layer may be used only in any one of the 24, 26, 28 and the data lines 62, 64, 65, 66, and 68, so that the gate lines 22, 24, 26, 28 and the data lines 62, 64, Of course, any one of (65, 66, 68) can be formed using the double layer wiring formation method according to the present invention.

In addition, in the above-described embodiment, both the gate wirings 22, 24, 26, 28 and the data wirings 62, 64, 65, 66, 68 both contain aluminum or an aluminum alloy in the first metal layer and chromium in the second metal layer. Although included, only one of the gate wirings 22, 24, 26, 28 and the data wirings 62, 64, 65, 66, and 68 may be applied to the double layer structure as necessary.

As described above, according to the method of manufacturing a thin film transistor substrate using four masks according to the second embodiment of the present invention, the lower layer of the double layer wiring, which is etched by using different etching solutions, is more etched than the upper layer. It is possible to prevent the occurrence of defects by removing the undercut caused.

As described above, according to the present invention, in the method of manufacturing a thin film transistor substrate in which a double layer wiring is formed using different etching solutions, an undercut caused by etching the lower layer more than the upper layer can be removed to prevent the occurrence of defects. It becomes possible.

1 is a schematic layout view of a thin film transistor substrate formed by a manufacturing method according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along line II-II ′ of FIG. 1;

3 to 11 are cross-sectional views sequentially showing each step of manufacturing a thin film transistor substrate according to the first embodiment of the present invention;

12 is a schematic layout view of a thin film transistor substrate formed by the manufacturing method according to the second embodiment of the present invention;

13A and 13B are cross-sectional views of a thin film transistor substrate taken along lines XIIIa-XIIIa 'and XIIIb-XIIIb' of FIG. 12, respectively;

14A to 25B are cross-sectional views sequentially illustrating steps of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10: substrate material 22: gate line

24: gate pad 26: gate electrode

30 gate insulating film 40 semiconductor layer

50: middle layer 62: data line

65 source electrode 66 drain electrode

68: data pad 70: protective film

82 pixel electrode 900 photosensitive film

Claims (7)

In the method of manufacturing a thin film transistor substrate, Depositing a first metal layer etched by the first etching solution; Depositing a second metal layer etched by a second etching solution on the first metal layer; Forming a photoresist pattern on the second metal layer; First etching the second metal layer with the second etching solution; Etching the first metal layer with the first etching solution to form a first metal layer pattern; And secondly etching the first etched second metal layer with the second etch solution to form a second metal layer pattern. The method of claim 1, And the first metal layer comprises aluminum. The method of claim 2, The first etching solution is a method of manufacturing a thin film transistor substrate comprising phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ) and acetic acid (CH ₃ COOH). The method of claim 1, And the second metal layer comprises chromium. The method of claim 4, wherein The second etching solution comprises a nitric acid (HNO ₃ ) and the cyan ammonium nitrate ((NH ₄ ) ₂ Ce (NO ₃ ) ₆ ) The method of manufacturing a thin film transistor substrate. The method according to any one of claims 1 to 5, And the first and second metal layers are gate wiring layers. The method according to any one of claims 1 to 5, And the first and second metal layers are data wiring layers.