KR20050073373A - Methode of forming a contact hole in semiconductor device - Google Patents
Methode of forming a contact hole in semiconductor device Download PDFInfo
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- KR20050073373A KR20050073373A KR1020040001745A KR20040001745A KR20050073373A KR 20050073373 A KR20050073373 A KR 20050073373A KR 1020040001745 A KR1020040001745 A KR 1020040001745A KR 20040001745 A KR20040001745 A KR 20040001745A KR 20050073373 A KR20050073373 A KR 20050073373A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 38
- 239000011229 interlayer Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000012858 packaging process Methods 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000010354 integration Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 패키징 공정에서 패드 역할을 할 슈퍼-콘택홀과 일반적인 배선 연결 역할을 하는 노멀-콘택홀이 동시에 존재하는 소자를 제조함에 있어, 슈퍼-콘택홀을 먼저 형성하고, 웨이퍼를 상하좌우로 천천히 회전시키면서 슈퍼-콘택홀을 BARC로 채우고, BARC로 채워진 슈퍼-콘택홀을 포함한 전체 구조상에 노멀-콘택홀용 포토레지스트 패턴을 형성한 후, 식각 공정으로 노멀-콘택홀을 형성하고, 이후, 포토레지스트 제거 공정을 실시하므로, 슈퍼-콘택홀에서의 도포 불량으로 인한 평탄화 공정 등의 추가 공정 없이 두 종류의 콘택홀을 하나의 웨이퍼에 용이하게 형성할 수 있다. The present invention relates to a method for forming a contact hole in a semiconductor device, and in manufacturing a device in which a super-contact hole serving as a pad and a normal-contact hole serving as a general wiring connection exist simultaneously in a packaging process, Is formed first, and the wafer is slowly rotated up, down, left, and right, and the super-contact hole is filled with BARC, the photoresist pattern for the normal-contact hole is formed on the entire structure including the super-contact hole filled with BARC, and then the etching process is performed. Since a contact hole is formed and a photoresist removal process is performed thereafter, two types of contact holes can be easily formed on one wafer without an additional process such as a planarization process due to poor coating in the super-contact hole. .
Description
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 특히 패키징 공정에서 패드 역할을 할 슈퍼-콘택홀과 일반적인 배선 연결 역할을 하는 노멀-콘택홀을 용이하게 형성할 수 있는 반도체 소자의 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and in particular, to forming a contact hole in a semiconductor device that can easily form a super-contact hole that will serve as a pad and a normal-contact hole that serves as a general wiring connection in a packaging process. It is about a method.
세계적으로 가속화되는 국제 기술 경쟁으로 인하여 미세전자기기(micro-electronic system)의 소형화를 위한 막대한 연구 노력이 집중되고 있다. 칩 스케일 패키징(chip scale packaging), 플립 칩(flip chip), 다중칩 모듈(multichip module)은 현재 모빌 폰(mobile phone), 핸드-헬드 컴퓨터(hand-held computers), 칩 카드(chip card) 등의 많은 다양한 전자제품군에 통상적인 적용방법이 되고 있다. 미래 전자기기의 응용에는 매우 다양한 기능을 지닌 매우 복잡한 소자가 요구되고 있어서 이러한 상황을 만족시키기 위해서 칩 영역(chip area)이 급격히 증가되고 있다. 이러한 의미는 다기능 소자의 집적으로 인한 수율(yield) 문제, 소자 구현의 복잡성으로 인한 비용 증가 및 기술적인 한계에 직면해 있다. 또한, 미세전자기기의 성능과 다기능성, 신뢰성 등으로 인하여 서브 시스템(sub system)간의 배선(wiring)이 한계에 직면해 있다. 이러한 요인들은 미래 IC 세대의 크리티컬 퍼포먼스 버털넥(critical performance bottleneck)으로 인식이 되고 있다. 3차원 집적 기술(3D integration technology)은 임베디드 시스템 온 칩(embedded SoC) 기술을 대체할 가장 높은 잠재력을 지닌 기술로 기대되고 있다.Due to the accelerating global competition in technology, enormous research efforts for miniaturizing micro-electronic systems have been concentrated. Chip scale packaging, flip chip, multichip modules are currently used in mobile phones, hand-held computers, chip cards, etc. Has become a common application method in many different electronic product groups. Future applications of electronic devices require very complex devices with a wide variety of functions, and the chip area is rapidly increasing to satisfy this situation. This confronts yield problems due to the integration of multifunction devices, increased costs due to the complexity of device implementation, and technical limitations. In addition, due to the performance, versatility, reliability, and the like of the microelectronic device, wiring between sub systems faces limitations. These factors are recognized as the critical performance bottlenecks of future IC generations. 3D integration technology is expected to have the highest potential to replace embedded system on chip (SoC) technology.
패키징 공정에서 패드 역할을 할 슈퍼-콘택홀과 일반적인 배선 연결 역할을 하는 노멀-콘택홀이 하나의 웨이퍼 상에서 동시에 패터닝하고 있다. 슈퍼-콘택홀은 직경이 1 내지 2 ㎛이고 깊이가 6 내지 10 ㎛이다. 반면에 노멀-콘택홀은 직경이 0.1 내지 0.3 ㎛이고 깊이가 1 내지 2 ㎛이다. 슈퍼-콘택홀을 먼저 형성하는데, 이후에 노멀-콘택홀을 형성하기 위해서는 슈퍼-콘택홀을 포토레지스트와 같은 물질로 채워 평탄화하여야 한다. 그러나, 노멀-콘택홀을 형성하기 위하여 포토레지스트를 도포할 때 먼저 형성되어 있는 슈퍼-콘택홀에서 도포 불량이 발생하는 문제가 발생할 수 있다. 이러한 문제로 인하여 인터그레이션 스컴(integration scheme)을 변경하거나 포토레지스트를 매우 두껍게 도포한 후에 포토레지스트를 화학적 기계적 연마(CMP) 공정으로 연마하여 평탄화시켜야 하지만, 이러한 방법은 추가 공정의 발생이나 포토레지스트를 평탄화시킬 수 있는 장비 소요가 추가로 발생할 수 있는 문제가 있다. In the packaging process, a super-contact hole serving as a pad and a normal contact hole serving as a general wiring connection are patterned simultaneously on one wafer. Super-contact holes have a diameter of 1 to 2 μm and a depth of 6 to 10 μm. Normal-contact holes, on the other hand, have a diameter of 0.1-0.3 μm and a depth of 1-2 μm. The super-contact hole is first formed, and then, in order to form the normal-contact hole, the super-contact hole must be filled with a material such as photoresist and planarized. However, when the photoresist is applied to form the normal contact hole, a problem may occur in which a coating failure occurs in the super-contact hole formed first. This problem requires changing the integration integration scheme or applying a very thick photoresist and then flattening the photoresist with a chemical mechanical polishing (CMP) process. There is a problem that can additionally occur equipment requirements that can planarize.
따라서, 본 발명은 패키징 공정에서 패드 역할을 할 슈퍼-콘택홀과 일반적인 배선 연결 역할을 하는 노멀-콘택홀을 추가 공정 없이 용이하게 형성할 수 있는 반도체 소자의 콘택홀 형성 방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of easily forming a super-contact hole, which serves as a pad in a packaging process, and a normal-contact hole, which serves as a general wiring connection, without an additional process. have.
상기한 목적을 달성하기 위한 본 발명의 측면에 따른 반도체 소자의 콘택홀 형성 방법은 소자 형성층이 형성된 반도체 기판이 제공되는 단계; 소자 형성층 상에 층간 절연층을 형성하는 단계; 층간 절연층 상에 슈퍼-콘택홀용 포토레지스트 패턴을 형성하고, 이를 식각 마스크로 한 식각 공정으로 슈퍼-콘택홀을 형성하는 단계; 슈퍼-콘택홀용 포토레지스트 패턴을 제거하고, 슈퍼-콘택홀을 포함한 전체 구조 표면상에 배리어층을 형성하는 단계; 슈퍼-콘택홀이 충분히 매립되도록 BARC층을 형성하는 단계; 블랭켓 식각 공정으로 슈퍼-콘택홀 이외에 도포된 BARC층을 제거하는 단계; 전체 구조 상부에 노멀-콘택홀용 포토레지스트 패턴을 형성하고, 이를 식각 마스크로 한 식각 공정으로 노멀-콘택홀을 형성하는 단계; 및 노멀-콘택홀용 포토레지스트 패턴 및 BARC층을 제거하는 단계를 포함한다.According to an aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, the method including: providing a semiconductor substrate having an element formation layer; Forming an interlayer insulating layer on the device forming layer; Forming a photoresist pattern for a super-contact hole on the interlayer insulating layer, and forming the super-contact hole by an etching process using the same as an etching mask; Removing the photoresist pattern for the super-contact hole and forming a barrier layer on the entire structure surface including the super-contact hole; Forming a BARC layer such that the super-contact hole is sufficiently buried; Removing the applied BARC layer in addition to the super-contact hole by a blanket etching process; Forming a normal-contact hole photoresist pattern on the entire structure, and forming a normal-contact hole by an etching process using the same as an etching mask; And removing the photoresist pattern for the normal-contact hole and the BARC layer.
상기에서, 슈퍼-콘택홀은 직경이 1 내지 2 ㎛이고 깊이가 6 내지 10 ㎛정도이다.In the above, the super-contact hole has a diameter of 1 to 2 μm and a depth of about 6 to 10 μm.
배리어층은 산화물 계열 및 질화물 계열 중 적어도 어느 하나의 계열로 형성한다.The barrier layer is formed of at least one of oxide and nitride series.
BARC층은 상하좌우로 천천히 회전시키면서 BARC를 도포하면서 약 80 ℃ 전후로 가열한다.The BARC layer is heated to about 80 ° C. while applying BARC while slowly rotating up, down, left, and right.
노멀-콘택홀은 직경이 0.1 내지 0.3 ㎛이고 깊이가 1 내지 2 ㎛정도이다. The normal-contact hole has a diameter of 0.1 to 0.3 mu m and a depth of about 1 to 2 mu m.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허 청구 범위에 의하여 이해되어야 한다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only the present embodiment is provided to make the disclosure of the present invention complete, and to fully convey the scope of the invention to those skilled in the art, the scope of the present invention should be understood by the claims of the present application.
한편, 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다라고 기재되는 경우에 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다. 또한, 도면에서 각 층의 두께나 크기는 설명의 편의 및 명확성을 위하여 과장되어질 수도 있다. 도면상에서 동일 부호는 동일 요소를 지칭한다. On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In addition, the thickness or size of each layer in the drawings may be exaggerated for convenience and clarity of description. In the drawings, like numerals refer to like elements.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1E are cross-sectional views of devices for describing a method for forming contact holes in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(11)에 소자 분리막(12)을 형성하여 액티브 영역을 정의하고, 액티브 영역에 소오스/드레인 접합부 및 게이트로 구성되는 PMOS 트랜지스터(13P)와 NMOS 트랜지스터(13N) 등의 단위 소자들로 이루어진 소자 형성층을 형성한다. 소자 형성층이 형성된 전체 구조 상에 층간 절연층(14)을 형성한다. 층간 절연층(14) 상에 슈퍼-콘택홀용 포토레지스트 패턴(15)을 형성하고, 이를 식각 마스크로 한 식각 공정으로 층간 절연층(14), 소자 분리막(12) 및 반도체 기판(11)을 식각하여, 직경이 1 내지 2 ㎛이고 깊이가 6 내지 10 ㎛정도인 슈퍼-콘택홀(16)을 형성한다.Referring to FIG. 1A, an isolation region 12 is formed in a semiconductor substrate 11 to define an active region, and a PMOS transistor 13P, an NMOS transistor 13N, etc., each having a source / drain junction and a gate in the active region. An element formation layer consisting of unit elements is formed. The interlayer insulating layer 14 is formed on the entire structure in which the element formation layer is formed. A photoresist pattern 15 for a super-contact hole is formed on the interlayer insulating layer 14, and the interlayer insulating layer 14, the device isolation layer 12, and the semiconductor substrate 11 are etched by an etching process using the photoresist pattern 15 for a super-contact hole. As a result, a super-contact hole 16 having a diameter of 1 to 2 m and a depth of about 6 to 10 m is formed.
도 1b를 참조하면, 슈퍼-콘택홀용 포토레지스트 패턴(15)을 제거하고, 슈퍼-콘택홀(16)을 포함한 전체 구조 표면상에 배리어층(17)을 형성한다. 배리어층은 산화물 계열 및 질화물 계열 중 적어도 어느 하나의 계열로 형성한다.Referring to FIG. 1B, the photoresist pattern 15 for the super-contact hole is removed, and the barrier layer 17 is formed on the entire structure surface including the super-contact hole 16. The barrier layer is formed of at least one of oxide and nitride series.
도 1c를 참조하면, 슈퍼-콘택홀(16)이 충분히 매립되도록 BARC층(18)을 형성한다. BARC를 좌우회전식으로 도포할 경우 슈퍼-콘택홀(16)이 부분적으로 채워지지 않는 문제가 있다. 따라서 본 발명에서는 상하좌우로 천천히 회전시키면서 BARC를 도포하면서 약 80 ℃ 전후로 가열하여 유동성을 확보하여 슈퍼-콘택홀(16)을 양호하게 매립시키면서 표면 평탄화를 이루게 한다.Referring to FIG. 1C, a BARC layer 18 is formed to sufficiently fill the super-contact hole 16. When the BARC is applied to the left and right rotations, there is a problem that the super-contact hole 16 is not partially filled. Therefore, in the present invention, while slowly rotating up, down, left, and right, while applying BARC, it is heated to about 80 ° C. to ensure fluidity, thereby making the surface of the super-contact hole 16 well buried and achieving flatness.
도 1d를 참조하면, 블랭켓(blank) 식각 공정으로 슈퍼-콘택홀(16) 이외에 도포된 BARC층(18)을 제거한다. 슈퍼-콘택홀(16) 내에 BARC층(18)으로 채워진 전체 구조 상부에 노멀-콘택홀용 포토레지스트 패턴(19)을 형성하고, 이를 식각 마스크로 한 식각 공정으로 층간 절연층(14)을 식각하여, 직경이 0.1 내지 0.3 ㎛이고 깊이가 1 내지 2 ㎛정도인 노멀-콘택홀(20)을 형성한다.Referring to FIG. 1D, the BARC layer 18 applied in addition to the super-contact hole 16 is removed by a blanket etching process. The photoresist pattern 19 for the normal contact hole is formed on the entire structure filled with the BARC layer 18 in the super-contact hole 16, and the interlayer insulating layer 14 is etched by an etching process using the etching mask as an etching mask. In addition, a normal-contact hole 20 having a diameter of 0.1 to 0.3 m and a depth of about 1 to 2 m is formed.
도 1e를 참조하면, 노멀-콘택홀용 포토레지스트 패턴(19) 및 BARC층(18)을 포토레지스트 제거(PR strip) 공정으로 모두 제거하여 슈퍼-콘택홀(16) 및 노멀-콘택홀(20)이 완성된다. Referring to FIG. 1E, the photoresist pattern 19 and the BARC layer 18 for the normal contact hole are all removed by a photoresist strip process to remove the super-contact hole 16 and the normal contact hole 20. This is done.
상술한 바와 같이, 본 발명은 슈퍼-콘택홀과 노멀-콘택홀을 형성함에 있어 슈퍼-콘택홀을 상하좌우 회전 도포방식으로 BARC를 도포하여 단차를 최소화시키고 도포 불량 등의 문제가 없어 노멀-콘택홀을 양호하게 형성할 수 있으며, 또한 포토레지스트 CMP 장비의 추가 구입 없이 슈퍼-콘택홀과 노멀-콘택홀을 양호하게 형성할 수 있다.As described above, in the present invention, in forming the super-contact hole and the normal-contact hole, BARC is applied to the super-contact hole by up, down, left and right rotation application method to minimize the step difference, and there is no problem such as poor coating. The hole can be well formed, and the super-contact hole and the normal-contact hole can be well formed without additional purchase of photoresist CMP equipment.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 소자의 단면도이다. 1A to 1E are cross-sectional views of devices for describing a method for forming contact holes in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 반도체 기판 12: 소자 분리막11: semiconductor substrate 12: device isolation film
13P: PMOS 트랜지스터 13N: NMOS 트랜지스터13P: PMOS Transistor 13N: NMOS Transistor
14: 층간 절연층 15: 슈퍼-콘택홀용 포토레지스트 패턴14: interlayer insulating layer 15: photoresist pattern for super-contact hole
16: 슈퍼-콘택홀 17: 배리어층16: Super Contact Hole 17 Barrier Layer
18: BARC층 19: 노멀-콘택홀용 포토레지스트 패턴18: BARC layer 19: photoresist pattern for normal-contact hole
20: 노멀-콘택홀 20: normal contact hole
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