KR100864430B1 - methods of manufacturing a double side substrate having a dual semiconductor device and double side substrates fabricated thereby - Google Patents

Abstract

Provided are a double-sided substrate manufacturing method having dual semiconductor elements and a double-sided substrate manufactured thereby. This method provides a substrate having a first pattern on one surface. A through hole is formed through the back surface of the substrate to expose the first pattern. A connection wiring covering the through hole is formed. A second pattern is formed on the rear surface of the substrate having the conductive pattern so as to be in one-to-one alignment with the first pattern while being connected to the first pattern through the connection wiring. Also provided is a double-sided substrate produced by the method.

Description

Methods of manufacturing a double side substrate having a dual semiconductor device and double side substrates fabricated thereby

1 is a process cross-sectional view for explaining a method for manufacturing a double-sided substrate according to the prior art.

2 is a process flowchart for explaining a method of manufacturing the double-sided substrate having a dual semiconductor device according to embodiments of the present invention.

3A to 3F are cross-sectional views of processes for describing a method of manufacturing a double-sided substrate having dual semiconductor devices according to an embodiment of the present invention.

4A to 4D are cross-sectional views illustrating processes of manufacturing a double-sided board having dual semiconductor devices according to another exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to methods of manufacturing semiconductor devices and semiconductor devices manufactured thereby, and more particularly to methods of manufacturing double-sided substrates having dual semiconductor devices and double-sided substrates produced thereby.

As is generally known, in the past, single-sided substrates, which process only one side of the substrate to form a semiconductor device, have been used. However, in recent years, as the electronic devices become more functional, the density of substrates is increased, so that a double-sided board constituting a semiconductor element is required on both sides. In order to implement such a double-sided substrate technology, it is necessary to first form a semiconductor device on one surface of the substrate, and then to minimize the thickness of the substrate by polishing an auxiliary insulating film such as glass on the substrate on which the device is formed. In addition, the double-sided substrate requires a structure for transmitting an electrical signal to the semiconductor devices of the upper and lower sides because the semiconductor elements are configured on the upper and lower sides of the substrate. A method of using a through hole as a passage for transmitting electrical signals on both sides of the substrate has been proposed.

1 is a process cross-sectional view for explaining a method for manufacturing a double-sided substrate according to the prior art. Hereinafter, a conventional method of manufacturing a double-sided substrate using the through hole will be described with reference to FIG. 1.

Hereinafter, a method of manufacturing a conventional double-sided substrate having the above configuration will be described.

First, the first patterns 5 are formed on one surface of the substrate 1. The substrate 1 may be a silicon substrate in which a cell region I and a scribe brine region II are defined. The first patterns 5 may be any one of a pad, a resistor, a capacitor, an inductor, and a transistor of a semiconductor device. In this case, an interlayer insulating film 3 may be interposed between the substrate 1 and the first patterns 5.

Next, an adhesive layer 13 is formed on the substrate having the first patterns 5. An auxiliary insulating layer 15 such as glass is formed on the adhesive layer 13. The adhesive layer 13 is to improve the adhesive force between the auxiliary insulating layer 15 and the substrate 1. Subsequently, a release tape 16 is attached onto the auxiliary insulating film 15.

Then, the back surface of the substrate on which the release tape 16 is attached is polished using a separate polishing apparatus. Here, in the step of polishing the back surface of the substrate, it is preferable to process the back surface of the substrate as thinly as possible. When the back surface of the substrate is processed thinly, the size of the semiconductor chip can be reduced as a result.

Next, the first insulating layer 17 and the photoresist pattern (not shown) are sequentially formed on the back surface of the substrate on which the polishing process is completed. The photoresist pattern may be patterned to cover the cell regions I of the substrate and to expose the scribe brain regions II, which are boundary regions between the cell regions I. FIG. The first insulating layer 17 and the substrate 1 are etched using the photoresist pattern as a mask to form through holes 7 exposing at least a portion of the first patterns 5. That is, the through holes 7 are formed in the scribe brain regions II of the substrate. A second insulating layer 19 is formed on the side of the substrate exposed by the through holes 7.

Subsequently, conductive patterns 10 are formed on the back surface of the substrate having the second insulating layer 19. As a result, the conductive patterns 10 may be formed to surround the upper surface of the rear surface of the substrate having the second insulating layer 19 and the side surface of the substrate exposed by the through holes 7. In this case, the conductive patterns 10 may be formed by patterning a portion of the conductive pattern 10 formed on the rear surface of the substrate having the second insulating layer 19 by the second patterns 11 and the through holes 7. The patterned portion to surround the can be divided into connection wirings (9). The conductive patterns 10 have a form in which the second patterns 11 and the connection lines 9 are integrated. That is, the second patterns 11 and the connection wires 9 may be simultaneously patterned with a film of the same material. The second patterns 11 may be formed of a film of the same material as the first patterns 5.

Then, the substrate on which the conductive patterns 10 are formed is sawed and separated by each chip unit. When the sawing process is completed, the release tape 16, the auxiliary insulating layer 15, and the adhesive layer 13 may be selectively removed.

Now, a conventional double-sided substrate manufactured by the above methods will be described with reference to FIG. 1.

As shown in FIG. 1, a conventional double-sided substrate is provided with a substrate 1 having first patterns 3 on one surface thereof. The substrate 1 may be a substrate having a rear surface polished. In addition, an interlayer insulating film 3 may be interposed between the substrate 1 and the first patterns 5. An adhesive layer 13 and an insulating layer 15 may be further formed on the substrate 1 having the first patterns 5. In this case, the adhesive layer 13 and the insulating layer 15 may be omitted.

Through holes 7 are formed on the rear surface of the substrate 1 to expose at least a portion of the first patterns 5. The through holes 7 may be formed in the scribe brain region II of the substrate 1. Connection wires 9 are formed to surround side surfaces of the substrate exposed by the through holes 7 and are electrically connected to the first patterns 5. Second patterns 11 are formed on the rear surface of the substrate having the connection lines 9 and connected to the first patterns 5 through the connection lines 9. Here, the connection lines 9 and the second patterns 11 have an integrated form and constitute the conductive patterns 10.

The first insulating layer 17 may be interposed between the back surface of the substrate having the through holes 7 and the second patterns 11. A second insulating layer 19 may be further formed on the side surface of the substrate exposed by the through holes 7.

However, in the above-described conventional double-sided substrate technology, the conductive patterns may be applied only to the first patterns formed in the cell region necessarily adjacent to the scribe brain regions. That is, it is difficult to apply the conductive patterns to the first patterns in the cell regions. Accordingly, the conductive patterns, strictly speaking, serve as auxiliary wirings connected to the first patterns adjacent to the scribe brain regions on one surface of the substrate and correspond to the first patterns formed on the entire surface of the substrate. There is a problem in that the second patterns cannot be formed on the back surface of the substrate.

In addition, with current alignment equipment, it is difficult to align the second patterns on the back surface of the substrate with the first patterns on one surface of the substrate. As a result, the second patterns are separated from the first patterns by at least several tens of micrometers by a misalignment line.

Therefore, not only the first patterns adjacent to the scribe regions of the substrate but also the first patterns formed on the entire cell regions are formed on the back surface of the substrate by forming second patterns integrated with the first patterns on the substrate. There is a need for a method of manufacturing a double-sided substrate having dual semiconductor elements capable of implementing patterns on both sides of the substrate, and a double-sided substrate manufactured thereby.

In order to solve the above problems, an object of the present invention is to form a second pattern integrated with the first patterns through the through hole with respect to the first patterns processed on one surface of the substrate to have a one-to-one alignment on the back surface of the substrate It is to provide a method for producing a double-sided substrate having dual semiconductor elements and a double-sided substrate manufactured thereby.

In order to achieve the above object, the present invention provides a method for manufacturing a double-sided substrate having a dual semiconductor device. The method of the present invention provides a substrate having a first pattern on one surface. A through hole is formed through the back surface of the substrate to expose the first pattern. A connection wiring covering the through hole is formed. A second pattern is formed on the rear surface of the substrate having the connection wiring so as to be in one-to-one alignment with the first pattern through the connection wiring.

After providing the substrate having the first pattern, it is preferable to polish the back surface of the substrate until the final thickness of the substrate is 100 ~ 150㎛.

Forming the through hole includes sequentially forming a first insulating film and a predetermined photoresist pattern on the back surface of the substrate, etching the first insulating film and the substrate using the photoresist pattern as a mask, and removing the photoresist pattern. .

After forming the through hole, the method may further include forming a second insulating layer covering the side surface of the substrate exposed by the through hole.

Forming the connection wiring covering the through hole includes forming a conductive film on the back surface of the substrate having the through hole, and planarizing the conductive film to fill the through hole.

Forming a connection wiring covering the through hole may form a conductive film on the rear surface of the substrate having the through hole, covering the side surface of the substrate exposed by the first pattern and the through hole, and having a space spaced on the side surface. Etching of the film. The second pattern is formed while forming the connection wiring.

After forming the connection wiring, an insulating film is formed on the back surface of the substrate having the second pattern, and the insulating film is etched to form an insulating pattern for filling the spaced apart space.

The present invention provides a double-sided substrate produced by the above method. The double-sided substrate may include a substrate having a first pattern formed on one surface thereof, a through hole exposing the first pattern through the rear surface of the substrate, a connection wiring covering the through hole and electrically connected to the first pattern; And a second pattern formed on the rear surface of the substrate having wiring and connected to the first pattern through a connection wiring and one-to-one alignment with the first pattern.

It is preferable that the said board | substrate has a thickness of 100-150 micrometers.

The first pattern and the second pattern may be any one of a pad, a resistor, a capacitor, an inductor, and a transistor.

The display device may further include a first insulating film formed on an upper surface of the substrate exposed by the connection wiring, and a second insulating film interposed between the substrate and the connection wiring.

The connection wiring may be disposed so as to planarize the back surface of the substrate by filling the through hole.

Preferably, the connection wiring has an integrated structure with the second pattern.

Preferably, the connection wiring and the second pattern are made of the same film.

The connection wiring may be disposed to cover a side surface of the substrate exposed by the first pattern and the through hole, and to have a space spaced apart from the side surface.

The semiconductor device may further include an insulation pattern filling the spaced space.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

2 is a process flowchart for explaining a method of manufacturing a double-sided substrate having dual semiconductor devices according to embodiments of the present invention. 3A to 3F are cross-sectional views of processes for describing a method of manufacturing a double-sided substrate having a dual semiconductor device according to an exemplary embodiment of the present invention.

As shown in FIG. 2 and FIG. 3A, first patterns 55 are formed on a substrate 51 having a predetermined thickness. (Step S10 of FIG. 2) The first patterns 55 have a circuit design. And, through the mask manufacturing step may be produced in a desired shape on one surface of the substrate 51. The first patterns 55 may be any one of a pad, a resistor, a capacitor, an inductor, and a transistor. An interlayer insulating layer 53 may be interposed between the substrate 51 and the first patterns 55.

An adhesive layer 57 and an auxiliary insulating layer 59 that are sequentially stacked are formed on the substrate 51 to cover the first patterns 55. (Step S20 of FIG. 2) The adhesive layer 57 is This is to improve the adhesion between the auxiliary insulating film 59 to be formed later and the substrate 51. The adhesive layer 57 may be an adhesive tape. The adhesive tape may be an ultraviolet curable film. Alternatively, the adhesive layer 57 may be formed of an epoxy-based adhesive material. The auxiliary insulating layer 59 may be formed of a light transmissive material, and preferably, may be formed of a material having high light transmissivity.

The peeling tape 60 is affixed on the board | substrate 51 with the said auxiliary insulating film 59. (Step S30 of FIG. 2)

As shown in Figure 2 and Figure 3b, using a polishing device (not shown) to polish the back surface of the substrate having the peeling tape 60 (step S40 of FIG. 2). The thickness of the first patterns 55 formed on one surface of the substrate may be reduced so that only a minimum thickness of the first patterns 55 is not affected. Polishing the back surface of the substrate may be preferably performed until the final thickness of the polished substrate is 100 (20 μm) to 150 μm. As a result, the final board | substrate 51a processed thinly can be obtained. Here, the peeling tape 60 is the first patterns 55 on one surface of the substrate by the stress caused by the contamination or polishing by the silicon powder generated from the substrate while the back surface of the substrate is polished It serves to prevent this damage. On the other hand, the dotted lines not described in FIG. 3B correspond to the original substrate thickness before grinding.

As shown in FIGS. 2 and 3C, through holes 65 exposing the first patterns 55 are formed on the back surface of the substrate on which the polishing process is completed (step S50 of FIG. 2). The process of forming the holes 65 is as follows. First, the first insulating layer 61 and the photoresist layer pattern 63 are sequentially formed on the back surface of the substrate on which the polishing process is completed. The photoresist pattern 63 may be patterned to expose at least a portion of the first patterns 55. The first insulating layer 61 and the substrate 51a are etched using the photoresist pattern 63 as a mask.

As shown in FIGS. 2 and 3D, the photoresist pattern is removed. Connection wirings 69 filling the through holes 65 are formed. (Step S60 of FIG. 2) The connection lines 69 are formed by forming a conductive film on the back surface of the substrate having the through holes 65 and then etching the conductive film. The conductive layer etching process may use a chemical mechanical polishing or etch back process. Before forming the connection lines 65, a second insulating layer 67 may be formed on the side of the substrate exposed by the through holes 65.

As shown in FIG. 2 and FIG. 3E, second patterns 71 are formed on the back surface of the substrate having the connection wirings 69 (step S70 of FIG. 2). May be formed to be electrically connected to the first patterns 55 through the connection wirings 69 and align one-to-one with the first patterns 55. The second patterns 71 may be the same device as the first patterns 55, and may be any one of a pad, a resistor, a capacitor, an inductor, and a transistor. In addition, the second patterns 71 may be formed of a conductive film of the same material as the first patterns 55. Alternatively, the connection lines 69 and the second patterns 71 may be simultaneously patterned with a film of the same material. The connection lines 69 and the second patterns 71 form conductive patterns 72.

Meanwhile, in order to form the second patterns 71 to align one-to-one with the first patterns 55 on the back surface of the substrate based on the first patterns 55 formed on one surface of the substrate, a conventional general Since the alignment equipment cannot be precisely aligned, a special alignment equipment, the double side alignment equipment, can be used. The double side aligning apparatus reads coordinates on a computer by reading the first patterns 55 on one surface of a substrate, and then aligns the second patterns 71 one-to-one at the same position on the rear surface of the substrate. System.

As shown in FIGS. 2 and 3E, the substrate having the second patterns 71 is transferred to a transfer cassette (not shown) by a transfer robot, and saw the individual substrates 91 by sawing the transferred substrate. (Step S80 of FIG. 2) During the sawing process, the release tape 60 is attached to one surface of the substrate 51a. The sawing process can be carried out using commercially available abrasive wheels such as diamond wheels rotating at high speeds.

2 and 3F, the release tape is removed from one surface of the substrate. Subsequently, the auxiliary insulating film and the adhesive film are removed from one surface of the substrate. (Step S90 of FIG. 2) The insulating film and the adhesive film can be easily removed by a heat treatment process.

Although not shown in the drawing, a semiconductor package may be manufactured by packaging individual chips 91 that have passed through S90 of FIG. 2.

Now, a double-sided substrate having a dual semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 3F.

Referring again to FIG. 3F, a substrate 51a having first patterns 55 on one surface thereof is provided. The first patterns 55 may be any one of a pad, a resistor, a capacitor, an inductor, and a transistor. An interlayer insulating layer 53 may be interposed between the substrate 51a and the first patterns 55. The substrate 51a may be a silicon substrate having a back surface polished. Through holes 65 exposing the first patterns 55 are formed on the rear surface of the substrate 51a. Connection wirings 69 are formed to fill the through holes 65 to planarize the rear surface of the substrate. In this case, a first insulating layer 61 may be formed on the rear surface of the substrate exposed by the connection wirings 69. A second insulating layer 67 may be interposed between the substrate 51a and the connection wirings 69. On the back surface of the substrate 51a having the connection wirings 69, the first patterns 55 are electrically aligned with the first patterns 55 through the connection wirings 69. The second patterns 71 are arranged to form a structure.

4A through 4D are cross-sectional views illustrating processes of manufacturing a double-sided substrate having dual semiconductor devices according to another exemplary embodiment of the present invention. Hereinafter, a method of manufacturing a double-sided substrate having a dual semiconductor device according to another embodiment of the present invention will be described with reference to FIGS. 2 and 4A to 4D.

As shown in FIGS. 2 and 4A, through holes 65 are formed to expose at least a portion of the first patterns 55 through the polished substrate 51 a. (Step S50 of FIG. 2) In another embodiment of the present invention, the through hole forming process may be applied in the same manner as in the embodiment of the present invention (step S50 of FIG. 2 and FIGS.

2, 4B and 4C, exposed by the first patterns 55 and the through holes 65 on the back surface of the substrate 51a having the through holes 65. The conductive patterns 82 are formed to cover the side surfaces of the substrate and have spaces 81C spaced apart from each other (step S60 of FIG. 2 and step S70 of FIG. 2). The connection lines 81P1 covering the side surfaces of the substrate exposed by the patterns 55 and the through holes 65 and the portion patterned on the upper surface of the substrate may be divided into the second patterns 81P2. Therefore, the conductive patterns 82 have a form in which the second patterns 81P2 and the connection wirings 81P1 are integrated. The conductive patterns 82 are formed by forming a conductive film 81 on the back surface of the substrate 51a having the through holes 65 and etching the conductive film. Prior to forming the conductive patterns 82, a first insulating layer 61 may be formed on an upper surface of a substrate exposed by the through holes 65, and may be formed by the through holes 65. The second insulating layer 67 may be formed on the exposed side surface of the substrate.

Next, an insulating film is formed on the back surface of the substrate having the conductive patterns 82, and the insulating patterns are etched to form insulating patterns 83 filling the spaces 81C.

Subsequently, the substrate having the insulating patterns 83 is transferred to a transfer cassette (not shown) through a transfer robot, and the sawed substrate is sawed and separated into individual chips 91 (S80 of FIG. 2). Step) During the sawing process, the release tape 60 is attached to one surface of the substrate 51a.

2 and 4D, the release tape is removed from one side of the substrate. Subsequently, the auxiliary insulating film and the adhesive film are removed from one surface of the substrate. (Step S90 of FIG. 2) The insulating film and the adhesive film can be easily removed by a heat treatment process.

Next, a double-sided substrate having a dual semiconductor device according to another embodiment of the present invention will be described with reference to FIG. 4D.

Referring back to FIG. 4D, a substrate 51a having first patterns 55 on one surface thereof is provided. Through holes 65 exposing the first patterns 55 are formed on the rear surface of the substrate 51a. Connection wirings 81P1 are formed to cover the substrate side exposed by the through holes 65 and the first patterns 55. The second pattern which is connected to the first patterns 55 on the rear surface of the substrate having the connection wirings 81P1 and one-to-one aligned with the first patterns 55 through the connection wirings 81P1. The fields 81P2 are formed. In this case, the connection wirings 81P1 and the second patterns 81P2 constitute conductive patterns 82, and the second patterns 81P2 and the connection wirings 81P1 are arranged in an integrated form. do. That is, the second patterns 81P2 and the connection wirings 81P1 may be simultaneously patterned with a film of the same material. The first insulating layer 61 may be further formed on the rear surface of the substrate exposed by the connection wires 81P1. A second insulating layer 67 may be interposed between the substrate 51a and the connection wirings 81P1.

According to the present invention, first patterns and second patterns are formed on both surfaces of the substrate through the through holes, respectively. In this case, the second patterns are formed to be aligned one-to-one with respect to the first patterns. As a result, dual semiconductor devices may be manufactured by interconnecting first and second patterns that are correctly aligned on one surface and the back surface with one double-sided substrate.

In addition, in the present invention, the first patterns on one surface of the substrate do not necessarily exist only in the cell region near the scribe brain region. That is, since the first patterns may be located anywhere in the cell region, there is an advantage in high integration.

Claims (17)

Providing a substrate having a first pattern on one surface thereof; Forming an adhesive film pin (and) auxiliary insulating layer on the substrate provided with the first pattern; Attaching a release tape on the auxiliary insulating film; Forming a through hole penetrating a rear surface of the substrate to expose the first pattern; Forming a connection wiring covering the through hole; And forming a second pattern on the rear surface of the substrate having the connection wiring, the second pattern being aligned one-to-one with the first pattern while being connected to the first pattern through the connection wiring. The method of claim 1, wherein after attaching the peeling tape, A method for manufacturing a double-sided substrate comprising polishing the back surface of the substrate until the final thickness of the substrate is 100 (20 μm) to 150 μm. The method of claim 1, wherein forming the through hole Sequentially forming a first insulating film and a predetermined photoresist pattern on the back surface of the substrate, Etching the first insulating film and the substrate using the photosensitive film pattern as a mask, The method of manufacturing a double-sided substrate, characterized in that for removing the photosensitive film pattern. The method of claim 1, wherein after forming the through hole, Forming a second insulating film covering the side surface of the substrate exposed by the through hole. The method of claim 1, wherein forming the connection wiring A conductive film is formed on the back surface of the substrate having the through hole, And planarizing the conductive film to fill the through hole. The method of claim 1, wherein forming the connection wiring Forming a conductive film on a rear surface of the substrate having the through hole, covering the side surface of the substrate exposed by the first pattern and the through hole, and having a space spaced on the side surface; And etching the conductive film. The method of claim 6, wherein the second pattern is formed while the connection wiring is formed. The method of claim 6, wherein after forming the connection wiring, An insulating film is formed on the back surface of the substrate having the second pattern, And etching the insulating film to form an insulating pattern filling the spaced space. A substrate having a first pattern provided on one surface thereof; Through holes exposing the first pattern through the back surface of the substrate, A connection wiring covering the through hole and electrically connected to the first pattern; And a second pattern formed on a rear surface of the substrate having the connection wirings and connected to the first pattern through the connection wirings and aligning one-to-one with the first pattern. The double-sided substrate of claim 9, wherein the substrate has a thickness of 100 μm to 150 μm. The double-sided substrate of claim 9, wherein the first pattern and the second pattern are any one of a pad, a resistor, a capacitor, an inductor, and a transistor. The method of claim 9, A first insulating film formed on an upper surface of the substrate exposed by the connection wiring; And a second insulating layer interposed between the substrate and the connection wiring. The double-sided substrate of claim 9, wherein the connection line is disposed to planarize the rear surface of the substrate by filling the through hole. The double-sided substrate of claim 9, wherein the connection line has an integrated structure with the second pattern. The double-sided substrate of claim 14, wherein the connection wiring and the second pattern are formed of the same film. The double-sided substrate of claim 14, wherein the connection line covers a side surface of the substrate exposed by the first pattern and the through hole, and has a space spaced apart from the side surface. The double-sided substrate of claim 16, further comprising an insulation pattern filling the spaced spaces.

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