CN114649219A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
- Publication number
- CN114649219A CN114649219A CN202011502393.8A CN202011502393A CN114649219A CN 114649219 A CN114649219 A CN 114649219A CN 202011502393 A CN202011502393 A CN 202011502393A CN 114649219 A CN114649219 A CN 114649219A
- Authority
- CN
- China
- Prior art keywords
- chip
- bonding
- layer
- bonding interface
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000010410 layer Substances 0.000 claims abstract description 261
- 239000003292 glue Substances 0.000 claims abstract description 72
- 239000011241 protective layer Substances 0.000 claims abstract description 51
- 239000012790 adhesive layer Substances 0.000 claims abstract description 50
- 238000012360 testing method Methods 0.000 claims abstract description 23
- 239000011521 glass Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 11
- 238000005520 cutting process Methods 0.000 claims description 6
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 230000003749 cleanliness Effects 0.000 abstract description 10
- 239000000853 adhesive Substances 0.000 abstract description 7
- 230000001070 adhesive effect Effects 0.000 abstract description 7
- 230000002159 abnormal effect Effects 0.000 abstract description 6
- 238000004140 cleaning Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
Abstract
The invention provides a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the semiconductor device comprises the following steps: temporarily bonding the chip qualified in the test with a second slide glass through a second bonding adhesive layer, and contacting the protective layer on the first surface of the chip with the second bonding adhesive layer; flattening one side of the chip far away from the second slide glass to expose the bonding interface layer on the second surface of the chip; bonding the chip with the target wafer through the bonding interface layer on the second surface; removing the second slide glass, wherein a part of the second bonding adhesive layer is remained on the protective layer of the first surface; and flattening one side of the chip far away from the target wafer to remove the residual second bonding glue layer and the protective layer on the first surface and expose the bonding interface layer on the first surface to obtain a bonding structure. The technical scheme of the invention can prevent the mixed bonding interface from directly contacting with the bonding adhesive, ensure that the surface of the bonding interface layer has high cleanliness, and avoid causing the mixed bonding process between the chip and the target wafer to be abnormal.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly, to a method for manufacturing a semiconductor device.
Background
Chip-wafer stacking is favored by the global semiconductor macro because it is not limited by chip size matching and its KGD (knock-off Good die) scheme can greatly improve yield. At present, the mass production scheme of the chip-wafer stacking technology mainly uses a Micro Bump (Micro Bump) packaging process, the minimum pitch size (connection unit size) of the Micro Bump is about 40 μm, and Underfill (Underfill) between the Micro bumps is not favorable for heat dissipation, so the development direction is developing towards the smaller pitch size of the Micro Bump packaging process.
The Bumpless process is mainly characterized in that the metal-metal direct bonding on a bonding interface is realized by utilizing a hybrid bonding technology, and the pitch size can be smaller than 10 mu m, so that higher I/O (input/output) connection density is realized, no under-filling material is used, and the heat dissipation performance is better. The temporary bonding can be utilized in the Bumpless process, specifically, the chip to be bonded and the slide glass are temporarily bonded by using bonding glue, then are subjected to bonding disconnection, the bonding glue is removed by cleaning with a glue removing solution, and then the chip to be bonded and the target wafer are subjected to mixed bonding. However, the mixed bonding has high requirement on the cleanliness of the interface, and if the cleanliness does not meet the requirement, gaps or impurities and the like exist at the interface after the mixed bonding, so that the bonding is not firm; and the cleanliness of the interface can hardly meet the requirement by adopting the photoresist removing liquid for cleaning.
Therefore, how to improve the existing chip-wafer bonding method to avoid the adverse effect of the bonding glue on the bonding interface is a problem that needs to be solved at present.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which can prevent a mixed bonding interface from directly contacting bonding glue, ensure that the surface of the bonding interface layer has high cleanliness and avoid the abnormal mixed bonding process between a chip and a target wafer.
To achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising:
step S1, forming a plurality of chips which are qualified in testing, wherein a bonding interface layer and a protective layer are sequentially formed on the two opposite first surfaces and the second surfaces of each chip;
step S2, providing a second slide, forming a second bonding adhesive layer, temporarily bonding the chip with the second slide through the second bonding adhesive layer, wherein the protective layer on the first surface of the chip is in contact with the second bonding adhesive layer, and a gap is formed between the adjacent chips;
step S3, covering a dielectric layer on the chip, the dielectric layer filling the gap;
step S4, flattening one side of the chip far away from the second slide glass until the bonding interface layer on the second side of the chip is exposed;
step S5, bonding the chip with a target wafer through the bonding interface layer on the second surface;
step S6, performing a de-bonding process to remove the second carrier, wherein a portion of the second bonding glue layer remains on the protective layer of the first surface; and the number of the first and second groups,
step S7, planarizing a side of the chip away from the target wafer to remove the remaining second bonding glue layer and the protective layer on the first surface, and exposing the bonding interface layer on the first surface to obtain a bonding structure.
Optionally, the step S1 includes:
providing a device wafer;
sequentially forming a first bonding interface layer and a first protective layer on the front surface of the device wafer;
providing a first carrier, forming a first bonding adhesive layer, temporarily bonding the device wafer with the first carrier through the first bonding adhesive layer, and contacting the first protective layer with the first bonding adhesive layer;
sequentially forming a second bonding interface layer and a second protective layer on the back surface of the device wafer, wherein the front surface and the back surface are opposite;
performing a de-bonding process to remove the first carrier; and the number of the first and second groups,
and performing a cutting process on the device wafer to obtain a chip qualified in test, wherein a part of the first bonding glue layer is remained on the first protective layer of the chip.
Optionally, after the device wafer is temporarily bonded to the first carrier wafer through the first bonding glue layer and before the second bonding interface layer is formed on the back side of the device wafer, the method for manufacturing a semiconductor device further includes:
thinning the back of the device wafer; and the number of the first and second groups,
and forming a conductive through hole structure on the back surface of the device wafer.
Optionally, after forming the second bonding interface layer on the back side of the device wafer and before forming the second protection layer on the back side of the device wafer, the method for manufacturing a semiconductor device further includes:
and testing the chips on the device wafer, and marking the chips which are qualified in the test.
Optionally, the first surface of the chip is the front surface of the device wafer, and the second surface of the chip is the back surface of the device wafer; in the step S4, planarizing a side of the chip away from the second carrier to remove the second protective layer;
or the first surface of the chip is the back surface of the device wafer, and the second surface of the chip is the front surface of the device wafer; in the step S4, a side of the chip away from the second carrier is planarized to remove the remaining first bonding glue layer and the first protection layer.
Optionally, the step S3 includes:
forming a third bonding glue layer in the gap, wherein the top surface of the third bonding glue layer is lower than the top surface of the chip; and the number of the first and second groups,
and covering an oxide layer on the chip and the third bonding adhesive layer, wherein the third bonding adhesive layer and the oxide layer form the dielectric layer.
Optionally, after the step S4 and before the step S5 and/or after the step S7, a plasma process is performed to activate the bonding interface layer on the second side of the chip and the bonding interface layer on the first side of the chip.
Optionally, the second slide glass is a light-transmitting substrate; the step S6 includes: and irradiating the second slide glass and the second bonding adhesive layer by adopting laser so as to decompose the second bonding adhesive layer and further remove the second slide glass and part of the second bonding adhesive layer.
Optionally, the method for manufacturing a semiconductor device further includes:
and circularly and repeatedly executing the steps S1 to S7, and taking the bonded structure obtained by executing the steps S1 to S7 at the previous time as a target wafer for executing the steps S1 to S7 at the next time.
The present invention also provides a semiconductor device comprising:
a first chip;
the second chip is provided with a first face and a second face which are opposite, at least the first face is provided with a bonding interface layer, and the second chip is bonded with the first chip through the bonding interface layer on the first face;
the oxide layer covers the side wall of a part of the height of the second chip; and the number of the first and second groups,
and the bonding glue layer covers the side wall of the other part of the height of the second chip.
Optionally, at least two layers of the second chip are bonded on the first chip, and the bonding interface layer on the second side of the second chip close to the first chip is bonded with the bonding interface layer on the first side or the second side of the second chip far from the first chip.
Optionally, the first surface is a front surface of the second chip, and the second surface is a back surface of the chip; or, the first surface is a back surface of the second chip, and the second surface is a front surface of the chip.
Optionally, the oxide layer covers a sidewall of the second chip close to a partial height of the first chip; the bonding glue layer covers the side wall of the second chip far away from the other part of the height of the first chip.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the manufacturing method of the semiconductor device, the protective layer is formed on the bonding interface layer on the chip which is qualified in the test, so that the bonding interface layer can be prevented from contacting with the bonding adhesive layer when the chip is temporarily bonded with the slide glass; and before the chip and the target wafer are mixed and bonded, a flattening process is adopted to remove the residual bonding glue layer and the residual protective layer on the protective layer, so that the mixed bonding interface can be prevented from being directly contacted with the bonding glue, the surface of the bonding interface layer is ensured to have high cleanliness, and the mixed bonding process between the chip and the target wafer is prevented from being abnormal.
2. According to the semiconductor device, the bonding interface layer is formed on at least the first surface of the second chip, the second chip is bonded with the first chip through the bonding interface layer on the first surface, the bonding interface layer has high cleanliness, mixed bonding between the second chip and the first chip is prevented from being abnormal, and reliability of the semiconductor device is prevented from being reduced.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
FIGS. 2 a-2 r are device diagrams of an embodiment of a method of fabricating the semiconductor device shown in FIG. 1;
fig. 3a to 3i are device diagrams of another embodiment in the method of manufacturing the semiconductor device shown in fig. 1.
Fig. 4a to 4b are schematic structural diagrams of a semiconductor device according to an embodiment of the present invention;
fig. 5a to 5b are schematic structural views of a semiconductor device according to another embodiment of the present invention.
Wherein the reference numerals of figures 1 to 5b are as follows:
11-a device wafer; 111-a first bonding interface layer; 112-a first protective layer; 113-a second bonding interface layer; 114-a second protective layer; 12-a first slide; 121-a first bonding glue layer; 13-blue film; 21-a chip; 22-a second slide; 221-a second bonding glue layer; 23-gap; 241-a third bonding glue layer; 242-an oxide layer; 25-a target wafer; 30-a first chip; 311-a first bonding interface layer; 312 — a second bonding interface layer; 31-a second chip; 32-an oxide layer; 33-bond paste layer.
Detailed Description
To make the objects, advantages and features of the present invention more apparent, the semiconductor device and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, and referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, the method for manufacturing a semiconductor device including:
step S1, forming a plurality of chips which are qualified in testing, wherein a bonding interface layer and a protective layer are sequentially formed on the first surface and the second surface of each chip, which are opposite to each other;
step S2, providing a second slide, forming a second bonding adhesive layer, temporarily bonding the chip with the second slide through the second bonding adhesive layer, wherein the protective layer on the first surface of the chip is in contact with the second bonding adhesive layer, and a gap is formed between the adjacent chips;
step S3, covering a dielectric layer on the chip, wherein the dielectric layer fills the gap;
step S4, flattening one side of the chip far away from the second slide glass until the bonding interface layer on the second surface of the chip is exposed;
step S5, bonding the chip with a target wafer through the bonding interface layer on the second surface;
step S6, executing a bonding removal process to remove the second carrier, wherein a part of the second bonding glue layer is left on the protective layer of the first surface;
step S7, planarizing a side of the chip away from the target wafer to remove the remaining second bonding glue layer and the protective layer on the first surface, and exposing the bonding interface layer on the first surface to obtain a bonding structure.
The method for manufacturing the semiconductor device according to the present embodiment is described in detail with reference to fig. 2a to 3i, where fig. 2i is a schematic top view of the semiconductor device, and fig. 2a to 2h, fig. 2j to 2r, and fig. 3a to 3i are schematic longitudinal cross-sectional views of the semiconductor device. Fig. 2a to 2r illustrate an embodiment of the present invention, and fig. 2a to 2i and fig. 3a to 3i illustrate another embodiment of the present invention.
According to step S1, a plurality of chips passing the test are formed, and a bonding interface layer and a protective layer are sequentially formed on two opposite first and second surfaces of each chip.
The step S1 includes: first, as shown in fig. 2a, a device wafer 11 is provided, where the device wafer 11 includes a substrate (not shown) and a device structure (not shown) formed on the substrate, and the device structure includes a gate structure, a metal interconnection structure, and the like; then, as shown in fig. 2a and fig. 2b, a first bonding interface layer 111 and a first protection layer 112 are sequentially formed on the front side of the device wafer 11; then, as shown in fig. 2c, providing a first carrier 12, forming a first bonding glue layer 121, temporarily bonding the device wafer 11 to the first carrier 12 through the first bonding glue layer 121, and contacting the first protective layer 112 with the first bonding glue layer 121; then, as shown in fig. 2d, thinning the back surface of the device wafer 11, that is, thinning the substrate on the back surface of the device wafer 11, where the front surface and the back surface are opposite; then, forming a conductive via structure (not shown) on the back side of the device wafer 11; then, as shown in fig. 2e, a second bonding interface layer 113 is formed on the back side of the device wafer 11; then, testing the chips on the device wafer 11, and marking the chips which are qualified in the test, so as to select the chips which are qualified in the test after subsequent cutting, wherein the chips are tested after the second bonding interface layer 113 is formed, instead of being tested on the front side, so that the failure of the back process can be prevented, and the damaged chips are not identified; then, as shown in fig. 2f, a second passivation layer 114 is formed on the second bonding interface layer 113 on the back side of the device wafer 11; then, as shown in fig. 2g, a support film, such as a blue film 13 or a UV film (hereinafter, a blue film is taken as an example), is attached on a side of the second protection layer 114 away from the device wafer 11; then, as shown in fig. 2h, a debonding process is performed to remove the first carrier 12, and the first bonding glue layer 121 remains on the first protective layer 112, so that the surface of the chip is protected from being damaged in the subsequent cutting process, and particle impurities caused by cutting do not fall on the surface of the chip; then, performing a cutting process on the device wafer 11, and cleaning and removing the first bonding glue layer 121 by using a glue removing solution, but because the glue removing solution cannot completely remove the first bonding glue layer 121, a part of the first bonding glue layer 121 remains on the first protection layer 112; then, the blue film 13 is subjected to film expansion, so that the distance between adjacent chips is increased, and the chips 21 which are qualified in the test can be conveniently selected for the subsequent process.
The first bonding interface layer 111 and the second bonding interface layer 113 each include an insulating dielectric layer (not shown) and a metal layer (not shown) in the insulating dielectric layer. The first protective layer 112 and the second protective layer 114 may be made of silicon oxide, silicon oxynitride, silicon nitride, or the like.
A device structure is formed on one side of the front surface of the device wafer 11, and a substrate is arranged on one side of the back surface of the device wafer 11. The first surface of the chip 21 is the front surface of the device wafer 11, and the second surface of the chip 21 is the back surface of the device wafer 11, so that the first bonding interface layer 111 and the first protection layer 112 are formed on the first surface of the chip 21, and the second bonding interface layer 113 and the second protection layer 114 are formed on the second surface of the chip 21; or, the first surface of the chip 21 is the back surface of the device wafer 11, and the second surface of the chip 21 is the front surface of the device wafer 11, then the second bonding interface layer 113 and the second protection layer 114 are formed on the first surface of the chip 21, and the first bonding interface layer 111 and the first protection layer 112 are formed on the second surface of the chip 21.
According to step S2, referring to fig. 2i, 2j and 3a, a second carrier 22 is provided, a second bonding glue layer 221 is formed, the chip 21 is temporarily bonded to the second carrier 22 through the second bonding glue layer 221, the protective layer on the first side of the chip 21 is in contact with the second bonding glue layer 221, and a gap 23 is formed between adjacent chips 21. Fig. 2i is a schematic top view of fig. 2j and fig. 3a, and the process steps before fig. 3a refer to fig. 2a to fig. 2 h.
As shown in fig. 2j, the first surface of the chip 21 is the back surface of the device wafer 11, and the second protection layer 114 is in contact with the second bonding glue layer 221; as shown in fig. 3a, the first surface of the chip 21 is the front surface of the device wafer 11, and the first protection layer 112 and the residual first bonding adhesive layer 121 are in contact with the second bonding adhesive layer 221.
The second carrier sheet 22 may be a light-transmissive substrate to facilitate a subsequent de-bonding process by laser. The material of the light-transmitting substrate can be glass, ceramic, plastic and the like.
According to step S3, a dielectric layer is covered on the chip 21, and the dielectric layer fills the gap 23.
Referring to fig. 2k and 3b, the step S3 includes: firstly, forming a third bonding adhesive layer 241 in the gap 23, wherein the top surface of the third bonding adhesive layer 241 is lower than the top surface of the chip 21, and the third bonding adhesive layer can be formed by steps of coating bonding adhesive, curing the bonding adhesive and removing excess bonding adhesive, when the depth of the gap 23 is deep, the speed of filling the gap 23 by coating the bonding adhesive is fast, and compared with the step of depositing silicon oxide and other materials to fill the gap 23, the cost can be saved; then, an oxide layer 242 is covered on the chip 21 and the third bonding adhesive layer 241, the oxide layer 242 fills the gap 23, in fig. 2k, the oxide layer 242 buries the remaining first bonding adhesive layer 121, in fig. 3b, the oxide layer 242 buries the second protection layer 114, and the third bonding adhesive layer 241 and the oxide layer 242 form the dielectric layer.
Alternatively, the oxide layer 242 may be replaced by other materials, such as silicon nitride, silicon oxynitride, etc.
Before the third bonding adhesive layer 241 is formed in the gap 23, another oxide layer (not shown) may be formed on the sidewall and the bottom wall of the gap 23, since the bonding adhesive flows when the third bonding adhesive layer 241 is formed by coating, in order to prevent the flowing bonding adhesive from punching or shifting the chip 21, the another oxide layer may fix the chip 21, and the another oxide layer may also serve as a buffer layer between the second bonding adhesive layer 221 and the third bonding adhesive layer 241.
The side of the chip 21 remote from the second carrier sheet 22 is planarized until the bonding interface layer on the second side of the chip 21 is exposed, as per step S4. And carrying out planarization treatment by adopting a chemical mechanical polishing process.
As shown in fig. 2l, the side of the chip 21 away from the second carrier 22 is the side where the second side (i.e. the front side of the device wafer 11) of the chip 21 is planarized, so as to remove the remaining first bonding glue layer 121 and the first protective layer 112 and expose the first bonding interface layer 111; alternatively, as shown in fig. 3c, the side of the chip 21 away from the second carrier 22 is the side where the second side of the chip 21 (i.e. the back side of the device wafer 11) is planarized, so as to remove the second protection layer 114 and expose the second bonding interface layer 113.
After the step S4 and before the step S5, a plasma (plasma) process is performed to activate the bonding interface layers on the second side of the chip 21, i.e., the first bonding interface layer 111 shown in fig. 2l and the second bonding interface layer 113 shown in fig. 3c, so that the subsequent bonding with the target wafer is stronger.
According to step S5, the chip 21 is bonded to a target wafer 25 through the bonding interface layer on the second side.
The chip 21 and the target wafer 25 may be pre-bonded and then annealed, so that the bonding force between the chip 21 and the target wafer 25 is enhanced.
As shown in fig. 2m, the bonding interface layer on the second side is the first bonding interface layer 111, and the chip 21 is bonded to the target wafer 25 through the first bonding interface layer 111; as shown in fig. 3d, the bonding interface layer on the second side is the second bonding interface layer 113, and the chip 21 is bonded to the target wafer 25 through the second bonding interface layer 113.
The target wafer 25 may include a device structure therein, and a bonding interface layer may also be formed on a bonding surface of the target wafer 25 and the chip 21.
According to step S6, a debonding process is performed to remove the second carrier 22, and a portion of the second bonding glue layer 221 remains on the protective layer of the first surface.
Because the second carrier 22 is a light-transmitting substrate, the second carrier 22 and the second bonding adhesive layer 221 can be irradiated by laser, so that the second bonding adhesive layer 221 is decomposed, the second carrier 22 and the second bonding adhesive layer 221 are separated, and the second carrier 22 and a part of the second bonding adhesive layer 221 are removed.
After the debonding process is performed, the remaining side of the second bonding glue layer 221 may be further cleaned, but both the debonding process and the further cleaning may not completely remove the second bonding glue layer 221.
As shown in fig. 2n, the second protective layer 114 and the third bonding glue layer 241 in the gap 23 have the second bonding glue layer 221 remained thereon; as shown in fig. 3e, the first bonding glue layer 121 and the second bonding glue layer 221 still remain on the first protection layer 112, and the second bonding glue layer 221 remains on the third bonding glue layer 241 in the gap 23.
In addition, when the second carrier sheet 22 is irradiated with laser, the laser also penetrates through the second carrier sheet 22 and is irradiated onto the third bonding glue layer 241 in the gap 23, and if the third bonding glue layer 241 is also partially decomposed and removed, the bonding glue can be continuously filled in the gap 23 to fill the gap 23.
According to step S7, the side of the chip 21 away from the target wafer 25 is planarized to remove the remaining second bonding glue layer 221 and the protective layer on the first surface, and expose the bonding interface layer on the first surface, so as to obtain a bonded structure. And carrying out planarization treatment by adopting a chemical mechanical polishing process.
As shown in fig. 2o, the side of the chip 21 away from the target wafer 25 is the side where the first surface of the chip 21 (i.e. the back surface of the device wafer 11) is planarized, so as to remove the remaining second bonding glue layer 221 and the second protection layer 114 and expose the second bonding interface layer 113; as shown in fig. 3f, the side of the chip 21 away from the target wafer 25 is the side where the first surface of the chip 21 (i.e., the front surface of the device wafer 11) is planarized, so as to remove the remaining second bonding glue layer 221, the remaining first bonding glue layer 121, and the first protection layer 112, and expose the first bonding interface layer 111.
After the step S7, a plasma (plasma) process is performed to activate the bonding interface layer on the first side of the chip 21, i.e. the second bonding interface layer 113 shown in fig. 2o and the first bonding interface layer 111 shown in fig. 3f, so that the bonding with other chips is more secure.
Then, after the above steps S1 to S7, a layer of the plurality of qualified test chips 21 is bonded on the target wafer 25 in the bonding structure.
The manufacturing method of the semiconductor device further includes:
and repeating the steps S1 to S7 in a loop manner, and using the bonding structure obtained by performing the steps S1 to S7 for the last time as the target wafer 25 for performing the steps S1 to S7 for the next time, so as to bond chips to each other, so that at least two layers of the chips 21 passing the test are bonded on the target wafer 25 in the new bonding structure.
Taking the bonding of two layers of the plurality of qualified test chips 21 on the target wafer 25 as an example, referring to fig. 2p to 2i and fig. 3g to 3i, the steps include: firstly, the steps S1 to S7 are executed to obtain the bonded structure, in which a layer of the plurality of chips 21 that pass the test is bonded on the target wafer 25, and the bonded structure is used as a new target wafer when the step S5 is executed next time, wherein the face to be bonded in the bonded structure may be the second bonding interface layer 113 (as shown in fig. 2 o) or the first bonding interface layer 111 (as shown in fig. 3 f); then, as shown in fig. 2p and fig. 3g, the steps S1 to S5 are continued to bond the bonding interface layer on the newly fabricated chip 21 on the second carrier 22 and the bonding interface layer on the new target wafer (i.e. the bonding structure), wherein the bonding interface layer on the chip 21 on the second carrier sheet 22 to be newly manufactured can be the first bonding interface layer 111 or the second bonding interface layer 113, then, it may be that the second bonding interface layer 113 or the first bonding interface layer 111 in the bonding structure is bonded with the first bonding interface layer 111 on the chip 21 on the second carrier 22 which is newly manufactured, or, the second bonding interface layer 113 or the first bonding interface layer 111 in the bonding structure may be bonded to the second bonding interface layer 113 on the chip 21 on the second carrier 22 that is newly manufactured; next, as shown in fig. 2q and fig. 3h, continuing to perform the step S6, performing a de-bonding process to remove the second carrier 22, wherein a portion of the second bonding adhesive layer 221 remains on the protective layer of the first surface; next, as shown in fig. 2r and fig. 3i, the step S7 is continuously performed to planarize a side of the chip 21 away from the bonding structure, so as to remove the remaining second bonding glue layer 221 and the protective layer on the first surface, and expose the bonding interface layer on the first surface, so as to obtain a new bonding structure, where two layers of the plurality of chips 21 that pass the test are bonded on the target wafer 25.
In addition, for the chips 21 that pass the test, only the protective layer may be formed on the first surface without forming the bonding interface layer, and the bonding interface layer and the protective layer may be formed in this order on the second surface, and the method for manufacturing a semiconductor device (not shown) may include: firstly, providing a second carrier, forming a second bonding adhesive layer, and temporarily bonding the chip with the second carrier through the second bonding adhesive layer, wherein a protective layer on the first surface of the chip is in contact with the second bonding adhesive layer, and a gap is formed between the adjacent chips; then, covering a dielectric layer on the chip, wherein the dielectric layer fills the gap; then, flattening one side of the chip far away from the second slide glass until the bonding interface layer on the second side of the chip is exposed; then, bonding the chip with a target wafer through a bonding interface layer on the second surface; then, executing a bonding removing process to remove the second carrier, wherein a part of the second bonding glue layer is remained on the protective layer of the first surface; and then, flattening one side of the chip far away from the target wafer to remove the residual second bonding glue layer, and optionally removing the protective layer on the first surface and exposing the first surface of the chip.
In addition, after the above steps, the bonding structure may be further cut to obtain a chip stack structure having at least one layer of the chips 21.
In conclusion, the protective layer is formed on the bonding interface layer on the chip which is qualified in the test, so that the bonding interface layer can be prevented from contacting the bonding adhesive layer when the chip is temporarily bonded with the slide glass; and before the chip and the target wafer are mixed and bonded, a planarization process is adopted to remove the residual bonding glue layer and the residual protective layer on the protective layer, so that the mixed bonding interface can be prevented from being directly contacted with the bonding glue, the surface of the bonding interface layer is ensured to have high cleanliness, and the mixed bonding process between the chip and the target wafer is prevented from being abnormal (for example, gaps or impurities exist at the interface after mixed bonding).
An embodiment of the present invention provides a semiconductor device, referring to fig. 4a to 4b and fig. 5a to 5b, the semiconductor device includes a first chip 30, a second chip 31, an oxide layer 32, and a bonding glue layer 33, the second chip 31 is bonded on the first chip 30, and at least one layer of the second chip 31 may be bonded on the first chip 30. Fig. 4a to 4b illustrate the second chip 31 bonded to the first chip 30 by one layer, and fig. 5a to 5b illustrate the second chip 31 bonded to the first chip 30 by two layers.
The semiconductor device provided in this embodiment will be described in detail with reference to fig. 4a to 4b and fig. 5a to 5 b.
The first chip 30 and the second chip 31 may have a substrate (not shown) and a device structure (not shown) therein.
The second chip 31 has two opposite first and second faces, at least the first face is formed with a bonding interface layer, and the second chip 31 and the first chip 30 are bonded through the bonding interface layer on the first face. The bonding interface layer of the second chip 31 has high cleanliness, and meets the requirements of the bonding process between chips of adjacent layers.
The front surface of the second chip 31 may be formed with a first bonding interface layer 311, and/or the back surface of the second chip 31 may be formed with a second bonding interface layer 312, the front surface and the back surface of the second chip 31 are opposite surfaces, a device structure is formed on one side of the front surface of the second chip 31, and a substrate is formed on one side of the back surface of the second chip 31. The first bonding interface layer 311 and the second bonding interface layer 312 each include an insulating dielectric layer (not shown) and a metal layer (not shown) in the insulating dielectric layer.
The first surface is a front surface of the second chip 31, and the second surface is a back surface of the second chip 31, in this case, the second chip 31 and the first chip 30 are bonded through the first bonding interface layer 311 (as shown in fig. 4 a); alternatively, the first surface is a back surface of the second chip 31, and the second surface is a front surface of the chip 31, in this case, the second chip 31 and the first chip 30 are bonded by the second bonding interface layer 312 (as shown in fig. 5 a).
The oxide layer 32 covers the sidewall of a part of the height of the second chip 31, as shown in fig. 4a and 5a, the oxide layer 32 covers the sidewall of a part of the height of the second chip 31 close to the first chip 30; the bonding glue layer 33 covers the sidewall of the other part of the height of the second chip 31, as shown in fig. 4a and 5a, the bonding glue layer 33 covers the sidewall of the other part of the height of the second chip 31 away from the first chip 30.
In addition, another oxide layer (not shown) may be sandwiched between the sidewalls of the second chip 31 and the oxide layer 32 and the bonding glue layer 33.
If at least two layers of the second chip 31 are bonded on the first chip 30, the bonding interface layer on the second side of the second chip 31 close to the first chip 30 is bonded with the bonding interface layer on the first side or the second side of the second chip 31 far from the first chip 30.
Wherein the second side is the back side of the second chip 31, then the second bonding interface layer 312 on the second side of the second chip 31 close to the first chip 30 is bonded to the first bonding interface layer 311 on the first side of the second chip 31 far from the first chip 30 (as shown in fig. 4b, i.e. the back side of the second chip 31 close to the first chip 30 is bonded to the front side of the second chip 31 far from the first chip 30), or alternatively, the second bonding interface layer 312 on the second side of the second chip 31 far from the first chip 30 is bonded (i.e. the back side of the second chip 31 close to the first chip 30 is bonded to the back side of the second chip 31 far from the first chip 30); or, the second side is the front side of the second chip 31, the first bonding interface layer 311 on the second side of the second chip 31 close to the first chip 30 is bonded to the second bonding interface layer 312 on the second side of the second chip 31 far from the first chip 30 (as shown in fig. 5b, that is, the front side of the second chip 31 close to the first chip 30 is bonded to the back side of the second chip 31 far from the first chip 30), or the first bonding interface layer 311 on the first side of the second chip 31 far from the first chip 30 is bonded (that is, the front side of the second chip 31 close to the first chip 30 is bonded to the front side of the second chip 31 far from the first chip 30).
In addition, the semiconductor device described above can also be manufactured by the manufacturing method of the semiconductor device of the present invention. The structures in fig. 4a to 4b and fig. 5a to 5b correspond to the partial structures in fig. 2a to 3i, specifically, the first chip 30 is obtained after the target wafer 25 is cut, the second chip 31 is the chip 21, the oxide layer 32 is the oxide layer 242, the bonding glue layer 33 is the third bonding glue layer 241, the first bonding interface layer 311 is the first bonding interface layer 111, and the second bonding interface layer 312 is the second bonding interface layer 113.
Due to the adoption of the manufacturing method of the semiconductor device, the surface of the bonding interface layer on the second chip has high cleanliness, the mixed bonding between the second chip and the first chip is prevented from being abnormal (for example, gaps or impurities exist at the interface after the mixed bonding), and the reliability of the semiconductor device is prevented from being reduced.
The above description is only for the purpose of describing the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are intended to fall within the scope of the appended claims.
Claims (13)
1. A method of manufacturing a semiconductor device, comprising:
step S1, forming a plurality of chips which are qualified in testing, wherein a bonding interface layer and a protective layer are sequentially formed on the two opposite first surfaces and the second surfaces of each chip;
step S2, providing a second slide, forming a second bonding adhesive layer, temporarily bonding the chip with the second slide through the second bonding adhesive layer, wherein the protective layer on the first surface of the chip is in contact with the second bonding adhesive layer, and a gap is formed between the adjacent chips;
step S3, covering a dielectric layer on the chip, the dielectric layer filling the gap;
step S4, flattening one side of the chip far away from the second slide glass until the bonding interface layer on the second side of the chip is exposed;
step S5, bonding the chip with a target wafer through the bonding interface layer on the second surface;
step S6, performing a de-bonding process to remove the second carrier, wherein a portion of the second bonding glue layer remains on the protective layer of the first surface; and the number of the first and second groups,
step S7, planarizing a side of the chip away from the target wafer to remove the remaining second bonding glue layer and the protective layer on the first surface, and exposing the bonding interface layer on the first surface to obtain a bonding structure.
2. The method for manufacturing the semiconductor device according to claim 1, wherein the step S1 includes:
providing a device wafer;
sequentially forming a first bonding interface layer and a first protective layer on the front surface of the device wafer;
providing a first carrier, forming a first bonding adhesive layer, temporarily bonding the device wafer with the first carrier through the first bonding adhesive layer, and contacting the first protective layer with the first bonding adhesive layer;
sequentially forming a second bonding interface layer and a second protective layer on the back surface of the device wafer, wherein the front surface and the back surface are opposite;
performing a de-bonding process to remove the first carrier; and the number of the first and second groups,
and performing a cutting process on the device wafer to obtain a chip qualified in test, wherein a part of the first bonding glue layer is remained on the first protective layer of the chip.
3. The method of manufacturing a semiconductor device according to claim 2, wherein after temporarily bonding the device wafer to the first carrier through the first bonding glue layer and before forming the second bonding interface layer on the back side of the device wafer, the method further comprises:
thinning the back of the device wafer; and the number of the first and second groups,
and forming a conductive through hole structure on the back surface of the device wafer.
4. The method of manufacturing a semiconductor device according to claim 2, wherein after forming the second bonding interface layer on the backside of the device wafer and before forming the second protective layer on the backside of the device wafer, the method further comprises:
and testing the chips on the device wafer, and marking the chips which are qualified in the test.
5. The method of manufacturing a semiconductor device according to claim 2, wherein the first side of the chip is a front side of the device wafer, and the second side of the chip is a back side of the device wafer; in the step S4, planarizing a side of the chip away from the second carrier to remove the second protective layer;
or the first surface of the chip is the back surface of the device wafer, and the second surface of the chip is the front surface of the device wafer; in the step S4, a side of the chip away from the second carrier is planarized to remove the remaining first bonding glue layer and the first protection layer.
6. The method for manufacturing a semiconductor device according to claim 1, wherein the step S3 includes:
forming a third bonding glue layer in the gap, wherein the top surface of the third bonding glue layer is lower than the top surface of the chip; and the number of the first and second groups,
and covering an oxide layer on the chip and the third bonding adhesive layer, wherein the third bonding adhesive layer and the oxide layer form the dielectric layer.
7. The method for manufacturing a semiconductor device according to claim 1, wherein after the step S4 and before the step S5 and/or after the step S7, a plasma process is performed to activate the bonding interface layer on the second face of the chip and the bonding interface layer on the first face of the chip.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the second carrier sheet is a light-transmitting substrate; the step S6 includes: and irradiating the second slide glass and the second bonding adhesive layer by adopting laser so as to decompose the second bonding adhesive layer and further remove the second slide glass and part of the second bonding adhesive layer.
9. The method for manufacturing a semiconductor device according to any one of claims 1 to 8, further comprising:
and circularly and repeatedly executing the steps S1 to S7, and taking the bonded structure obtained by executing the steps S1 to S7 at the previous time as a target wafer for executing the steps S1 to S7 at the next time.
10. A semiconductor device, comprising:
a first chip;
the second chip is provided with a first surface and a second surface which are opposite, at least the first surface is provided with a bonding interface layer, and the second chip is bonded with the first chip through the bonding interface layer on the first surface;
the oxide layer covers the side wall of a part of the height of the second chip; and the number of the first and second groups,
and the bonding glue layer covers the side wall of the other part of the height of the second chip.
11. The semiconductor device according to claim 10, wherein the second chip having at least two layers bonded to the first chip, and wherein a bonding interface layer on a second side of the second chip close to the first chip is bonded to a bonding interface layer on a first side or a second side of the second chip remote from the first chip.
12. The semiconductor device according to claim 10 or 11, wherein the first face is a front face of the second chip, and the second face is a back face of the chip; or, the first surface is a back surface of the second chip, and the second surface is a front surface of the chip.
13. The semiconductor device according to claim 10, wherein the oxide layer covers a sidewall of the second chip close to a partial height of the first chip; the bonding glue layer covers the side wall of the second chip far away from the other part of the height of the first chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011502393.8A CN114649219A (en) | 2020-12-17 | 2020-12-17 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011502393.8A CN114649219A (en) | 2020-12-17 | 2020-12-17 | Semiconductor device and method for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114649219A true CN114649219A (en) | 2022-06-21 |
Family
ID=81990159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011502393.8A Pending CN114649219A (en) | 2020-12-17 | 2020-12-17 | Semiconductor device and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114649219A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024082359A1 (en) * | 2022-10-17 | 2024-04-25 | 长鑫存储技术有限公司 | Semiconductor dicing method |
-
2020
- 2020-12-17 CN CN202011502393.8A patent/CN114649219A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024082359A1 (en) * | 2022-10-17 | 2024-04-25 | 长鑫存储技术有限公司 | Semiconductor dicing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI774684B (en) | Wafer-level etching methods for planar photonics circuits and devices | |
| TWI556349B (en) | Semiconductor device structure and fabricating method thereof | |
| CN102468279B (en) | Integrated circuit device and method for preparing same | |
| US9620430B2 (en) | Sawing underfill in packaging processes | |
| CN100580869C (en) | Substrate treating method and method of manufacturing semiconductor apparatus | |
| US8455301B2 (en) | Method of fabricating stacked chips in a semiconductor package | |
| TWI564992B (en) | Manufacturing method of semiconductor device | |
| US20100279463A1 (en) | Method of forming stacked-die packages | |
| WO2021134940A1 (en) | Bonding structure and fabrication method therefor | |
| JP2007251157A (en) | Method for manufacturing wafer level laminate package | |
| US20120049332A1 (en) | Semiconductor package and method for manufacturing the same | |
| CN110137096A (en) | A kind of bonding structure and its manufacturing method | |
| CN104347528A (en) | Semiconductor package and fabrication method thereof | |
| US9070672B2 (en) | Semiconductor device packaging structure and packaging method | |
| US8409927B1 (en) | Methods for fabricating integrated circuit systems including high reliability die under-fill | |
| US8652939B2 (en) | Method and apparatus for die assembly | |
| US8772136B2 (en) | Method for fabricating semiconductor device | |
| CN114649219A (en) | Semiconductor device and method for manufacturing the same | |
| CN114628250A (en) | Wafer scribing method | |
| US20170373003A1 (en) | Semiconductor chip and multi-chip package using thereof | |
| US9177862B2 (en) | Semiconductor stack structure and fabrication method thereof | |
| CN110867387A (en) | Bonding structure and manufacturing method thereof | |
| CN114649218B (en) | Semiconductor device and method for manufacturing the same | |
| JP2015115387A (en) | Method of manufacturing semiconductor device | |
| KR101064288B1 (en) | Methode of forming a contact hole in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Country or region after: China Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Applicant after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Applicant before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |
|
| CB02 | Change of applicant information |