WO2021134940A1

WO2021134940A1 - Bonding structure and fabrication method therefor

Info

Publication number: WO2021134940A1
Application number: PCT/CN2020/081525
Authority: WO
Inventors: 刘天建; 胡杏; 占迪; 郭万里
Original assignee: 武汉新芯集成电路制造有限公司
Priority date: 2019-12-30
Filing date: 2020-03-27
Publication date: 2021-07-08
Also published as: CN111106022A

Abstract

Provided in the present invention are a bonding structure and a fabrication method therefor. A chip is bonded onto a wafer, a mixed bonding structure is formed on a die of the wafer, and a back connection line structure and a mixed bonding structure are also pre-formed on the back surface of the chip. Thus, electrical lead-out of an interconnecting structure in the chip is implemented by means of the back connection line structure, and the chip can further be bonded to the mixed bonding structure on the die by means of a mixed interconnecting structure on the chip, thus achieving the interconnection of the chip and the wafer. In the present solution, there is no need to carry out the processes of filling and grinding a large number of dielectric layers after chip bonding, which, while reducing fabrication costs can better ensure consistency between chips, and has better scalability.

Description

Bonding structure and manufacturing method thereof

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on December 30, 2019, the application number is 201911403367.7, and the invention title is "a bonding structure and its manufacturing method", the entire content of which is incorporated herein by reference Applying.

Technical field

The invention relates to the field of semiconductor devices and their manufacturing, in particular to a bonding structure and a manufacturing method thereof.

Background technique

As semiconductor technology enters the post-Moore era, in order to meet the needs of high integration and high performance, the chip structure is developing in a three-dimensional direction, and wafer-level packaging technology has been widely used. However, wafer-level packaging is a monolithic wafer. Round packaging, even if there is a failed die, it must be packaged, resulting in a waste of resources. At present, chip-to-wafer packaging has become another research hotspot, and there are still many problems to be solved on how to achieve industrialization in the process.

Summary of the invention

In view of this, the purpose of the present invention is to provide a bonding structure and a manufacturing method thereof, which realize chip-to-wafer packaging and have better implementability.

In order to achieve the above objectives, the present invention has the following technical solutions:

A method for manufacturing a bonding structure includes:

A bottom wafer is provided, the bottom wafer has dies arranged in an array, a hybrid bonding structure is formed on the surface of the dies, and the hybrid bonding structure includes a dielectric bonding layer and a conductive bonding pad;

Provide 1st to Nth chips, N≥1, pre-formed with a back connection structure and a hybrid bonding structure from the back of the chip, the back connection structure respectively connects the interconnection lines in the chip and the conductive bonds of the chip Bonding pads, and when N≥2, a hybrid bonding structure is also formed on the front side of the first to N-1th chips, and the conductive bonding pads on the front side are connected to the interconnection lines in the chip;

Using the hybrid bonding structure, the n-th chip is sequentially bonded on each die of the bottom wafer to realize the interconnection between the chip and the die, and n is from 1 to N and is a natural number.

Optionally, a pad is further formed on the front side of the Nth chip, and the pad is connected to an interconnection line in the Nth chip.

Optionally, each chip passes the wafer level test.

Optionally, the material of the conductive bonding pad is copper, and the material of the dielectric bonding layer includes silicon oxide, NDC, and/or a combination thereof.

Optionally, the method for forming the chip includes:

Provide wafers to be bonded with chips formed;

Bond the carrier on the front side of the wafer to be bonded;

Using the carrier as a supporting wafer to form a back connection structure and a hybrid bonding structure on the back of the wafer to be bonded;

Remove the slide

The wafer to be bonded is cut to obtain chips for bonding.

A bonding structure including:

A bottom wafer, the bottom wafer has dies arranged in an array, a hybrid bonding structure is formed on the surface of the dies, and the hybrid bonding structure includes a dielectric bonding layer and a conductive bonding pad;

The first to Nth chips, N≥1 and a natural number, a back wiring structure and a hybrid bonding structure are formed on the back of the chip, and the back wiring structure is connected to the interconnection lines and conductive bonding in the chip, respectively When N≥2, the hybrid bonding structure is also formed on the front side of the first to N-1th chips, and the conductive bonding pad on the front side is connected to the interconnection line in the chip, and each of the chips uses hybrid bonding The structure is sequentially stacked and bonded on the die.

Optionally, each chip passes the wafer level test.

In the bonding structure and the manufacturing method thereof provided by the embodiments of the present invention, a chip is bonded on a wafer, a hybrid bonding structure is formed on the die of the wafer, and a back wiring structure and a hybrid bonding structure are also preformed on the back of the chip In this way, the electrical lead-out of the interconnection structure in the chip is realized through the back wiring structure, and the hybrid interconnection structure on the chip can be bonded to the hybrid bonding structure on the die to realize the chip-to-wafer interconnection. In this solution, there is no need to fill and grind a large number of dielectric layers after the chip bonding, which reduces the manufacturing cost, and at the same time can better ensure the consistency between the chips, and has better implementability.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. A person of ordinary skill in the art can obtain other drawings based on these drawings without creative work.

Fig. 1 shows a schematic flow chart of a method for manufacturing a bonding structure according to an embodiment of the present invention;

Figures 2-4 show schematic structural diagrams in the process of forming a bonding structure according to the manufacturing method of the first embodiment of the present invention;

5-8 show schematic structural diagrams in the process of forming a bonding structure according to the manufacturing method of the second embodiment of the present invention;

9-15 show schematic diagrams of the chip structure in the process of forming the chip in the bonding structure according to the manufacturing method of the embodiment of the present invention.

Detailed ways

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do so without departing from the connotation of the present invention. Similar promotion, therefore, the present invention is not limited by the specific embodiments disclosed below.

Secondly, the present invention will be described in detail in conjunction with schematic diagrams. In detailing the embodiments of the present invention, for ease of description, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not be limited here. The scope of protection of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual production.

As described in the background art, the current chip-to-wafer packaging has become another research hotspot, and how to achieve industrialization in the process still has many problems to be solved. To this end, the present application provides a method for manufacturing a bonding structure, as shown in FIG. 1, including:

N chips are provided, N≥1, a back wiring structure and a hybrid bonding structure are preformed on the back of the chip, and the back wiring structure is connected to the interconnection lines and conductive bonding pads in the chip, and when When N≥2, a hybrid bonding structure is also formed on the front surface of the first to N-1th chips, and the conductive bonding pads are connected to the interconnection lines in the chip;

Using the hybrid bonding structure, the n-th chip is sequentially bonded on each die to realize the interconnection between the chip and the die, and n is from 1 to N.

In this application, the chip is bonded on the wafer, and the hybrid bonding structure is formed on the die of the wafer. The back wiring structure and the hybrid bonding structure are also preformed on the back side of the chip. In this way, it is realized by the back wiring structure. The electrical lead-out of the interconnection structure in the chip can further be bonded to the hybrid bonding structure on the die through the hybrid interconnection structure on the chip to realize the chip-to-wafer interconnection. In this solution, there is no need to fill and grind a large number of dielectric layers after the chip bonding, which reduces the manufacturing cost, and at the same time can better ensure the consistency between the chips, and has better implementability.

In order to better understand the technical solutions and technical effects of the present application, different embodiments will be described below with reference to the accompanying drawings.

Example one

In this embodiment, only one layer of chips is bonded on the wafer. This method has low manufacturing cost, and at the same time can better ensure the consistency between the chips, and has better implementability.

In step S101, a bottom wafer 10 is provided. The bottom wafer 10 has die 10' arranged in an array, and a hybrid bonding structure is formed on the surface of the die 10', and the hybrid bonding structure includes a dielectric bonding layer 120 and the conductive bonding pad 122 are shown in FIG. 2.

The wafer 100 may have completed device processing and formed a hybrid bonding structure on a substrate 100, and the substrate 100 may have formed a device structure and an interconnection line (not shown) electrically connecting the device structure. The structure is covered by a dielectric layer 110. The dielectric layer 110 may include multiple layers, such as an interlayer dielectric layer and an intermetal dielectric layer, which may be silicon oxide. The interconnection lines are formed in the dielectric material. The device structure may be a MOS device, For sensor devices, storage devices, and/or other passive devices, the interconnection lines may include multiple layers, and the interconnection lines of different layers may be interconnected through contact plugs, vias, etc., and the interconnection lines may be made of metal materials, for example, Tungsten, aluminum, copper, etc. In the illustration of the embodiment of the present application, only the dielectric layer 110 is shown, and the device structure and interconnection lines are not shown. This is just to simplify the drawings. It is understandable that in different designs and applications In this, the required device structure and interconnection lines of the required structure can be formed as required.

After the device processing is completed, the hybrid bonding structure is continued to be formed on the surface of the wafer. The surface is the surface on which the device structure is formed. It can also be called the front side of the wafer. The hybrid bonding structure means that the bonding interface is made of different materials. In the present application, the hybrid bonding structure includes a dielectric bonding layer 120 and a conductive bonding pad 122. The conductive bonding pad 122 is formed in the dielectric bonding layer 120 and is connected to the die The interconnection lines in the die are electrically connected. Generally, the conductive bonding pad 122 is formed on the top-level interconnection line in the die, and is electrically connected to the top-level interconnection line, so as to realize the electrical lead-out of the interconnection line in the die. Wherein, the dielectric bonding layer 120 is a dielectric material for bonding, which can be a single-layer or stacked-layer structure, for example, silicon oxide (bonding oxide), silicon nitride, NDC (Nitrogen doped Silicon Carbide), or their The combination. The conductive bonding pad 122 is a bonding conductive material, for example, a bonding metal material, and the bonding metal material may be, for example, copper. The conductive bonding pad 122 may have a suitable structure. In order to simplify the drawings, only this part is shown in the figure. In an example, it may include a bottom connection hole and a via hole (not shown). .

In step S102, the first chip 20 is provided, as shown in FIG. 3.

In the embodiment of the present application, the first chip 20 is a structure obtained by dicing the die after the wafer completes device processing, and the chip may be a pass die after the wafer-level test is completed. The first chip 20 may include a substrate 200, a device structure formed on the substrate 200, and an interconnection line 212 that electrically connects the device structure. The device structure is covered by a dielectric layer 210. The dielectric layer 210 may include multiple layers, for example, Including an interlayer dielectric layer and an intermetal dielectric layer, which may be silicon oxide, the interconnection lines are formed in the dielectric material, the device structure may have the same or different device structure as that in the bottom wafer die, and the interconnection lines may include multiple layers The interconnection lines of different layers can be interconnected through contact plugs, vias, etc., and the interconnection lines can be made of metal materials, such as tungsten, aluminum, copper, and the like. In the illustration of the embodiment of the present application, only the dielectric layer 210 and a layer of interconnection lines 212 are shown. This is only to simplify the drawings. It is understood that in different designs and applications, it can be used as required. Form the required device structure and interconnect lines of the required structure.

In addition, a back wiring structure 216 and

hybrid bonding structures

220 and 222 have been pre-formed on the back surface of the chip 20. The back surface of the chip 20 is the back surface of the substrate 200, that is, the surface opposite to the surface of the substrate 200 for processing the device structure. The back wiring structure 216 penetrates the substrate 200 to the interconnection line 212, and an isolation layer 217 is formed between the back wiring structure 216 and the substrate 200 to electrically isolate the device structure. The back wiring structure 216 may be a through silicon via structure, the isolation layer 217 may be formed on the sidewall of the through silicon via structure, and the interconnection line 212 may be the first metal wiring layer of the device structure.

The hybrid bonding structure on the same bottom wafer, the hybrid bonding structure on the first chip also includes the dielectric bonding layer 220 and the conductive bonding pad 222, which can be the same as or different from the hybrid bonding structure on the bottom wafer Material and structure, the conductive bonding pad 222 of the chip is formed on the back wiring structure 216 and is electrically connected to it. In this way, before the chip 20 is bonded to the die on the bottom wafer, the electrical lead-out structure and the bonding structure of the interconnection line 212 are pre-formed on the back of the chip, wherein the electrical lead-out structure includes a back wiring structure 216 and conductive bonding pad 222. The bonding structure includes a dielectric bonding layer 220 and a conductive bonding pad 222. In this way, there is no need to fill and grind a large number of dielectric layers after chip bonding in the subsequent bonding process, which reduces manufacturing Cost, and at the same time, it can better ensure the consistency between the chips, and has better implementability.

In this embodiment, only one layer of the first chip 20 is bonded on the bottom wafer 10, and a pad 214 may be pre-formed on the front surface of the chip. As shown in FIG. 3, the pad 214 is electrically connected to the first chip. The interconnection line 212 in the chip 20 may be the top metal connection layer of the device structure of the chip 20. In this way, after the bonding is completed, the pad 214 on the chip 20 can be used as the input/output port of the entire bonding structure, which reduces the manufacturing cost and has better implementability.

In step S103, the hybrid bonding structure is used to bond the first chip 20 on each die 10' of the bottom wafer 10 to realize the interconnection between the first chip 20 and the die 10', as shown in FIG. 4.

Hybrid bonding structures

120 and 122 are formed on the bottom wafer 10, and

hybrid bonding structures

220 and 222 are also pre-formed on the back surface of the first chip 20. These hybrid bonding structures can be cleaned before bonding. Then, the conductive bonding pad 222 of the first chip 20 is aligned with the conductive bonding pad 122 on the die, and the bonding force between the hybrid bonding structure is used to realize the bonding connection between the first chip 20 and the die 10' By bonding each first chip 20 to each die 10' on the bottom wafer 10 one by one, the chip-to-wafer bonding can be realized.

In this embodiment, only one layer of chips, that is, the first chip 20, is bonded to the bare chip, and the first chip 20 is pre-formed with pads. After bonding, the bonding structure can be processed, which has good performance. Implementation.

The embodiment of the present application also provides a bonding structure formed by the above method, as shown in FIG. 4, including:

The bottom wafer 10 has dies 10' arranged in an array, and

hybrid bonding structures

120, 122 are formed on the surface of the dies 10'. The hybrid bonding structure includes a dielectric bonding layer 120 and Conductive bonding pad 122;

On the first chip 20, a back wiring structure 216 and

hybrid bonding structures

220, 222 are formed on the back of the first chip 20, and the back wiring structure 216 is respectively connected to the interconnection lines 212 and the conductive bonding pads in the chip 20 222. The first chip is stacked and bonded on the die 10' using a hybrid bonding structure.

Example two

In this embodiment, multiple layers of chips are bonded on a wafer. This method has low manufacturing cost and high flexibility, and at the same time, it can better ensure the consistency between the chips, and has better implementability. The following will focus on the different parts from the first embodiment, and the same parts will not be repeated.

In step S201, a bottom wafer 10 is provided. The bottom wafer 10 has die 10' arranged in an array, and a hybrid bonding structure is formed on the surface of the die 10', and the hybrid bonding structure includes a dielectric bonding layer 120 and the conductive bonding pad 122 are shown in FIG. 5.

Same as step S101 in the first embodiment.

In step S202, the first to Nth chips 20 are provided, where N≧2 and a natural number, as shown in FIG. 6 and FIG. 3.

In this embodiment, multiple layers of chips are to be sequentially bonded to the bare chip 10' of the bottom wafer. For ease of description, the chips of each layer are marked as the first to Nth chips, and the first chip is bonded to the bare chip. On the chip, the second chip is bonded to the first chip, and so on, to realize the bonding of the multilayer chip to the wafer.

As in the first embodiment above, these chips 20 are structures obtained by cutting the die after the wafer is processed to complete the device. The chips may be intact pass dies after the wafer-level testing is completed. The chip 20 may include a substrate 200 and a device structure already formed on the substrate 200 and an interconnection line 212 that electrically connects the device structure. Different chips may have the same or different device structures. As in the first embodiment above, only the dielectric layer 210 and a layer of interconnection lines 212 are shown here. This is only to simplify the drawings. It should be understood that in different designs and applications, the required ones can be formed as required. Device structure and interconnection lines of the required structure.

Among them, the first to N-1th chips are intermediate bonding layers. As shown in FIG. 6, for the chips 20 located in the intermediate layer after bonding, a back wiring structure 216 and hybrid bonding are formed on the back of the chip 20 in advance.

Structures

220 and 222. The hybrid bonding structure also includes a dielectric bonding layer 220 and a conductive bonding pad 222. The back wiring structure 216 connects the interconnection lines 212 in the chip 20 and the conductive bonding pad 222 of the chip 20, respectively. , The front side of the chip 20 is also formed with

hybrid bonding structures

230 and 232, and the conductive bonding pad 232 on the front side is connected to the interconnection line 212 in the chip. For the Nth chip as the top chip, referring to FIG. 3, only the back wiring structure 216 and the

hybrid bonding structures

220 and 222 are pre-formed on the back of the chip 20 on the top layer.

The back wiring structure 216 and the

hybrid bonding structures

220 and 222 are pre-formed on the back of the first to Nth chips. These hybrid bonding structures may have the same or different materials and structures. As in the first embodiment, each chip 20 and Before the die on the bottom wafer is bonded, the electrical lead-out structure and the bonding structure of the interconnection line 212 are pre-formed on the back of the chip. The electrical lead-out structure includes a back wiring structure 216 and a conductive bonding pad. 222. The bonding structure includes a dielectric bonding layer 220 and a conductive bonding pad 222. In this way, there is no need to fill and grind a large number of dielectric layers after chip bonding in the subsequent bonding process, which reduces manufacturing costs and can better To ensure the consistency between chips, it has better implementability.

Hybrid bonding structures

230 and 232 are also formed on the front surface of the first to N-1th chips. The conductive bonding pads 232 in the hybrid bonding structure are electrically connected to the interconnection lines 212 in the chip, and the interconnections connected thereto are interconnected. The wire 212 may be a top metal layer, and the pre-formed

hybrid bonding structure

230, 232 is used for further bonding with the chip thereon.

Further, a pad 214 may be pre-formed on the front surface of the Nth chip, and the pad 214 is electrically connected to the interconnection line 212 in the Nth chip 20. The interconnection line may be the top metal connection of the device structure of the chip 20. Line layer.

The substrate in the foregoing embodiments may be a semiconductor substrate, for example, a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator) or GOI (Germanium On Insulator) Wait.

In step S203, using the hybrid bonding structure, the n-th chip is sequentially bonded on each die 10' of the bottom wafer 10 to realize the interconnection between the chip and the die, n is from 1 to N and is a natural number, refer to the figure 7 and Figure 8.

The hybrid bonding structure is preformed on the back surface of the first to Nth chips, and the hybrid bonding structure is also preformed on the front surface of the first to N-1th chips. In this way, the nth chip is sequentially bonded on the bare chip. That is, multi-layer chip-to-wafer bonding can be realized.

For ease of understanding, the description is given by taking a two-layer chip bonding to a wafer as an example.

Specifically, referring to FIG. 7, first, using the hybrid bonding structure, the first chip 20-1 is bonded on each die 10' of the bottom wafer 10 to realize the first chip 20-1 and the die. 10' interconnection.

Before bonding, these hybrid bonding structures can be cleaned. Then, the conductive bonding pad 222 of the first chip 20-1 is aligned with the conductive bonding pad 122 on the die, and the bonding force between the hybrid bonding structure is used to realize the first chip 20-1 and the die 10' In the bonding connection, each first chip 20-1 is bonded to each die 10' on the bottom wafer 10 one by one, that is, the bonding of the first chip 20-1 to the wafer can be realized.

Referring to FIG. 8, next, continue to use the hybrid bonding structure to bond the second chip 20-2 on each of the first chips 20-1 to realize the mutual interaction between the second chip 20-2 and the first chip 20-1. even.

Similarly, before bonding, these hybrid bonding structures can be cleaned. Then, align the conductive bonding pads 222 of the second chip 20-2 with the conductive bonding pads 232 on the front of the first chip 20-1, and use the bonding force between the hybrid bonding structures to realize the second chip 20-2 With the bonding connection with the first chip 20-1, each second chip 20-2 is bonded to the first chip 20-1 on each bare chip one by one, that is, the first chip 20-1 to the second chip 20- can be realized. 2’s bonding.

If it is still necessary to continue to bond the third chip or more chips, the same steps can be used.

If the second chip is the top chip, the front surface of the second chip can be pre-formed with pads, and the bonding structure can be processed after bonding, which has good feasibility.

The embodiment of the present application also provides a bonding structure formed by the above method, as shown in FIG. 8, including:

The bottom wafer 10 has dies 10' arranged in an array, and

hybrid bonding structures

The first to Nth chips, and the backside connection structure 216 and

hybrid bonding structures

220 and 222 are formed on the back surface of the first to Nth chips 20, and the back connection structure 216 is respectively connected to the interconnection lines 212 in the chip 20 And conductive bonding pads 222,

hybrid bonding structures

230, 232 are formed on the front surface of the first to N-1th chips, and the conductive bonding pads 232 on the front side are connected to the interconnection lines 212 in the chip, and the first to first to first N chips are sequentially stacked and bonded on the die using a hybrid bonding structure.

In addition, the present application also provides an embodiment of the method for forming the chip in the above embodiment, which will be described in detail below with reference to the accompanying drawings.

First, in step S1201, as shown in FIG. 9, a wafer 20' is provided, in which the chip 20 for bonding described above is formed.

For ease of description, the wafer on which the bonding chip 20 is formed is referred to as the wafer to be bonded 20' in this application. The front surface of the substrate 200 of the wafer to be bonded 20' has completed the device processing process. For the wafer with the top layer of the chip to be bonded, the device structure (not shown in the figure), the interconnection line 212 and the pad ( The processing of the device structure (not shown in the figure), the interconnection line 212, and the processing of the front

hybrid bonding structure

230, 232, the device structure and the interconnection have been completed for the wafer with the intermediate bonding chip. The line 212 is formed in the dielectric layer 210, and the

hybrid bonding structure

230, 232 or the liner may be covered by the dielectric layer 230 to protect it from damage in subsequent processes.

Then, the carrier 300 is bonded on the front surface of the wafer 20' to be bonded, as shown in FIG. 10.

The carrier 300 only plays a supporting role, and may be a substrate that has not undergone a device processing process, for example, may be a silicon pad.

Then, in step S1202, using the carrier 300 as a supporting wafer, a back wiring structure 216 and

hybrid bonding structures

220 and 222 are formed on the back of the wafer to be bonded 20', as shown in FIG. 14.

Specifically, a dielectric layer 218 may be formed on the back surface of the substrate 200 of the wafer 20' to be bonded first. The dielectric layer may be a hard mask layer. As shown in FIG. 10, the dielectric layer may be, for example, silicon nitride, Silicon oxide or their stacked layers, and a mask layer 219 is formed on the dielectric layer 218. The mask layer 219 can be a photosensitive resist, and an etching pattern can be formed in the mask layer 219 by using photolithography technology. Refer to the figure 11 shown.

Then, under the mask of the mask layer 219, etching is performed from the backside of the substrate 200 of the wafer to be bonded 20', for example, reactive ion etching, to form a chip penetrating into the chip of the wafer to be bonded 20' The through-silicon via of the interconnection line 212 is shown in FIG. 12, and an isolation layer 217 is formed on the sidewall of the through-silicon via. The isolation layer is a dielectric material, such as silicon oxide or a stack of silicon oxide and silicon nitride. The layer plays an insulating role. Then, a metal material is deposited, for example, a metal copper is deposited, and planarized, so that a back connection structure 216 is filled in the through silicon via, as shown in FIG. 13.

Next, continue to deposit the dielectric bonding layer 220. The dielectric bonding layer may be a single layer or a laminated structure, for example, silicon oxide or a stack of silicon oxide and NDC, and a conductive bond is formed in the dielectric bonding layer 220 The bonding pads 222, thereby forming

bonding structures

220, 222, as shown in FIG. 14.

In step S1203, the slide 300 is removed, as shown in FIG. 15.

After the carrier 300 is removed, the wafer to be bonded 20' can be transferred to another attachment, such as an adhesive film, and the pad on the front of the chip 20 is exposed, or the conductive bonding pad 232 The surface is exposed to form a hybrid bonding interface, as shown in Figure 15.

In step S1204, the wafer to be bonded is cut to obtain chips for bonding.

The wafer 20' to be bonded can be cut by laser or mechanical cutting to obtain the chip 20 for bonding.

The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the structural embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant part can refer to the part of the description of the method embodiment.

The above are only the preferred embodiments of the present invention. Although the present invention has been disclosed as above in preferred embodiments, it is not intended to limit the present invention. Anyone familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into equivalent changes. Examples. Therefore, all simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

A method for manufacturing a bonding structure, which is characterized in that it comprises:

A bottom wafer is provided, the bottom wafer has dies arranged in an array, a hybrid bonding structure is formed on the surface of the dies, and the hybrid bonding structure includes a dielectric bonding layer and a conductive bonding pad;

Provide 1st to Nth chips, N≥1, pre-formed with a back connection structure and a hybrid bonding structure from the back of the chip, the back connection structure respectively connects the interconnection lines in the chip and the conductive bonds of the chip Bonding pads, and when N≥2, a hybrid bonding structure is also formed on the front side of the first to N-1th chips, and the conductive bonding pads on the front side are connected to the interconnection lines in the chip;

Using the hybrid bonding structure, the n-th chip is sequentially bonded on each die of the bottom wafer to realize the interconnection between the chip and the die, and n is from 1 to N and is a natural number.
The manufacturing method according to claim 1, wherein a pad is further formed on the front surface of the Nth chip, and the pad is connected to the interconnection line in the Nth chip.
The manufacturing method of claim 1, wherein each chip passes a wafer-level test.
The manufacturing method according to claim 1, wherein the material of the conductive bonding pad is copper, and the material of the dielectric bonding layer includes silicon oxide, NDC, and/or a combination thereof.
The manufacturing method according to any one of claims 1 to 4, wherein the method for forming the chip comprises:

Provide wafers to be bonded with chips formed;

Bond the carrier on the front side of the wafer to be bonded;

Using the carrier as a supporting wafer to form a back connection structure and a hybrid bonding structure on the back of the wafer to be bonded;

Remove the slide

The wafer to be bonded is cut to obtain chips for bonding.
A bonding structure, characterized in that it comprises:

A bottom wafer, the bottom wafer has dies arranged in an array, a hybrid bonding structure is formed on the surface of the dies, and the hybrid bonding structure includes a dielectric bonding layer and a conductive bonding pad;

The first to Nth chips, N≥1 and a natural number, a back wiring structure and a hybrid bonding structure are formed on the back of the chip, and the back wiring structure is connected to the interconnection lines and conductive bonding in the chip, respectively When N≥2, the hybrid bonding structure is also formed on the front side of the first to N-1th chips, and the conductive bonding pad on the front side is connected to the interconnection line in the chip, and each of the chips uses hybrid bonding The structure is sequentially stacked and bonded on the die.
7. The structure according to claim 6, wherein a pad is further formed on the front surface of the Nth chip, and the pad is connected to the interconnection line in the Nth chip.
7. The structure of claim 6, wherein each chip passes a wafer level test.
The structure according to claim 6, wherein the material of the conductive bonding pad is copper, and the material of the dielectric bonding layer includes silicon oxide, NDC, and/or a combination thereof.