CN101026102A

CN101026102A - Stacked chip package using warp-proof insulative material and method of manufacturing the same

Info

Publication number: CN101026102A
Application number: CNA2007100040988A
Authority: CN
Inventors: 权容载; 李康旭; 马金希; 韩成一; 李东镐
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2006-01-24
Filing date: 2007-01-23
Publication date: 2007-08-29
Also published as: KR100703012B1

Abstract

In laminated chip structure and manufacturing method thereof, relative simple technology is used for fully filling the clearance between upper chip and lower chip thereby eliminating the clearance and preventing problems of fracture and stripping in relation of the clearance. The invention can be used in bonding method of chip level and wafer level. Before laminating chips or wafers, photosensitive polymer layer is applied on a first chip or wafer. The photosensitive polymer layer is partly solidified in order to stabilize structure thereof and keep adhesiveness performance thereof. A second chip or wafer is laminated, aligned and bonded to the first chip or wafer, and then the photosensitive polymer layer is solidified to completely bond the first and the second chips or wafers. In this manner, the adhesiveness between chips/wafers is greatly improved as well as clearance is fully filled. In addition, mechanical reliability is improved and mismatch of CTE is reduced, and warpage, fracture and stripping related problems can be reduced, thus, the rate of finished products and reliability can be improved.

Description

Use the stacked die encapsulation and the manufacture method thereof of warp-proof insulative material

Related application

The application requires the priority of the Korean Patent Application No. 10-2006-0007109 of application on January 24th, 2006 according to 35U.S.C.119, at this its content all is incorporated herein by reference.People such as the application and Yong-Chai Kwon, name is called the U.S. Patent Application Serial Number 11/436 of " Stacked Chip Package UsingPhotosensitive Polymer and Manufacturing Method Thereof ", 851 is relevant, U.S. Patent Application Serial Number 11/436,851 with the application apply on the same day and belong to same everyone, at this its content all is incorporated herein by reference.

Technical field

The present invention relates to comprise the semiconductor packages and the manufacture method thereof of stacked die encapsulating structure, this stacked die encapsulating structure utilization comprises the photosensitive polymer of band viscosity and anti-warpage performance.

Background technology

Semiconductor manufacturing and encapsulation technology have developed into the degree that device package can comprise a plurality of integrated circuit (IC) chip, and these a plurality of integrated circuit (IC) chip are bonded on together with stacked, three-dimensional relationship.This package level that is encapsulated in be you can well imagine for less form factor and high integration degree.This chip laminate structure can satisfy high speed operation, signal higher fan-out (fan-out), reduce noise rank, the low-power operation that the signal between the chip transmits and increase function in the single encapsulation.

Three-dimensional bonding techniques continues development.In the package level bonding structure, device is formed on the semiconductor wafer, and is cut into chip.Single chip is encapsulated in separately the encapsulation, and this encapsulation is stacked and be bonded together, to form a plurality of laminate packaging (MSP).In the past, the MSP of gained is extensive use of, but for modern Application, MSP is huger and heavy.

In the chip-scale bonding structure, device is formed on the semiconductor wafer, and is cut into chip.Stacked and the bonding of this single chip, and this chip-stack is encapsulated in single, public, the encapsulation, to form the encapsulation of multicore sheet (MCP) or three-dimensional chip laminate packaging (CSP).The MCP of gained has the characteristic of high finished product rate, and still, the PROCESS FOR TREATMENT amount is a problem, because during aligning and bond sequence, each single chip needs processed.

Recently, the wafer scale bonding structure becomes universal.In the wafer scale bonding structure, device is formed on the semiconductor wafer, and stacked a plurality of wafer, so that their respective chip is aligned.This wafer stack is bonded on together, is cut into chip-stack then.Each is encapsulated in this chip-stack in single, public, the encapsulation, to form wafer-level three-dimensional chip laminate packaging (WLCSP).The WL CSP of gained has the shortcoming of low rate of finished products.But the PROCESS FOR TREATMENT amount is high, because owing to stacked this chip of wafer scale, no longer need the processing of each single chip.

Chip-scale bonding and wafer scale bonding normally complicated with unsettled manufacturing process.In this bonding method, each chip uses the mutual in vertical direction transmission signals of centre-chip, vertical through hole.The intermediate chip through hole runs through each chip substrate, and be included in its top connection (landing) pad feature and its bottom the projection feature.According to conventional methods, when the projection of a chip and another bonding pads bonding, the telegraph key that this projection and pad at first take place closes, for example, under the temperature of the bonding eutectic point of the material that equals at least this node place to adopt, use heat pressing process, then do not fill up injection process, be used to fill the gap between the chip substrate, to guarantee mechanically link.Because the gap between the lower and upper chip substrate is less, for example, is about the order of magnitude of 20 μ m, it is insecure not filling up technology.Do not cause filling fully and evenly of gap if fill up technology, the space of gained may increase the possibility that produces fracture in the future so arbitrarily.In heating and cooling in future periodic process, this fracture may be expanded, and reduces the reliability of the chip laminate device of gained.

In addition, may form mechanical stress between the layer of chip or between the adjacent chips of encapsulation.This stress is not typically matched by the thermal coefficient of expansion (CTE) between two adjacent layers and causes.In the said chip stepped construction, the metal of chip substrate, connection pads and bonding material all have different CTR values.When standing a large amount of heating and cooling thermal cycle, this CTE does not match and may cause more fracture and peel off, and influences rate of finished products in the manufacture process and the device reliability in the course of work negatively.

Summary of the invention

The present invention relates to comprise the semiconductor packages and the manufacture method thereof of chip stacked laminated construction, this chip stacked laminated construction utilization comprises the photosensitive polymer of adhesiveness and anti-warpage performance.

The invention provides a kind of chip stacked encapsulating structure and manufacture method thereof, wherein use relative simple technology, the gap under the complete filling between chip and the last chip, this technology is eliminated space with the fracture relevant with this space with peel off problem.The present invention can be applied to chip-scale bonding and wafer scale bonding method.Before stacked die or stacked wafer, photosensitive polymer layer is applied to first chip or wafer.This photosensitive polymer layer so that make the Stability Analysis of Structures of this photosensitive polymer layer, is kept its adhesion property by partly solidified simultaneously.Second chip or wafer be stacked, aim at and be bonded to first chip or wafer, and this photosensitive polymer layer is cured then, with complete bonding first and second chips or wafer.In this way, improve the adhesion between the die/wafer widely, the complete filling in gap is provided simultaneously.In addition, Mechanical Reliability is enhanced not match with CTE and is reduced, and alleviates and fracture and peel off relevant problem.This causes the improvement of device yield and device reliability.

In one aspect, the present invention relates to a kind of method of making semiconductor device, this method comprises: form first semiconductor device on first substrate, this first semiconductor device is included in first bonding welding pad on the first surface of first substrate in the device region of first semiconductor device; On the first surface of first substrate, form first interconnection, this first interconnection is electrically coupled to first bonding welding pad, and pass first substrate formation conductive through hole, and this conductive through hole is electrically coupled to first interconnection and runs through the second surface of first substrate, and second surface is relative with first surface; Form second semiconductor device on second substrate, second semiconductor device comprises second bonding welding pad on the first surface of second substrate in the device region of second semiconductor device; Form second interconnection on the first surface of second substrate, this second interconnection is electrically coupled to second bonding welding pad; On the second surface of first substrate, photosensitive polymer layer is set, by this photosensitive polymer layer exposed portions serve conductive through hole; And the second surface that will comprise first substrate of photosensitive polymer layer is applied to the first surface of second substrate, and second interconnection of second substrate is aimed at the exposed portions serve of conductive through hole, so that first bonding welding pad is electrically coupled to second bonding welding pad.

In one embodiment, this photosensitive polymer layer is set also comprises, this photosensitive polymer layer of composition is with the exposed portions serve conductive through hole.

In another embodiment, first is interconnected on the direction of the outer rim of first substrate, and the first surface that crosses first substrate extends, and wherein second is interconnected on the direction of the outer rim of second substrate, and the first surface that crosses second substrate extends.

In another embodiment, in the drawn area of first semiconductor device, form this conductive through hole.In another embodiment, in the device region of first semiconductor device, form this conductive through hole.

In another embodiment, this method also is included in to be used first substrate and be registered to before second substrate, partly solidifies this photosensitive polymer layer.

In another embodiment, this method also is included in to be used first substrate and be registered to after second substrate, partly solidifies this photosensitive polymer layer.

In another embodiment, this photosensitive polymer layer comprises the photosensitive polymer layer of insulation, and this photosensitive polymer layer is set on the second surface of first substrate comprises: remove backing material from the second surface of first substrate, to expose the lower end of conductive through hole; The photosensitive polymer layer of insulation is set on the second surface of first substrate; Composition is somebody's turn to do the insulation photosensitive polymer layer, with lower end of exposing conductive through hole and the lower sidewall portion that covers conductive through hole; And solidify this insulation photosensitive polymer layer.

In another embodiment, this method also comprises: the photosensitive polymer layer of this insulation is provided with the photosensitive polymer layer of viscosity; Before first substrate being used and be registered to second substrate, partly solidify this sticking photosensitive polymer layer; And after first substrate being used and be registered to second substrate, partly solidify this sticking photosensitive polymer layer.

In another embodiment, this method also comprises this sticking photosensitive polymer layer of composition, to expose the lower end of conductive through hole.

In another embodiment, this method also comprises the upper surface that conductive layer is applied to second interconnection.

In another embodiment, form the conductive through hole that passes first substrate and comprise: form through hole in first substrate, this through hole runs through the first surface of first substrate and partly enters in first substrate; The insulating barrier of the sidewall of liner (line) through hole is set; Fill this through hole with electric conducting material, to form conductive through hole; And remove backing material from the second surface of first substrate, to expose the lower end of this conductive through hole.

In another embodiment, remove this backing material and comprise: grind the second surface of first substrate, to remove backing material; And the second surface and the partial insulative layer of etching first substrate, with the lower end of exposing conductive through hole and the bottom of conductive through hole lower end sidewall.

In another embodiment, first semiconductor device on formation first substrate on the public semiconductor wafer and second semiconductor device on second substrate.

In another embodiment, first semiconductor device on formation first substrate on first and second semiconductor wafers that separate and second semiconductor device on second substrate.

In another embodiment, this conductive through hole comprises first conductive through hole, and this photosensitive polymer layer comprises first photosensitive polymer layer, and also comprise: form second conductive through hole that passes second substrate, second conductive through hole is electrically coupled to second interconnection and runs through the second surface of second substrate, and second surface is relative with first surface; Second photosensitive polymer is set, by this second photosensitive polymer layer exposed portions serve, second through hole on the second surface of second substrate; On the first surface of the 3rd substrate, form the 3rd substrate that comprises the 3rd bonding pad; To comprise that the second surface of second substrate of second photosensitive polymer layer is applied to the first surface of the 3rd substrate, and the 3rd bonding pad of the 3rd substrate aimed at the exposed portions serve of second conductive through hole, second bonding welding pad is electrically coupled to the 3rd bonding pad.

In another embodiment, this second photosensitive polymer layer is set also comprises this second photosensitive polymer layer of composition, with exposed portions serve second conductive through hole.

In another embodiment, the 3rd substrate comprises the substrate that is selected from the group that is made of printed circuit board (PCB) (PCB), semiconductor device substrates and encapsulation built-in inserted plate.

In another embodiment, the method for claim 16 also comprises: before first substrate being used and be registered to second substrate, partly solidify this first photosensitive polymer layer; Before second substrate being used and be registered to the 3rd substrate, partly solidify this second photosensitive polymer layer; And with first substrate is used and be registered to second substrate after and with after the application of second substrate and being registered to the 3rd substrate, solidify this first and second photosensitive polymer layer simultaneously.

In another embodiment, this second photosensitive polymer layer comprises second photosensitive polymer layer of insulation, and this second photosensitive polymer layer is set on the second surface of second substrate comprises: remove backing material from the second surface of second substrate, to expose the lower end of second conductive through hole; Second photosensitive polymer layer of insulation is set on the second surface of second substrate; Second photosensitive polymer layer that composition should insulate is with lower end of exposing second conductive through hole and the lower sidewall portion that covers second conductive through hole; And second photosensitive polymer layer that solidifies this insulation.

In another embodiment, this method also comprises: second photosensitive polymer layer of this insulation is provided with second photosensitive polymer layer of viscosity; Before second substrate being used and be registered to the 3rd substrate, partly solidify this sticking second photosensitive polymer layer; And after second substrate is applied to and is registered to the 3rd substrate, partly solidify this sticking second photosensitive polymer layer.

In another embodiment, this method also comprises this sticking second photosensitive polymer layer of composition, to expose the lower end of second conductive through hole.

In another embodiment, be included in a plurality of first semiconductor device of formation on the public wafer at formation first semiconductor device on first substrate, each of a plurality of first semiconductor device has corresponding first interconnection and corresponding conductive through hole, and also be included in one of a plurality of first substrates are used and are registered to before each of second substrate, these a plurality of first semiconductor device of scribing are separating by a plurality of first semiconductor device.

In another embodiment, form second semiconductor device and be included in a plurality of second semiconductor device of formation on the public wafer, each of these a plurality of second semiconductor device has corresponding second interconnection and corresponding conductive through hole, and also be included in one of a plurality of second substrates are used and are registered to before each of first substrate, these a plurality of second semiconductor device of scribing are separating by a plurality of second semiconductor device.

In another embodiment, execution is provided with photosensitive polymer layer on the first surface of second substrate before these a plurality of second semiconductor device of scribing.

In another embodiment, this method also is included in to be used second substrate and be registered to before first substrate, partly solidifies this photosensitive polymer layer.

In another embodiment, this method also is included in to be used second substrate and be registered to after first substrate, solidifies this photosensitive polymer layer.

In another embodiment, forming first semiconductor device on first substrate comprises, on the first public wafer, form a plurality of first semiconductor device, each of these a plurality of first semiconductor device has corresponding first interconnection and corresponding conductive through hole, and form second semiconductor device and comprise, on the second public wafer, form a plurality of second semiconductor device, each of these a plurality of second semiconductor device has corresponding second interconnection, and wherein second substrate is used and is registered to first substrate and comprise, at first semiconductor device of a plurality of second semiconductor device on second wafer being used simultaneously and being registered on first wafer.

In another embodiment, this method also comprises, after a plurality of first semiconductor device of a plurality of second semiconductor device on second wafer being used simultaneously and are registered on first wafer, this first and second wafer of scribing is separating by a plurality of corresponding first and second semiconductor device.

In another embodiment, execution is provided with photosensitive polymer layer on the first surface of second substrate before scribing first and second wafers.

In another embodiment, this method also is included in a plurality of second semiconductor device application of second wafer and is registered to before a plurality of first semiconductor device of second wafer of first wafer, partly solidifies this photosensitive polymer layer.

In another embodiment, this method also is included in a plurality of second semiconductor device application of second wafer and is registered to after a plurality of first semiconductor device of second wafer of first wafer, partly solidifies this photosensitive polymer layer.

In another embodiment, this photosensitive polymer layer is the material that is selected from the group that is made of following composition: polyamide (polymide), Ju Ben oxazole (PBO), benzocyclobutene (BCB), epoxy resin, novolaks, melamine-phenol, acrylate and elastomer.

In another embodiment, this photosensitive polymer layer comprises photosensitive composition and bonding agent.

In another embodiment, this photosensitive polymer layer has first thermal coefficient of expansion, is higher than second thermal coefficient of expansion of substrate.

In another embodiment, be higher than the active device that first thermal coefficient of expansion compensation of photosensitive polymer layer of second thermal coefficient of expansion of substrate forms on the top of substrate, this top is relative with the photosensitive polymer layer with the 3rd thermal coefficient of expansion, the 3rd thermal coefficient of expansion is higher than second thermal coefficient of expansion of substrate, to prevent semiconductor device warpage in the subsequent thermal cyclic process of semiconductor device.

On the other hand, the present invention relates to a kind of semiconductor device, comprising: first semiconductor device on first substrate, first semiconductor device are included in first bonding welding pad on the first surface of first substrate in the device region of first semiconductor device; Form first interconnection on the first surface of first substrate, first interconnection is electrically coupled to first bonding welding pad; Pass first conductive through hole of first substrate, this conductive through hole is electrically coupled to first interconnection and runs through the second surface of first substrate, and second surface is relative with first surface; Second substrate comprises second bonding welding pad on the first surface of this second substrate; And first photosensitive polymer between the first surface of the second surface of first substrate and second substrate, these first photosensitive polymer bonding, first and second substrates, at least one of second bonding welding pad and first conductive through hole runs through first photosensitive polymer layer and contacts second bonding welding pad and another of first conductive through hole, so that first bonding welding pad is electrically coupled to second bonding welding pad.

In one embodiment, this device also comprises the second surface of first substrate and first insulating barrier between first photosensitive polymer layer, and this first conductive through hole runs through first insulating barrier, contacting second bonding welding pad of second substrate,

In another embodiment, this first insulating barrier covers the sidewall of the bottom of first conductive through hole.

In another embodiment, this device also comprises: second semiconductor device on the 3rd substrate, second semiconductor device comprise the 3rd bonding pad on the first surface of the 3rd substrate in the device region of second semiconductor device; On the first surface of the 3rd substrate second interconnection, this second interconnection is electrically coupled to the 3rd bonding pad; Pass second conductive through hole of the 3rd substrate, this second conductive through hole is electrically coupled to second interconnection and runs through the second surface of the 3rd substrate, and this second surface is relative with first surface; And second photosensitive polymer layer between the first surface of the second surface of the 3rd substrate and first substrate, this the second photosensitive polymer layer bonding the 3rd and first substrate, at least one of this first bonding welding pad and second conductive through hole runs through second photosensitive polymer layer and contacts first bonding welding pad and another of second conductive through hole, first bonding welding pad is electrically coupled to the 3rd bonding pad.

In another embodiment, this device also comprises the second surface of first substrate and first insulating barrier between first photosensitive polymer layer, this first conductive through hole runs through first insulating barrier, to contact second bonding welding pad of second substrate, and second insulating barrier between the second surface of the 3rd substrate and second photosensitive polymer layer, this second conductive through hole runs through second insulating barrier, to contact first bonding welding pad of first substrate.

In another embodiment, this first insulating barrier covers the sidewall of the bottom of first conductive through hole, and wherein this second insulating barrier covers the sidewall of the bottom of this second conductive through hole.

In another embodiment, first photosensitive polymer layer is patterned, to expose the part of first conductive through hole, contacting with second bonding welding pad, and wherein second photosensitive polymer layer is patterned, to expose the part of second conductive through hole, contacting with first bonding welding pad.

In another embodiment, first is interconnected on the direction of the outer rim of first substrate, and the first surface that crosses first substrate extends, and wherein second is interconnected on the direction of the outer rim of the 3rd substrate, and the first surface that crosses the 3rd substrate extends.

In another embodiment, first and second conductive through holes are located in the drawn area of first and second semiconductor device separately.

In another embodiment, first and second conductive through holes are positioned in the device region of each first and second semiconductor device.

In another embodiment, the far-end of each first and second conductive through hole and segment distal sidewall exceed the second surface extension of first substrate and second substrate respectively.

In another embodiment, first semiconductor device on formation first substrate on the public semiconductor wafer and second semiconductor device on the 3rd substrate.

In another embodiment, first semiconductor device on formation first substrate on first and second semiconductor wafers that separate and second semiconductor device on the 3rd substrate.

In another embodiment, this device also comprises the conductive layer on first upper surface that interconnects.

In another embodiment, second substrate comprises the substrate that is selected from the group that is made of printed circuit board (PCB) (PCB), semiconductor device substrates and encapsulation built-in inserted plate.

In another embodiment, this first photosensitive polymer layer is the material that is selected from the group that is made of following composition: polyamide, Ju Ben oxazole (PBO), benzocyclobutene (BCB), epoxy resin, novolaks, melamine-phenol, acrylate and elastomer.

In another embodiment, first photosensitive polymer layer has first thermal coefficient of expansion, is higher than second thermal coefficient of expansion of first substrate.

In another embodiment, be higher than the active device that first thermal coefficient of expansion compensation of first photosensitive polymer layer of second thermal coefficient of expansion of first substrate forms on the top of substrate, first substrate is relative with first photosensitive polymer layer with the 3rd thermal coefficient of expansion, the 3rd thermal coefficient of expansion is higher than second thermal coefficient of expansion of first substrate, with semiconductor device warpage in the subsequent thermal cyclic process that prevents semiconductor device.

Description of drawings

To understand above-mentioned and other purpose of the present invention, characteristics and advantage from the more specifically description of the preferred embodiments of the present invention, as shown in drawings, wherein in different views, identical reference character refers to identical parts from start to finish.This figure may not stress principle of the present invention in proportion.

Fig. 1 is the profile according to stacked die encapsulation of the present invention.

Fig. 2 to 17 illustrates according to the first embodiment of the present invention, is used to make the method for stacked die encapsulation.

Figure 18 to 23 is according to a second embodiment of the present invention, is used to make the profile of the method for stacked die encapsulation.

Figure 24 to 29 is a third embodiment in accordance with the invention, is used to make the profile of the method for stacked die encapsulation.

Embodiment

Referring now to accompanying drawing the present invention is described more completely, the preferred embodiments of the present invention shown in the drawings.But the present invention can embody with different forms, should not be regarded as being limited to exemplary embodiments set forth herein.In accompanying drawing and associated description, if ground floor be called as another layer " on ", so this ground floor can be directly on another layer, maybe can have insert layer.Same numbers refers to components identical all the time in specification.

Fig. 1 is the profile according to stacked die encapsulation of the present invention.Stacked die encapsulation according to the embodiment of Fig. 1 comprises printed circuit board (PCB) 10, and installation comprises the chip-stack of first chip 21 and second chip 51 it on.Each of first and

second chips

21,51 comprises and is used for transmitting the conductive interconnection 64 of signal to intermediate chip vertical through hole 11 with a plurality of bonding welding pads 53 of chip place-exchange signal in addition with from bonding welding pad.Following chip or the substrate of the tagma that this vertical through hole 11 passes chip in the lamination, their contacts here be the interconnection 64 or the conductive welding disk 125 of chip or substrate down.First chip 21 is comprised that by first insulating barrier first tack coat 123 of photosensitive polymer layer mechanically is bonded to printed circuit board (PCB) 10.Second chip 51 is comprised that by second insulating barrier 122 second tack coat 123 of photosensitive polymer layer mechanically is bonded to first chip 21.The protection encapsulating material 82 of use such as epoxy resin is sealed the multicore sheet encapsulation 100 of gained.Can use chip-scale bonding and wafer scale bonding technology to make as the embodiments of the invention that Fig. 1 described.

Fig. 2 to 17 illustrates according to the first embodiment of the present invention, is used to make the method for stacked die encapsulation.In first embodiment, adopt the chip-scale bonding technology.

With reference to figure 2, wafer 50 is included in a plurality of semiconductor chips 51 that form on the wafer substrates 52, and chip 51 is limited between the scribe line 56 of wafer 50.By cutting them along scribe line 56, chip 51 is divided into tube core.

With reference to figure 3, each semiconductor chip 51 typically is included in a plurality of bonding welding pads 53 around chip 51 peripheries, contiguous scribe line 56.Bonding welding pad 53 is used to transmit a signal to chip 51 position and the position beyond chip 51 in addition and sends signal.

Fig. 4 A-4H is the profile of two adjacent chips 51 in the zone of scribe line 56, and for example, the hatching I-I along Fig. 3 illustrates the formation according to perpendicular interconnection through hole of the present invention and horizontal conductive interconnection.With reference to figure 4A, each chip 51 is included in the substrate 52 semiconductor device that forms, and each chip comprises a plurality of bonding welding pads 53 or interconnect pad, is used for external signal communication.On the top surface of the substrate 52 that comprises semiconductor device, dielectric layer 54 is set.

With reference to figure 4B, in scribe line 56, form a plurality of through holes 13, for example, use bore process, laser drilling process or plasma etch process.Through hole 13 each substrate 52 that partly pass in the lump corresponding to bonding welding pad 53 form.With reference to figure 4C, on the resulting structures that comprises through hole 13, form separator 61, to cover the madial wall and the bottom of through hole 13.With reference to figure 4D, the composition separator 61 then, to expose bonding welding pad 53.With reference to figure 4E, form barrier metal layer 63 and the bonding welding pad 53 under the contact on the separator 61 in through hole 13 and on the substrate 52.In various embodiments, barrier metal layer 63 comprises stacked metal structure, and for example, Ti/Cu, Ti/TiN/Cu, Ta/Cu, Ta/TaN/Cu and Ti/Au/Cu's is at least a.With reference to figure 4F, form photoresist layer 57 and composition, with the barrier metal layer 63 between the bottom of exposing the point that contacts with beneath bonding welding pad 53 and through hole 13.With reference to figure 4G, fill zone between the photoresist layer figure 57 that comprises through hole 13 with metal level 64 then, as electro-coppering or gold, to be formed on the rearrangement line that extends in the perpendicular interconnection through hole 11 that extends on the vertical direction in the through hole 13 and the horizontal direction between perpendicular interconnection through hole 11 and bonding welding pad 53.Being combined in this and jointly being called metal interconnected 64 of perpendicular interconnection through hole 11 and horizontal rearrangement line.Metal interconnected 64 each along extending on the horizontal direction of horizontal component, from with device region the contact point of corresponding bonding welding pad 53 enter in the drawn area 56, and along extending on the vertical direction of vertical component, from horizontal component and enter the through hole 13, the vertical component that through hole 13 is interconnected is filled, to form perpendicular interconnection through hole 11 therein.Selectable conductive layer 65 is applied to the top surface of the metal level 64 of interconnection, to promote the adhesion in the follow-up bond sequence.Conductive layer 65 comprises that for example, low-melting-point metal is as scolder that uses the electroplating technology coating or metal such as Ni, NiV, Cr and the Pd that promotes adhesion.

With reference to figure 5, use the photoresist of standard to remove technology then, peel off and be used for limiting metal interconnected 64 photoresist figure 57.Although, having illustrated among Fig. 5 and in the drawn area 56 of device, formed through hole 11, this through hole can optionally be formed in the device region 27 of device.

With reference to figure 6, the exposed portions serve of the barrier metal layer 63 of wafer 50 is removed, and for example, uses the etching technique of standard.This step is isolated the vertical through hole 11 on the interconnection 64 and the opposite side of scribe line 56.

With reference to figure 7, temporary adhesive 121 is applied to the top surface of resulting structures, and supporting bracket 120 is applied to the top surface of temporary adhesive 121.In subsequent wafer attenuate operation process, supporting bracket 120 keeps the mechanical stability of chip architecture, and prevents the wafer grinding operation warpage of wafer 50 afterwards.Supporting bracket 120 can be used glass and other transparent materials with thermal coefficient of expansion (CTE) that substrate 52 materials with wafer 50 are complementary.The material that can be used for temporary adhesive 121 comprises that especially, spin coating band and ultraviolet light are responsive to be with.

With reference to figure 8, after supporting bracket 120 fixing, the back side 59 or the basal surface of wafer 50 are partly removed, and with thinned wafer, for example use mechanical lapping and/or chemical-mechanical polishing, are exposed up to the bottom of perpendicular interconnection through hole 11.The basal surface 59 of wafer 50 is etched then, for example uses wet etching and/or dry etching, to remove additional substrate material and separator 61 from the bottom of vertical through hole 11.In this way, through hole connects projection 36 and comprises from the basal surface 59 of wafer 50 and extending or the bottom of outstanding vertical through hole 11.

With reference to figure 9, on the basal surface 59 of second wafer 50, form insulating barrier 122.In one embodiment, insulating barrier 122 comprises photopolymerizable material, and this photopolymerizable material comprises thermosetting polymer, comprises photographic composition, plasticizer, crosslinking agent and polymer resin.For example, this photosensitive polymer layer can comprise at least a material that is selected from the group that is made of following composition: polyamide, Ju Ben oxazole (PBO), benzocyclobutene (BCB), epoxy resin, novolaks, melamine-phenol, acrylate and elastomer.

In addition, be that matched coefficients of thermal expansion (CTE-coupling) quality selects insulating barrier 122, preventing subsequent treatment between active stage, wafer 50 arch upward or crooked.For example, the front end of line (FEOL) at the top surface place of dielectric layer 54 and substrate 52 and back end of line (BEOL) composition have higher CTE parameter value, and substrate 52 itself has low CTE value.The insulating barrier 122 of the basal surface 59 by selecting substrate has higher CTE value, and the high CTE value of the composition at top surface place and layer is by layers 122 high CTE value counteracting of basal surface.Therefore, in the latter half of handling, when supporting bracket 120 is removed,, avoid the warpage of wafer 50 by the suitable selection of insulator layer 122.

With reference to Figure 10, insulator layer 122 is patterned, so that first opening 172 of the through hole connection projection (bump) 36 under exposing to be provided.Insulating barrier 122 is exposed at first, cures, development and full solidification.In the step of exposure process, exposure energy is adjusted, so that the segment thickness of remaining insulating barrier 122 in first opening 172, as the basal surface 59 of substrate 50 be layered in the interconnection 64 of following chip, wafer or substrate below this wafer or the insulator between the connection pads afterwards.After partial exposure,, carry out the composition in this operation process by the part photo-mask process.Therefore, the material of remaining insulating barrier 122 in opening is in each side that connects projection 36.

With reference to Figure 11, insulating barrier 122 be connected projection 36 on tack coat 123 is set.Tack coat 123 comprises, for example, and aforesaid photopolymerizable material.In one embodiment, the thickness of insulating barrier 122 is greater than the thickness of tack coat 123.

With reference to Figure 12, photosensitive polymer tack coat 123 is patterned, and so that second opening 174 to be provided, the through hole under this second opening 174 exposes connects the residual insulator material 122 in the projection 36 and first opening 172.After the exposure, carry out composition in this operation process fully by photo-mask process.Photosensitive polymer tack coat 123 so that it has the mechanically stable structure, is still kept its adhesion property by partly solidified simultaneously then.By heating this layer extremely less than the temperature required temperature of this layer of full solidification, photosensitive polymer tack coat 123 is partly solidified and is crosslinked, for example, and β-stage solidification.For example, in one embodiment, solidify photosensitive polymer tack coat 123,, for example be about 33-50% so that solidify percentage less than 100% on ground, a temperature lower part.Under this percentage, the photosensitive polymer tack coat is in the transition state between liquid and the solid, therefore is operating as the mechanically stable structure, and it keeps stable, the processing stage of the next one, and necessary its adhesion property of mechanically link after keeping simultaneously.The selection of photosensitive polymer tack coat mainly is based on the thermal stability of the device on the respective chip.For example, the DRAM device has in the about thermal stability of the 200C order of magnitude, and the desirable photosensitive polymer adhesive layer that therefore is used for this device will have in the about partly solidified temperature of the 150C order of magnitude.Low-temperature curable elastomer, PBO, epoxy resin, acrylate and novolaks material are well suited for the DRAM device application.On the other hand, the NAND flash device has the thermal stability that is about 400C, and the desirable photosensitive polymer tack coat that therefore is used for this device will have the partly solidified temperature that is about 300C.BCB, melamine-phenol and polyamide and above-mentioned low-temperature curable polymer are well suited for the NAND flash device and use.Photosensitive polymer tack coat 123 can comprise identical or different materials with beneath insulating barrier 122, depends on this application.

With reference to Figure 13, according to routine techniques, along its scribe line 56 cuttings 57 wafers 50 between adjacent interconnection 64 and the through-hole interconnection 11.In this way, wafer 50 is divided into chip 51.

With reference to Figure 14, remove supporting bracket 120 and adhesive 121 from the top surface of chip 51, for example use heat treatment or ultraviolet irradiation, to weaken the adhesion property of tack coat 121.This separates the chip 51 that separates with supporting bracket 120.

To be similar to, can form and cut other chips from another public wafer from the mode of 50 formation of public wafer and diced chip 51.For the remainder of this argumentation, this other chips are called first chip 21, and it is formed and cut by the first public wafer 20, and chip 51 is called as second chip 51, and it is formed and cut by the second public wafer 50.

With reference to Figure 15, the basal surface of first chip 21 that separates is applied to top surface or other package substrate of printed circuit board (PCB) 10.Printed circuit board (PCB) 10 comprises a plurality of chip bond pads 14 or connection pads, with the interconnect location that acts on the conductive path on the printed circuit board (PCB) 10.Bonding welding pad 14 is included in the optional conductive welding disk 125 on its upper surface.Conductive welding disk 125 comprises that for example, the low melting point electric conducting material is as scolder that uses the electroplating technology coating or electric conducting material such as Ni, NiV, Cr and the Pd that promotes bonding.Second opening 174 on the downside of first chip 21 is corresponding to the chip bond pads 14 of printed circuit board (PCB) 10 and the shape and size of chip conductive welding disk 125.Connection projection 36 in second opening 174 is aimed at and is bonded with chip bond pads 14.On printed circuit board (PCB) 10 in the process of stacked first chip 21, photosensitive polymer tack coat 123 complete filling, first chip 21 of first chip 21 and gap or the space between the printed circuit board (PCB) 10.In addition, the sclerosis insulating barrier 122 of first chip 21 prevents that the chip bond pads 14 of printed circuit board (PCB) 10 from contacting the substrate 22 of first chip 21 with conductive welding disk 125.

Can optionally carry out the thermocompression bonding operation this moment, so that obtain full solidification, therefore the photosensitive polymer tack coat 123 between first chip 21 and the printed circuit board (PCB) 10 all bonds.Simultaneously, because hot pressing process, between the chip bond pads 14 of the connection projection of first chip 21 with conductive welding disk 125 and printed circuit board (PCB) 10 telegraph key takes place and close.In order to carry out thermocompression bonding, in stepped construction, after stacked wafer or the chip, this structure is installed, and this bonder is heated to predetermined bonding peak temperature on the bonder chuck.When arriving predetermined temperature, under the pressure of the compression stress of piston, this structure is exposed to the heating environment predetermined period of time.This bonding peak temperature and time cycle are decided according to the required state of cure of polymeric layer with according to the hope flow of the compound of conductive layer 65.After the heating period of bond sequence, the pressure of piston is released and this stepped construction is cooled.Before hot pressing process, photosensitive polymer tack coat 123 and adjacent surface comprise dangling bonds.This hot pressing process impels dangling bonds to connect and quickens bond sequence.

With reference to Figure 16, the basal surface of second chip 51 that separates is applied to the top surface of first chip 21.Second opening 174 on the downside of second chip 51 is corresponding to the shape and size of the conductive interconnection of first chip 21, and first chip 21 comprises the conductive layer 65 of barrier metal layer 63, metal interconnecting layer 64 and first chip 21 of composition.Connection projection 36 in second opening 174 of second chip 51 be aligned and with the partially conductive of first chip 21 interconnection bonding.On first chip 21 in the process of stacked second chip 51, photosensitive polymer tack coat 123 complete filling, second chip 51 of second chip 51 and gap or the space between first chip 21.In addition, the sclerosis insulating barrier 122 of second chip 51 prevents the substrate 52 of conductive interconnection 64 contacts second chip 51 of first chip 21.At this moment, can optionally carry out this thermocompression bonding operation, so that obtain full solidification, therefore the photosensitive polymer tack coat 123 between second chip 51 and first chip 21 all bonds.Simultaneously, because telegraph key takes place in hot pressing process between the chip bond pads 14 of the connection projection of second chip 51 with conductive layer 65 and printed circuit board (PCB) 10 close.

Can optionally stacked additional chips on second and

first chip

51,21, and after each chip layer stacked, carry out hot pressing process, with each layer of bonding continuously, as mentioned above.In addition, this hot pressing process can be delayed, and is aligned also stacked up to all chips, and when the chip laminate operation is finished, can carry out single thermocompression bonding operation, so that obtain the full solidification of all photosensitive polymer tack coats 122 of each

chip

21,51 simultaneously.Simultaneously, because hot pressing process, the generation telegraph key closes between connection projection 36 with beneath conductive layer 65 or beneath conductive welding disk 125.

With reference to Figure 17, next, on chip-stack 101, form encapsulating material 82, each lamination 101 comprises first and

second chips

21,51 and printed circuit board (PCB) 10.This encapsulating material comprises, for example, and epoxy molding compound (EMC) or other materials that is fit to.

Although show and described two chips that promptly first and

second chips

21,51 is stacked in conjunction with above example, the present invention can be applied to surpassing the stacked of two chips.In addition, although the chip-stack shown in top is applied to printed circuit board (PCB), other encapsulation matrix can be applicable to the present invention equally, comprise, for example, semiconductor device substrates or encapsulation built-in inserted plate.

Figure 18 to 23 is according to a second embodiment of the present invention, is used to make the profile of the method for stacked die encapsulation.Among first embodiment in the above, between the chip-stack that is used to provide insulation and attachment function, insert the bilayer film that comprises insulating barrier 122 and photosensitive polymer tack coat 123.In second embodiment as described below, use individual layer with insulation and adhesion property.

With reference to Figure 18, prepare wafer 50 in the mode that is similar to top Fig. 4 to 8.Photosensitive polymer layer 129 is operating as insulator, anti-warpage layer, and forms tack coat on the basal surface 59 of second wafer 50.The photosensitive polymer layer material comprises thermosetting polymer, comprises photographic composition and bonding agent, for example, and plasticizer, crosslinking agent and polymer resin.As mentioned above, this photosensitive polymer layer can comprise, for example, be selected from least a material of the group that constitutes by following composition: polyamide, Ju Ben oxazole (PBO), benzocyclobutene (BCB), epoxy resin, novolaks, melamine-phenol, acrylate and elastomer.For matched coefficients of thermal expansion (CTE-coupling) quality, further select photosensitive polymer layer 129, to prevent in the subsequent treatment active procedure that arching upward or bending of wafer 50 prevents the warpage subsequently of aforesaid wafer 50.

With reference to Figure 19, photosensitive polymer layer 129 is patterned, and so that opening 176 to be provided, the beneath through hole that opening 176 exposes in the opening 176 connects projection 36.Photosensitive polymer layer 129 is exposed at first, is cured, is developed and partly solidified, as mentioned above.In the step of exposure process, exposure energy is adjusted, so that the segment thickness of remaining photosensitive polymer layer 129 in first opening 176, as the basal surface 59 of substrate 50 and the interconnection 64 of stacked following chip, wafer or substrate or the photosensitive polymer between the connection pads below this wafer afterwards.Carry out composition in this processing procedure by the part photo-mask process after the partial exposure.By heating this layer extremely less than the temperature required temperature of this layer of full solidification, photosensitive polymer tack coat 129 is partly solidified and is crosslinked, for example, and β-stage solidification, as mentioned above.The partly solidified layer that causes having the mechanically stable structure of photosensitive polymer layer 129 still keeps its adhesion property.

With reference to Figure 20, according to routine techniques, along its scribe line 56 cuttings 57 wafers 50 between adjacent interconnection 64 and the through-hole interconnection 11.In this way, wafer 50 is divided into chip 51.

With reference to Figure 21, remove supporting bracket 120 and adhesive 121 from the top surface of chip 51, for example use heat treatment or ultraviolet irradiation, to weaken the adhesion property of tack coat 121.This separates the chip 51 that separates with supporting bracket.

According to aforesaid second embodiment, form and the mode of diced chip 51 to be similar to by public wafer 50, can form and cut other chips from another public wafer.For the remainder of this argumentation, this other chips are called first chip, formed and cut by public first wafer 20, and chip 51 is called as second chip 51, is formed and is cut by public second wafer 50.

With reference to Figure 22, the basal surface of first chip 21 that separates is applied to top surface or other package substrate of printed circuit board (PCB) 10.Printed circuit board (PCB) 10 comprises a plurality of chip bond pads 14 or connection pads, with the interconnect location that acts on the conductive path on the printed circuit board (PCB) 10.Bonding welding pad 14 comprises the optional conductive welding disk 125 on its upper surface.Conductive welding disk 125 comprises that for example, low melting material is as scolder that uses the electroplating technology coating or material such as Ni, NiV, Cr and the Pd that promotes bonding.Second opening 176 on the downside of first chip 21 is corresponding to the chip bond pads 14 of printed circuit board (PCB) 10 and the shape and size of chip conductive welding disk 125.Connection projection 36 in second opening 176 is aimed at and is bonded with chip bond pads 14.On printed circuit board (PCB) 10 in the process of stacked first chip 21, photosensitive polymer layer 129 complete filling, first chip 21 of first chip 21 and gap or the space between the printed circuit board (PCB) 10.In addition, the photosensitive polymer layer 129 of first chip 21 prevents that the chip bond pads 14 of printed circuit board (PCB) 10 from contacting the substrate 22 of first chip 21 with conductive welding disk 125.Can optionally carry out the thermocompression bonding operation this moment, so that obtain the full solidification of the photosensitive polymer layer 129 between first chip 21 and the printed circuit board (PCB) 10.Simultaneously, because hot pressing process, between the chip bond pads 14 of the connection projection of first chip 21 with conductive welding disk 125 and printed circuit board (PCB) 10 telegraph key takes place and close.

With reference to Figure 23, the basal surface of second chip 51 that separates is applied to the top surface of first chip 21.Second opening 176 on the downside of second chip 51 is corresponding to the shape and size of the conductive interconnection of first chip 21, and first chip 21 comprises the conductive layer 65 of barrier metal layer 63, metal interconnecting layer 64 and first chip 21 of composition.Connection projection 36 in second opening 176 of second chip 51 is aimed at the interconnection of the partially conductive of first chip 21 and is bonded together.On first chip 21 in the process of stacked second chip 51, photosensitive polymer layer 129 complete filling, second chip 51 of second chip 51 and gap or the space between first chip 21, simultaneously, prevent that the conductive interconnection of first chip 21 from contacting the substrate 52 of second chip 51.At this moment, can optionally carry out the thermocompression bonding operation, so that between second chip 51 and first chip 21, obtain the full solidification of photosensitive polymer layer 123.Simultaneously, because hot pressing process, between the chip bond pads 14 of the connection projection of second chip 51 with conductive layer 65 and printed circuit board (PCB) 10 telegraph key takes place and close.

Can optionally stacked additional chips on second and

first chip

51,21, and after stacked each chip layer, carry out hot pressing process, as mentioned above.In addition, this hot pressing process can be delayed, and is aligned also stacked up to all chips, and when the chip laminate operation is finished, can carry out single thermocompression bonding operation, so that obtain the full solidification of all photosensitive polymer tack coats 122 of each

chip

As mentioned above, the further processing of gained chip-stack 101 comprises, forms encapsulating material 82 on chip-stack 101.In addition, as mentioned above, although show and described the stacked of two chips in conjunction with above example, i.e. first and

second chips

21,51, the present invention can be applied to surpassing the stacked of two chips.In addition, although the chip laminate shown in top is applied to printed circuit board (PCB), other encapsulation matrix can be applicable to the present invention equally, comprise, for example, semiconductor device substrates or encapsulation built-in inserted plate.

Among superincumbent first and second embodiment, on substrate, aim at respectively and the stacked chip that separates, form the chip laminate encapsulation in the mode consistent with the chip-scale bonding structure.In the 3rd following embodiment, before the mode diced chip consistent, comprise the entire wafer of a plurality of chips or comprise that the fragment of this wafer of a plurality of chips is aligned with stacked, and be applied to substrate with the wafer scale bonding structure.

With reference to Figure 24, prepare second wafer 50 in the mode that is similar to top Fig. 4 to 12, comprise the insulator layer 122 of composition and the tack coat 123 of composition, this tack coat comprises, for example, aforesaid photopolymerizable material.Photosensitive polymer tack coat 123 is partly solidified, as mentioned above.

With reference to Figure 25, comprise that second wafer 50 of supporting bracket 120 and first wafer 20 are stacked.Method with aforesaid Fig. 4 to 6 prepares first wafer 20.The basal surface that comprises second wafer 50 of a plurality of second chips 51 is applied to comprising the top surface of first wafer 20 of a plurality of first chips 21.Second opening 174 on second chip, 51 downsides of second wafer 50 comprises barrier metal layer 63, metal interconnecting layer 64 and the conductive layer 65 of the composition of first wafer 20 corresponding to the shape and size of the conductive interconnection of first chip 21 of first wafer 20.Connection projection 36 in second opening 174 of second wafer 50 is aimed at and bonding with the interconnection of the partially conductive of first wafer 20.On first wafer 20 in the process of stacked second wafer 50, gap or space between second chip 51 of photosensitive polymer tack coat 123 complete filling second wafer 50 of second wafer 50 and first chip 21 of first wafer 20.In addition, the sclerosis insulating barrier 122 of second chip 51 of second wafer 50 prevents that the conductive interconnection 64 of first chip 21 of first wafer 20 from contacting the substrate 52 of second chip 51 of second wafer.Can optionally carry out the thermocompression bonding operation this moment, so that obtain the full solidification of photosensitive polymer tack coat 123 between second wafer 50 and first wafer 20, therefore obtains the bonding fully of wafer 20,50.Simultaneously, because this hot pressing process, between the conductive interconnection 64 of first chip 21 of the connection projection 36 of second chip 51 of second wafer 50 with conductive layer 65 and first wafer 20 telegraph key takes place and close.

Can optionally stacked additional wafers on second and

first wafer

50,20, and after stacked each wafer, carry out hot pressing process, as mentioned above.In addition, this hot pressing process can be delayed, and is aligned also stacked up to all wafers, and when the stack of wafers operation is finished, can carry out single thermocompression bonding operation, so that obtain the full solidification of all photosensitive polymer tack coats 123 of each

wafer

20,50 simultaneously.Simultaneously, because this hot pressing process, the generation telegraph key closes between connection projection 36 with beneath conductive layer 65 or beneath conductive welding disk 125.

With reference to Figure 26, the basal surface of first wafer 50 is thinned and etching, as mentioned above, so that through hole connects projection 36 from basal surface extension or outstanding.Then with the method formation identical and the photosensitive polymer tack coat 123 of composition insulating barrier 122 and β-stage solidification with aforesaid Fig. 9 to 12.

With reference to Figure 27,, cut the 57 first and second

stacked wafers

20,50 along their scribe lines between adjacent interconnection 64 and the through-hole interconnection 11 56 according to routine techniques.In this way, this wafer 50 is divided into chip-stack, and each lamination comprises first chip 21 of first wafer 20 and second chip 51 of second wafer 50.

In the present embodiment of Miao Shuing, in lamination process, keep supporting bracket 120 on second wafer 50 here, be used for stacked additional wafers below second wafer 50, this supporting bracket is removed then.In the embodiment that replaces, first wafer 20 can keep the main body of its basic substrate 22 and the top surface that second wafer 50 could be employed and be bonded to first wafer 20.The supporting bracket of second wafer is removed then, and the 3rd wafer and optional subsequent wafer with supporting bracket are employed and are bonded to the top surface of second wafer 50.The supporting bracket of the 3rd wafer is removed then.

With reference to Figure 28, remove supporting bracket 120 and tack coat 128 from the top surface of second chip 51 of chip-stack 151, for example use heat treatment or ultraviolet irradiation, to weaken the adhesion property of tack coat 128.This separates the chip 51 that separates with supporting bracket 120.

With reference to Figure 29, chip-stack 151 is aligned and is bonded to package substrate then, for example, and printed circuit board (PCB) 10.The basal surface of first chip 21 of chip-stack 151 is applied to top surface or other package substrate of printed circuit board (PCB) 10.As mentioned above, printed circuit board (PCB) 10 comprises a plurality of chip bond pads 14 or connection pads, with the interconnect location that acts on the conductive path on the printed circuit board (PCB) 10.Bonding welding pad 14 comprises the optional conductive welding disk 125 on its upper surface.Conductive welding disk 125 comprises, for example, uses the low-melting-point metal or the flux material of electroplating technology coating.Second opening 174 on the downside of first chip 21 of chip-stack 151 is corresponding to the chip bond pads 14 of printed circuit board (PCB) 10 and the shape and size of chip conductive welding disk 125.Connection projection 36 in second opening 174 is aimed at and is bonded with chip bond pads 14.On printed circuit board (PCB) 10 in the process of first chip 21 of stacked chip-stack 151, photosensitive polymer tack coat 123 complete filling, first chip 21 of first chip 21 and gap or the space between the printed circuit board (PCB) 10.In addition, the sclerosis insulating barrier 122 of first chip 21 prevents that the chip bond pads 14 of printed circuit board (PCB) 10 from contacting the substrate 22 of first chip 21 with conductive welding disk 125.Can optionally carry out the thermocompression bonding operation this moment, so that obtain full solidification, so first chip 21 of chip-stack 151 and the photosensitive polymer tack coat 123 between the printed circuit board (PCB) 10 all bond.Simultaneously, because this hot pressing process, between the chip bond pads 14 of the connection projection of the chip-stack 151 with conductive welding disk 125 and printed circuit board (PCB) 10 telegraph key takes place and close.

In the further processing of this chip-stack, can on aforesaid chip-stack, provide encapsulating material 82.

Among described in the above the 3rd embodiment, when each layer is used, the complete stacked wafer of bonding.In embodiment optionally, can in public hot pressing process, solidify simultaneously and bonding comprises a plurality of wafer layer of β-stage tack coat.

In aforesaid the 3rd embodiment, utilize and wherein before the cutting of chip-stack, at first aim at the also wafer scale bonding method of a plurality of wafers of bonding.In the 3rd embodiment, between the wafer that is used for providing between the chip layer insulation and adhesion function, insert the bilayer film that comprises insulating barrier 122 and photosensitive polymer tack coat 123.In optional the 4th embodiment, the single photosensitive polymer layer with adhesion and insulation property is used to provide the wafer scale bonding.Use individual layer 129 in the mode that is similar to the described operation of top Figure 18-23, combine with the aforesaid wafer scale bonding method of Figure 24 to 29.

In this way, the invention provides and be used for chip stacked structure and manufacture method thereof, wherein use the gap between the chip and last chip under the relative simple technology complete filling, eliminate the space between the lower and upper chip and eliminate the fracture relevant and peel off problem with the space.The present invention can be applied to chip-scale and wafer scale bonding method.Before stacked die or stacked wafer, photosensitive polymer layer is applied to first chip or wafer.This photosensitive polymer layer is partly solidified, so that make the Stability Analysis of Structures of photosensitive polymer layer, keeps its adhesion property simultaneously.Second chip or wafer be stacked, aim at and be bonded to first chip or wafer, and photosensitive polymer layer is cured then, with complete bonding first and second chips or wafer.In this way, the adhesion between the die/wafer is improved widely, and the complete filling in gap is provided simultaneously.In addition, Mechanical Reliability is enhanced not match with CTE and is reduced, and alleviates with warpage, ruptures and peel off relevant problem, thereby improve device yield and device reliability.

Although specifically showed and described the present invention with reference to its preferred embodiment, but those of ordinary skill in the art is understood that, under the condition of the spirit and scope of the present invention that do not break away from accessory claim and limited, can carry out various changes in the form and details.

Claims

1. method of making semiconductor device comprises:

Form first semiconductor device on first substrate, this first semiconductor device is included in first bonding welding pad on the first surface of first substrate in the device region of first semiconductor device;

On the first surface of first substrate, form first interconnection, this first interconnection is electrically coupled to first bonding welding pad, and form the conductive through hole that passes first substrate, and this conductive through hole is electrically coupled to first interconnection and runs through the second surface of first substrate, and this second surface is relative with first surface;

Form second semiconductor device on second substrate, this second semiconductor device is included in second bonding welding pad on the first surface of second substrate in the device region of second semiconductor device;

Form second interconnection on the first surface of second substrate, this second interconnection is electrically coupled to second bonding welding pad;

On the second surface of first substrate, provide photosensitive polymer layer, by this photosensitive polymer layer exposed portions serve conductive through hole; And

To comprise that the second surface of first substrate of photosensitive polymer layer is applied to the first surface of second substrate, and second interconnection of second substrate will be aimed at the exposed portions serve of conductive through hole, so that first bonding welding pad is electrically coupled to second bonding welding pad.

2. according to the process of claim 1 wherein that photosensitive polymer layer is set also to be comprised, this photosensitive polymer layer of composition is with the exposed portions serve conductive through hole.

3. according to the method for claim 1, wherein this first is interconnected on the direction of the outer rim of first substrate, the first surface that crosses first substrate extends, and wherein this second is interconnected on the direction of the outer rim of second substrate, and the first surface that crosses second substrate extends.

4. in the scribe area of first semiconductor device, form conductive through hole according to the process of claim 1 wherein.

5. in the device region of first semiconductor device, form this conductive through hole according to the process of claim 1 wherein.

6. according to the method for claim 1, also comprise, before first substrate being used and be registered to second substrate, partly solidify photosensitive polymer layer.

7. according to the method for claim 6, also comprise, after first substrate being used and be registered to second substrate, solidify this photosensitive polymer layer.

8. according to the process of claim 1 wherein that this photosensitive polymer layer comprises the photosensitive polymer layer of insulation, and this photosensitive polymer layer wherein be set on the second surface of first substrate comprise:

Remove backing material from the second surface of first substrate, to expose the lower end of conductive through hole;

The insulation photosensitive polymer layer is set on the second surface of first substrate;

Composition is somebody's turn to do the insulation photosensitive polymer layer, with lower end of exposing conductive through hole and the lower sidewall portion that covers conductive through hole; And

Solidify this insulation photosensitive polymer layer.

9. method according to Claim 8 also comprises:

This insulation photosensitive polymer layer is provided with the photosensitive polymer layer of viscosity;

Before first substrate being used and be registered to second substrate, partly solidify this sticking photosensitive polymer layer; And

After first substrate being used and be registered to second substrate, solidify this sticking photosensitive polymer layer.

10. according to the method for claim 9, also comprise this sticking photosensitive polymer layer of composition, to expose the lower end of conductive through hole.

11., also comprise the upper surface that this conductive layer is applied to second interconnection according to the method for claim 1.

12. according to the process of claim 1 wherein that forming the conductive through hole that passes first substrate comprises:

Form through hole in first substrate, this through hole runs through the first surface of first substrate and partly enters first substrate;

The insulating barrier of the sidewall of liner through hole is set;

Fill this through hole with electric conducting material, to form conductive through hole; And

Remove backing material from the second surface of first substrate, to expose the lower end of conductive through hole.

13., wherein remove backing material and comprise according to the method for claim 12:

Grind the second surface of first substrate, to remove backing material; And

The second surface and the partial insulative layer of etching first substrate are with the lower end of exposing conductive through hole and the lower sidewall of conductive through hole lower end.

14. forming first semiconductor device on first substrate and second semiconductor device on second substrate on the public semiconductor wafer according to the process of claim 1 wherein.

15. forming first semiconductor device on first substrate and second semiconductor device on second substrate on first and second semiconductor wafers that separate according to the process of claim 1 wherein.

16. according to the process of claim 1 wherein that this conductive through hole comprises first conductive through hole, and wherein this photosensitive polymer layer comprises first photosensitive polymer layer, and also comprises:

Second conductive through hole of second substrate is passed in formation, and this second conductive through hole is electrically coupled to second interconnection and runs through the second surface of second substrate, and this second surface is relative with first surface;

Second photosensitive polymer is set, by this second photosensitive polymer layer exposed portions serve, second conductive through hole on the second surface of second substrate;

On the first surface of the 3rd substrate, form the 3rd substrate that comprises the 3rd bonding pad;

To comprise that the second surface of second substrate of second photosensitive polymer layer is applied to the first surface of the 3rd substrate, and the 3rd bonding pad of the 3rd substrate aimed at the exposed portions serve of second conductive through hole, second bonding welding pad is electrically coupled to the 3rd bonding pad.

17., second photosensitive polymer layer wherein is set also comprises this second photosensitive polymer layer of composition, with exposed portions serve second conductive through hole according to the method for claim 16.

18. according to the method for claim 16, wherein the 3rd substrate comprises the substrate that is selected from the group that is made of printed circuit board (PCB) (PCB), semiconductor device substrates and encapsulation built-in inserted plate.

19. the method according to claim 16 also comprises:

Before first substrate being used and be registered to second substrate, partly solidify this first photosensitive polymer layer;

Before second substrate being used and be registered to the 3rd substrate, partly solidify this second photosensitive polymer layer; And

With first substrate is applied to and aims at second substrate after and after second substrate being used and is registered to the 3rd substrate, solidify this first and second photosensitive polymer layer simultaneously.

20. according to the method for claim 16, wherein this second photosensitive polymer layer comprises second photosensitive polymer layer of insulation, and second photosensitive polymer layer wherein is set on the second surface of second substrate comprises:

Remove backing material from the second surface of second substrate, to expose the lower end of second conductive through hole;

Insulation second photosensitive polymer layer is set on the second surface of second substrate,

Composition is somebody's turn to do insulation second photosensitive polymer layer, with lower end of exposing second conductive through hole and the lower sidewall portion that covers second conductive through hole; And

Solidify this second photosensitive polymer layer that insulate.

21. the method according to claim 20 also comprises:

This second photosensitive polymer layer that insulate is provided with second photosensitive polymer layer of viscosity;

Before second substrate being used and be registered to the 3rd substrate, partly solidify this sticking second photosensitive polymer layer; And

After second substrate is applied to and aims at the 3rd substrate, solidify this sticking second photosensitive polymer layer.

22., also comprise this sticking second photosensitive polymer layer of composition, to expose the lower end of second conductive through hole according to the method for claim 21.

23. method according to claim 1, wherein be included in and form a plurality of first semiconductor device on the public wafer at formation first semiconductor device on first substrate, each of these a plurality of first semiconductor device has corresponding first interconnection and corresponding conductive through hole, and also comprise these a plurality of first semiconductor device of scribing, with before one of will these a plurality of first substrates using and be registered to each of second substrate, should separate by a plurality of first semiconductor device.

24. method according to claim 23, wherein form this second semiconductor device and be included in a plurality of second semiconductor device of formation on the public wafer, each of these a plurality of second semiconductor device has corresponding second interconnection, and also be included in one of a plurality of second substrates are used and are registered to before each first substrate, these a plurality of second semiconductor device of scribing are separating by a plurality of second semiconductor device.

25., wherein before these a plurality of second semiconductor device of scribing, carry out and on the first surface of second substrate, photosensitive polymer layer be set according to the method for claim 24.

26. according to the method for claim 25, also be included in second substrate used and is registered to before first substrate, partly solidify this photosensitive polymer layer.

27. according to the method for claim 26, also be included in second substrate be applied to and be registered to after first substrate, solidify this photosensitive polymer layer.

28. method according to claim 1, wherein forming first semiconductor device on first substrate comprises, on the first public wafer, form a plurality of first semiconductor device, each of these a plurality of first semiconductor device has corresponding first interconnection and corresponding conductive through hole, and wherein form second semiconductor device and comprise, on the second public wafer, form a plurality of second semiconductor device, each of these a plurality of second semiconductor device has corresponding second interconnection, and wherein second substrate is used and is registered to first substrate and comprise, a plurality of first semiconductor device on first wafer are used and be registered to a plurality of second semiconductor device on second wafer simultaneously.

29. method according to claim 28, also comprise, after a plurality of first semiconductor device of a plurality of second semiconductor device on second wafer being used simultaneously and are registered on first wafer, this first and second wafer of scribing is separating by a plurality of corresponding first and second semiconductor device.

30., wherein before scribing first and second wafers, carry out and on the first surface of second substrate, photosensitive polymer layer be set according to the method for claim 29.

31. according to the method for claim 30, also be included in a plurality of second semiconductor device application of second wafer and aim at before a plurality of first semiconductor device of second wafer of first wafer, partly solidify this photosensitive polymer layer.

32. according to the method for claim 31, also be included in a plurality of second semiconductor device application of second wafer and be registered to after a plurality of first semiconductor device of second wafer of first wafer, partly solidify this photosensitive polymer layer.

33. according to the process of claim 1 wherein that this photosensitive polymer layer is the material that is selected from the group that is made of following composition: polyamide, Ju Ben oxazole (PBO), benzocyclobutene (BCB), epoxy resin, novolaks, melamine-phenol, acrylate and elastomer.

34. according to the process of claim 1 wherein that this photosensitive polymer layer comprises photosensitive composition and bonding agent.

35. according to the process of claim 1 wherein that this photosensitive polymer layer has first thermal coefficient of expansion, it is higher than second thermal coefficient of expansion of substrate.

36. method according to claim 35, wherein be higher than the active device that first thermal coefficient of expansion compensation of this photosensitive polymer layer of second thermal coefficient of expansion of substrate forms on the top of substrate, the top of substrate is relative with the photosensitive polymer layer with the 3rd thermal coefficient of expansion, the 3rd thermal coefficient of expansion is higher than second thermal coefficient of expansion of substrate, with semiconductor device warpage in the subsequent thermal cyclic process that prevents semiconductor device.

37. a semiconductor device comprises:

First semiconductor device on first substrate, this first semiconductor device are included in first bonding welding pad on the first surface of first substrate in the device region of first semiconductor device;

Form first interconnection on the first surface of first substrate, this first interconnection is electrically coupled to first bonding welding pad;

Pass first conductive through hole of first substrate, this conductive through hole is electrically coupled to first interconnection and runs through the second surface of first substrate, and this second surface is relative with first surface;

Second substrate comprises second bonding welding pad on the first surface of second substrate; And

First photosensitive polymer layer between the first surface of the second surface of first substrate and second substrate, these first photosensitive polymer layer bonding, first and second substrates, at least one of this second bonding welding pad and first conductive through hole runs through first photosensitive polymer layer extends and contacts another of second bonding welding pad and this first conductive through hole, so that first bonding welding pad is electrically coupled to second bonding welding pad.

38. according to the device of claim 37, also be included in the second surface of first substrate and first insulating barrier between first photosensitive polymer layer, this first conductive through hole runs through first insulating barrier, to contact second bonding welding pad of second substrate.

39. according to the device of claim 38, wherein this first insulating barrier covers the sidewall of the bottom of first conductive through hole.

40. the device according to claim 37 also comprises:

Second semiconductor device on the 3rd substrate, this second semiconductor device are included in the 3rd bonding pad on the first surface of the 3rd substrate in the device region of second semiconductor device;

On the first surface of the 3rd substrate second interconnection, this second interconnection is electrically coupled to the 3rd bonding pad;

Pass second conductive through hole of the 3rd substrate, this second conductive through hole is electrically coupled to second interconnection and runs through the second surface extension of the 3rd substrate, and this second surface is relative with first surface; And

Second photosensitive polymer layer between the first surface of the second surface of the 3rd substrate and first substrate, this the second photosensitive polymer layer bonding the 3rd and first substrate, at least one of first bonding welding pad and second conductive through hole runs through this second photosensitive polymer layer extends and contacts another of first bonding welding pad and second conductive through hole, first bonding welding pad is electrically coupled to the 3rd bonding pad.

41. device according to claim 40, also comprise the second surface of first substrate and first insulating barrier between first photosensitive polymer layer, first conductive through hole runs through this first insulating barrier and extends, to contact second bonding welding pad of second substrate, and second insulating barrier between the second surface of the 3rd substrate and second photosensitive polymer layer, second conductive through hole runs through this second insulating barrier, to contact first bonding welding pad of first substrate.

42. according to the device of claim 41, wherein this first insulating barrier covers the sidewall of the bottom of first conductive through hole, and wherein second insulating barrier covers the sidewall of the bottom of second conductive through hole.

43. device according to claim 40, wherein this first photosensitive polymer layer is patterned, with exposed portions serve first conductive through hole, contacting with second bonding welding pad, and wherein this second photosensitive polymer layer is patterned, with exposed portions serve second conductive through hole, contacting with first bonding welding pad.

44. device according to claim 40, wherein first be interconnected on the direction of the outer rim of first substrate, the first surface that crosses first substrate extends, and wherein second is interconnected on the direction of the outer rim of the 3rd substrate, and the first surface that crosses the 3rd substrate extends.

45. according to the device of claim 40, wherein this first and second conductive through hole is positioned in the drawn area of first and second semiconductor device separately.

46. according to the device of claim 40, wherein this first and second conductive through hole is positioned in the device region of first and second semiconductor device separately.

47. according to the device of claim 40, wherein the far-end of each first and second conductive through hole and segment distal sidewall exceed the second surface extension of first substrate and second substrate respectively.

48., wherein forming first semiconductor device on first substrate and second semiconductor device on the 3rd substrate on the public semiconductor wafer according to the device of claim 40.

49., wherein forming first semiconductor device on first substrate and second semiconductor device on the 3rd substrate on first and second semiconductor wafers that separate according to the device of claim 37.

50., also comprise the conductive layer on first upper surface that interconnects according to the device of claim 37.

51. according to the device of claim 37, wherein this second substrate comprises the substrate that is selected from the group that is made of printed circuit board (PCB) (PCB), semiconductor device substrates and encapsulation built-in inserted plate.

52. according to the device of claim 37, wherein this first photosensitive polymer layer is the material that is selected from the group that is made of following composition: polyamide, Ju Ben oxazole (PBO), benzocyclobutene (BCB), epoxy resin, novolaks and elastomer.

53. according to the device of claim 37, wherein this first photosensitive polymer layer has first thermal coefficient of expansion, it is higher than second thermal coefficient of expansion of first substrate.

54. device according to claim 53, wherein be higher than the active device that first thermal coefficient of expansion compensation of this first photosensitive polymer layer of second thermal coefficient of expansion of first substrate forms on the top of first substrate, the top of first substrate is relative with first photosensitive polymer layer with the 3rd thermal coefficient of expansion, the 3rd thermal coefficient of expansion is higher than second thermal coefficient of expansion of first substrate, with semiconductor device warpage in the subsequent thermal cyclic process that prevents semiconductor device.