KR20050073040A - Method for forming capacitor of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a capacitor of a semiconductor device. The disclosed method includes providing a semiconductor substrate having an interlayer insulating film having a plug, forming an etch stop layer and a first dilution film on the interlayer insulating film, and forming the first dilution film and the etch stop layer. Forming a first trench to expose the plug by etching, forming a first electrode layer in contact with the plug in the first trench, and a second sacrificial layer on the remaining first dilution film including the first electrode layer Forming an oxide film, forming a second trench that exposes the first electrode layer by etching the second rare metallization film, and forming a second electrode layer in contact with the first electrode layer on the surface of the second trench Forming a lower electrode composed of first and second electrode layers, removing the second and first rarely produced films, and then dielectric and upper electrodes on the lower electrode. And forming. According to the present invention, the first electrode layer is formed in advance in the region where the lower electrode is to be formed, and the cylindrical second electrode layer is formed on the first electrode layer, so that the first electrode layer supports the second electrode layer and the predetermined height is increased. Instead, the lower electrode may be prevented from falling down during the wet etching of the sacrificial oxide film.

Description

Method for forming capacitor of semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a capacitor of a semiconductor device.

DRAM is because stored data is not directly connected to a power source. It needs refresh every certain time. In addition, since the stored data has to be maintained for a long time, the larger the charging capacity of the capacitor is advantageous.

However, as the integration of semiconductor devices proceeds, the cell size is reduced, and the decrease in the cell size entails the reduction of the capacitor area, and the reduction of the capacitor area leads to the reduction of the charging capacity. It is difficult to secure the charging capacity required to keep the device operating characteristics constant.

In order to secure a certain amount of charge capacity required for cell operation, high-integration devices currently in mass production include forming charge storage electrodes in various three-dimensional structures, using high-k dielectric materials as the dielectric film, or making the dielectric film as thin as possible. To form.

This is based on the charge capacity of the capacitor being proportional to the electrode surface area and the dielectric constant of the dielectric film and inversely proportional to the gap between the upper and lower electrodes, i.

In detail, the first method is to reduce the thickness of the dielectric film to reduce the gap between the upper electrode and the lower electrode in order to secure the charging capacity. For example, the ONO film (oxide film / nitride film / oxide film) of the thin film is intended to increase the charging capacity by reducing the thickness of the dielectric film. However, this method has a limitation in reducing the thickness due to high integration since the direct tunneling phenomenon occurs at the dielectric of 30 Å or less, thereby greatly deteriorating the characteristics of the device.

Second, there is a method of increasing the capacity by using a material having a high dielectric constant as a dielectric film. For example, dielectric films such as Ta2O2, TaON, and Al2O3 are for increasing charge capacity using high dielectric constant materials.

Third, there is a method of increasing the surface area of the lower electrode. For example, the lower electrode of the three-dimensional structure such as the cylinder, concave, and pin structures is intended to increase the charge capacity by expanding the electrode surface area. will be.

In order to further expand the surface area of the capacitor type capacitor, the full cylinder type electrode which utilizes both inside and outside of the cylinder as a charge storage electrode has recently been developed.

1A to 1D are cross-sectional views of processes for describing a method of forming a semiconductor device according to the related art.

Referring to FIG. 1A, a semiconductor substrate 11 having an interlayer insulating film 12 having a plug 13 is provided.

Subsequently, a sacrificial oxide layer 14 is formed on the interlayer insulating layer 12, and a portion of the sacrificial oxide layer 14 is etched to form a trench 15 that exposes the plug 13.

Next, a lower electrode material 16 is formed on the surface of the trench 15 and the sacrificial oxide layer 14.

Referring to FIG. 1B, a resist 17 is coated on the lower electrode material 16 to fill the trench 15.

Referring to FIG. 1C, the lower electrode material 16 on the resist 17 and the sacrificial oxide layer 14 is removed by CMP and etch back to electrically isolate the neighboring lower electrode 16. The lower electrode 16a is formed.

Referring to FIG. 1D, the resist remaining after the etch back process is removed through a strip process, and then the sacrificial oxide film is removed.

Subsequently, although not shown, hemispherical silicon is grown on the lower electrode surface, and then a dielectric film and an upper electrode are sequentially formed on the lower electrode on which the hemispherical polysilicon is formed to form a capacitor.

However, in the method of forming a capacitor according to the prior art, the line width also decreases according to the size of the device, so that the tension caused by the etching solution or the cleaning solution is generated at the bottom of the lower electrode in the process of removing the sacrificial oxide film by wet etching. As a result, the lower electrode may be inclined or collapsed and, in severe cases, the lower electrode may be pulled out, which may cause a problem of causing electrical disconnection between the two electrodes.

Accordingly, the present invention has been made to solve the conventional problems as described above, and provides a method for forming a capacitor of a semiconductor device that can suppress the collapse of the electrode when removing the sacrificial oxide film.

In order to achieve the above object, the present invention provides a semiconductor substrate having an interlayer insulating film having a plug; Forming an etch stop layer and a first rare production layer on the interlayer insulating layer; Forming a first trench through which the plug is exposed by etching the first rare production layer and the etch stop layer; Forming a first electrode layer in contact with the plug in the first trench; Forming a second dilution film on the remaining first dilution film including the first electrode layer; Etching the second rare oxidized film to form a second trench exposing a first electrode layer; Forming a lower electrode composed of first and second electrode layers by forming a second electrode layer contacting the first electrode layer on the surface of the second trench; Removing the second and first rare production films; And sequentially forming a dielectric film and an upper electrode on the lower electrode.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are cross-sectional views illustrating a method of forming a capacitor according to the present invention.

Referring to FIG. 2A, an interlayer insulating film 22 is formed on the semiconductor substrate 21. Then, a predetermined portion of the interlayer insulating film 22 is etched to form a trench, and the plug 23 is formed by filling it with a conductive material.

Referring to FIG. 2B, an etch stop layer 24 and a first dilution layer 25 are sequentially formed on the interlayer insulating layer 22 having the plug 23 formed thereon. Subsequently, a predetermined portion of the first oxide layer 25 and the etch stop layer 24 is etched to form a first trench for exposing the lower plug 23.

Here, the etch stop layer 24 is formed to a thickness of 500 ~ 1000Å by the Plasma Enhanced Chemical Vapor Deposition (PECVD) method or the Low Pressure Chemical Vapor Deposition (LPCVD) method. The rare production film 25 is formed in the thickness of 2000-8000 micrometers.

Then, the conductive material is embedded on the substrate product to completely fill the first trenches, and the first electrode layer 26 is formed by CMP to expose the first thin film 25.

Referring to FIG. 2C, a second dilution film 27 is formed on the first electrode layer 26 and the first dilution film 25 to a thickness of 7000 to 16000 μs. Next, the second rare metallization film 27 is patterned to form a second trench 28 exposing the first electrode layer 26.

Referring to FIG. 2D, a second electrode layer material 29 is formed on the surface of the second trench 28 where the first electrode layer 26 is exposed and on the second rare metallization film 27. Here, the second electrode layer material 29 preferably uses titanium (TiN) or ruthenium (Ru). Subsequently, the photosensitive film 30 is coated to fill the second trench 28.

Referring to FIG. 2E, the second electrode layer 29a is formed by performing CMP and etch back on the photosensitive film 30 to remove the second electrode layer material 29 on the second thin film 28. Thus, the lower electrode 31 formed of the first electrode layer 27 and the second electrode layer 29a is formed. Then, the remaining photoresist film is removed through a strip process.

Referring to FIG. 2F, the second and first rare production films 28 and 25 may be removed by wet etching using a solution such as BOE having an etching selectivity with the nitride film. As a result, a cylindrical lower electrode 31 using both sides of the electrode is formed.

In this case, the first electrode layer having a wide area may support the second electrode layer on the upper portion, and replace the predetermined height to prevent the electrode from falling down during wet etching.

Subsequently, although not shown, a dielectric film and an upper electrode are sequentially formed on the lower electrode 31 to form a capacitor of the semiconductor device according to the present invention.

In this case, when the silicon film is used as the lower electrode material, it is preferable to increase the surface area by growing a hemispherical polysilicon film, and the dielectric film is preferably a high dielectric material such as an HfO 2 film, an Al 2 O 3 and a Ta 2 O 5 film.

As the size of the device becomes smaller and the etching depth of the cylindrical capacitor becomes longer, when the sacrificial oxide film defining the lower electrode formation region is removed by wet etching, a phenomenon occurs that the lower electrode collapses.

In order to prevent the lower electrode from falling down as described above, the present invention may reduce the height of the cylindrical second electrode layer deposited by depositing the first electrode layer and subsequently depositing the first electrode layer, thereby preventing the lower electrode from falling down.

As described above, according to the present invention, the first electrode layer is previously formed in the region where the lower electrode is to be formed, and the second electrode layer of the cylindrical shape is formed on the first electrode layer, so that the first electrode layer supports the second electrode layer. By replacing the predetermined height, the lower electrode may be prevented from falling down during the wet etching of the sacrificial oxide film.

Therefore, the reliability of a capacitor and a capacitor formation process can be ensured, and a yield can be improved.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

1A to 1F are cross-sectional views of processes for explaining a method of forming a capacitor according to the related art.

2A through 2E are cross-sectional views of processes for explaining a method of forming a capacitor according to the present invention.

* Description of the symbols for the main parts of the drawings

21: semiconductor substrate 22: interlayer insulating film

23: plug 24: etch barrier

25: first rare production film 26: first trench

27: first electrode layer 28: second rare production film

29: second trench 30: second electrode layer

31: lower electrode

Claims (1)

Providing a semiconductor substrate having an interlayer insulating film having a plug; Forming an etch stop layer and a first rare production layer on the interlayer insulating layer; Forming a first trench through which the plug is exposed by etching the first rare production layer and the etch stop layer; Forming a first electrode layer in contact with the plug in the first trench; Forming a second dilution film on the remaining first dilution film including the first electrode layer; Etching the second rare oxidized film to form a second trench exposing a first electrode layer; Forming a lower electrode composed of first and second electrode layers by forming a second electrode layer contacting the first electrode layer on the surface of the second trench; Removing the second and first rare production films; And And sequentially forming a dielectric film and an upper electrode on the lower electrode.