KR20050070743A - Method for manufacturing semiconductor devices - Google Patents

Abstract

In the method for manufacturing a semiconductor device according to the present invention, a gate electrode is formed on an active region of a semiconductor substrate and nitrogen ions are implanted into the active region of the semiconductor substrate. Thereafter, an LED region, a halo region, and a source / drain region for forming a PMOS transistor are formed in an active region of the semiconductor substrate.

Therefore, in the present invention, by using the gate electrode of the PMOS transistor as an ion implantation mask layer, after ion implantation of nitrogen ions into the active region of the semiconductor substrate, the LEDs and the halo regions are formed to diffuse boron ions to the edge of the channel region. Can be suppressed.

Accordingly, the present invention reduces the sidewall junction capacitance of the edge portion of the gate electrode by suppressing the accumulation of boron ions on the semiconductor substrate under the edge portion of the gate electrode. In addition, the gate-drain overlap capacitance can be reduced by suppressing the diffusion of the boron ions.

Description

Method for manufacturing semiconductor device {Method For Manufacturing Semiconductor Devices}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, parasitics while suppressing short channel effect (SCE) and reverse short channel effect (RSCE) of a PMOS transistor. The present invention relates to a method for manufacturing a semiconductor device in which electrical characteristics are improved by reducing capacitance.

In general, when the semiconductor device is miniaturized as the semiconductor device is highly integrated, for example, the gate electrode, the source / drain, etc. of the MOS transistor are reduced in size, thereby reducing the channel length of the MOS transistor. When the channel length of the MOS transistor is reduced to a predetermined size or less, undesirable phenomena of the MOS transistor, for example, a short channel effect (SCE) and a reverse short channel effect (RSCE) Is generated largely, making it difficult to adjust the threshold voltage of the MOS transistor.

In order to suppress the short channel effect and the reverse short channel effect, the horizontal reduction such as the reduction of the gate electrode length of the MOS transistor and the vertical reduction such as the reduction of the gate insulating layer thickness and the source / drain junction depth of the MOS transistor are performed. Must also be done together. In addition, the horizontal reduction and vertical reduction reduce the voltage of the driving power source, increase the doping concentration of the semiconductor substrate, and in particular, the doping profile of the channel region should be efficiently controlled.

However, since the size of the semiconductor device is rapidly being reduced, but the driving voltage required in the electronic products to which the semiconductor device is applied is still high, for example, in the case of a general NMOS transistor, electrons injected from a source may cause a large potential variation of the drain ( Due to the potential gradient, it is severely accelerated to the drain and thus has a fragile structure in which hot carriers are prone to occur near the drain. In order to improve the structure of a general MOS transistor vulnerable to such a hot carrier, a transistor having a lightly doped drain (LDD) structure has been introduced.

In this LDD NMOS transistor, the low concentration (n-) LDD region located between the channel and the source / drain mitigates the high drain-gate voltage near the drain junction, thereby reducing severe potential fluctuations and further reducing the occurrence of hot carriers. Can be suppressed. Various techniques for manufacturing the transistor of the LDD structure have been proposed. Among these techniques, a method of forming a spacer of an insulating film on both sidewalls of the gate electrode is the most typical method of manufacturing the transistor of the LDD structure. It is used as most mass production technology.

In recent years, as the integration of semiconductor devices progresses, shallow junction technology is required to form a very shallow junction depth in order to effectively suppress the short channel effect (SCE) and the reverse shot channel effect (RSCE). It is becoming. That is, by the boron (B +) ion or BF ₂ + ion in the ion implantation step of the ion implantation with a low energy ion implantation has been to form the shallows junction. Nevertheless, as ultra-high integration of semiconductor devices proceeds, it becomes increasingly difficult to obtain a desired profile for the junction of the LDD region. Therefore, a halo structure is further introduced to suppress the depletion regions of the source / drain in proximity to each other in the horizontal direction without affecting the doping concentration of the channel region that determines the threshold voltage of the MOS transistor.

The halo structure may be formed by implanting impurities of a type opposite to that of the source / drain, that is, halo ions, in a region near the junction of the source / drain adjacent to the gate electrode of the MOS transistor. This is to reduce the depletion region of the source / drain region by forming a diffusion region having an impurity concentration higher than the well doping concentration near the source / drain junction of the MOS transistor.

In the conventional PMOS transistor having such a halo structure, as shown in FIG. 1, the active region of the semiconductor substrate 10 is defined by the device isolation film 11 in the field region of the semiconductor substrate 10, and the semiconductor substrate A gate electrode 20 is formed on the active region of the semiconductor substrate 10 with the gate insulating layer 13 interposed therebetween, and a P-type LDD region in the active region of the semiconductor substrate 10 with the gate electrode 20 at the center thereof. 30 is formed, a hollow region (H) 40 is formed on the semiconductor substrate 10 under the junction of the LDD region 30, and spacers 50 of an insulating film are formed on both sidewalls of the gate electrode 20. Is formed, a P + type source / drain region 60 is formed in the semiconductor substrate 10 with the gate electrode 20 and the spacer 50 in the center, and the gate electrode 20 and the source / drain region ( Silicide layer 70 is formed on 60.

However, in the conventional PMOS transistor manufacturing method, ion implantation of boron (B) ions or BF ions for forming the LDD region 30 and ions of halo ions (As) for forming the halo region (H) are performed. After the implantation is completed, boron ions of the LDD region 30 are activated by a rapid heat treatment process.

However, since the rapid heat treatment process is performed without reducing damage caused by ion implantation of the halo ions (As), for example, an interstitial site, boron ions are formed at the edge of the channel region. The diffusion is accelerated toward the negative portion and accumulated in the semiconductor substrate 10 under the edge of the gate electrode 20. This increases the sidewall junction capacitance at the edge of the gate electrode 20.

In addition, when the LED region 30 is formed, boron ions are diffused and promoted toward the edge of the channel region, thereby increasing the gate-drain overlap capacitance.

Therefore, the parasitic capacitance of the PMOS transistor is increased, thereby deteriorating the electrical characteristics of the PMOS transistor.

Accordingly, it is an object of the present invention to reduce parasitic capacitance by suppressing the diffusion of boron ions to the channel region edge of a PMOS transistor.

Another object of the present invention is to prevent the deterioration of electrical characteristics of a PMOS transistor.

The semiconductor device manufacturing method according to the present invention for achieving the above object is

Forming a gate electrode on an active region of the semiconductor substrate; Ion implanting nitrogen ions into an active region of the semiconductor substrate using the gate electrode as an ion implantation mask layer to suppress diffusion of boron ions to an edge portion of a channel region of the semiconductor substrate; Forming an LED region by implanting boron ions at low concentration into an active region of the semiconductor substrate; Forming a halo region by implanting halo ions into the active region of the semiconductor substrate at a predetermined inclination angle; Forming a spacer on sidewalls of the gate electrode; Forming a source / drain region by implanting boron ions at a high concentration into the active region of the semiconductor substrate; And forming a silicide layer on the gate electrode and the source / drain region.

Preferably, the nitrogen ions may be ion implanted at an energy of 10-50 KeV and a concentration of 1E14-5E14 ions / cm ² .

Therefore, the present invention can improve the electrical characteristics of the semiconductor device by reducing the parasitic capacitance of the PMOS transistor.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are given to the same components and parts of the same operation as the conventional parts.

2A to 2G are cross-sectional process diagrams illustrating a method for manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2A, first, an isolation process, for example, a shallow trench isolation (STI) process, is performed for electrical isolation between active regions of a semiconductor substrate 10, for example, a single crystal silicon substrate. The device isolation film 11 of an insulating film, such as an oxide film, is formed in the field region of the semiconductor substrate 10 by using the?

Although not shown in the drawings, after the formation of the device isolation layer 11, ion implantation for adjusting the threshold voltage V _T , ion implantation for preventing punch through, and channel stopper are formed. Ion implantation, and ion implantation for well formation may be further proceeded.

After the formation of the device isolation layer 11 is completed, the gate insulating film 13, for example, a gate oxide film on the active region of the semiconductor substrate 10 by a thermal oxidation process of a thickness of 20 ~ 100Å To grow. Subsequently, a conductive layer for the gate electrode 20, for example, a polycrystalline silicon layer, is deposited on the gate insulating layer 13 by a chemical vapor deposition process, for example, a low pressure chemical vapor deposition process. . In this case, the polycrystalline silicon layer is doped at a high concentration to perform the role as the gate electrode 20. To this end, the polycrystalline silicon layer is generally stacked and ion implanted with a high concentration of impurities.

Referring to FIG. 2B, an etching mask layer (not shown) corresponding to the pattern of the gate electrode 20 is formed on the gate electrode forming region of the polycrystalline silicon layer of the gate electrode 20 by using a photolithography process. For example, the pattern of a photosensitive film is formed.

Then, using the dry etching process, the polycrystalline silicon layer and the gate insulating layer 13 under the pattern of the photoresist layer are left and the polycrystalline silicon layer and the gate insulating layer 13 in the remaining regions are completely removed, and then the pattern of the photoresist layer is removed. By removing, the pattern of the gate insulating film 13 and the gate electrode 20 is formed.

Referring to FIG. 2C, ions for suppressing diffusion of boron ions in the active region of the semiconductor substrate 10 using the pattern of the gate electrode 20 as an ion implantation mask layer, for example, nitrogen (N) ) Ions 21 are ion implanted at an energy of 10-50 KeV and a concentration of 1E14-5E14 ions / cm ² .

Accordingly, the nitrogen ions 21 promote defects and recombination such as interstitial sites of silicon (Si) ions of the semiconductor substrate 10 to prevent diffusion of boron ions toward the channel edges. Since it suppresses, it can suppress that it accumulates in the semiconductor substrate 10 under the edge part of the said gate electrode 20. FIG. This reduces the sidewall junction capacitance of the edge portion of the gate electrode 20.

In addition, the nitrogen ions 21 can reduce the gate-drain overlap capacitance by suppressing the diffusion of boron ions even in the formation of a subsequent P-type LED region.

Therefore, the present invention can improve the electrical characteristics of the semiconductor device by reducing the parasitic capacitance of the PMOS transistor.

Referring to FIG. 2D, thermal oxidation, for example, over the entirety of the semiconductor substrate 10 including the gate electrode 20 is then performed to mitigate etching damage of the etch surface of the gate electrode 20. The liner oxide film 23 is formed to a thickness of 40 to 60 kPa by the step.

Subsequently, impurities, for example, BF ₂ ions 25, for forming P-type LED regions in the active region of the semiconductor substrate 10 are formed by using the gate electrode 20 as an ion implantation mask layer. Ion implantation with energy of KeV and concentration of 1E14 ~ 5E15 ions / cm ² .

In this case, an ion implantation masking layer (not shown) is exposed on the semiconductor substrate 10 to expose a region for the PMOS transistor of the semiconductor substrate 10 and to mask a region (not shown) for the NMOS transistor of the semiconductor substrate 10. For example, after the pattern of the photoresist film is formed, the BF ₂ ions 25 are ion implanted into the semiconductor substrate 10 in the region for the PMOS transistor.

Similarly, an ion implantation masking layer on the semiconductor substrate 10 to expose a region (not shown) for the NMOS transistor of the semiconductor substrate 10 and to mask a region for the PMOS transistor of the semiconductor substrate 10. (Not shown), for example, an impurity for forming an N-type LED region of the NMOS transistor in the semiconductor substrate 10 in the region for the NMOS transistor after forming a pattern of a photoresist film, for example, arsenide (As) Ion implantation. At this time, the arsenide (As) ions are implanted with an energy of 10 ~ 70 KeV and a concentration of 1E14 ~ 5E15 atom / cm ² .

Referring to FIG. 2E, the halo ions for the halo region (H) 40, for example arsenide (As) ions 27, are then placed on the semiconductor substrate 10 in the region for the PMOS transistor. The ion implantation is performed with respect to the surface of the active region of the semiconductor substrate 10 at an inclination angle of 10 to 40 degrees, an energy of 10 to 60 KeV, and a concentration of 1E14 to 1E15 ions / cm ² , for example.

In this case, an ion implantation masking layer (not shown) is exposed on the semiconductor substrate 10 to expose a region for the PMOS transistor of the semiconductor substrate 10 and to mask a region (not shown) for the NMOS transistor of the semiconductor substrate 10. For example, after forming a pattern of a photoresist film, the arsenide (As) ions 27 are implanted into the semiconductor substrate 10 in the region for the PMOS transistor.

Similarly, an ion implantation masking layer on the semiconductor substrate 10 to expose a region (not shown) for the NMOS transistor of the semiconductor substrate 10 and to mask a region for the PMOS transistor of the semiconductor substrate 10. Not shown), for example, after the pattern of the photoresist film is implanted into the semiconductor substrate 10 of the region for the NMOS transistor, impurities, for example boron (B) ions for forming the halo region of the NMOS transistor . At this time, the boron (B) ions are implanted with an energy of 10 ~ 60 KeV and a concentration of 1E14 ~ 1E15 atom / cm ² .

Thereafter, a heat treatment process, for example, a rapid heat treatment process is performed at a temperature of 600 to 800 ° C. and an inert gas such as nitrogen (N ₂ ) for 10 to 60 seconds to form the halo ions and the LED region. By activating the impurities for the P-type LED region 30 and the halo region (H) (40) is formed.

In this case, the nitrogen ions 21 promote defects and recombination such as interstitial sites of silicon (Si) ions of the semiconductor substrate 10 to prevent the boron ions from diffusing toward the channel edges. Suppress it. Therefore, the nitrogen ions 21 are suppressed from accumulating on the semiconductor substrate 10 under the edge of the gate electrode 20, thereby reducing sidewall junction capacitance of the edge of the gate electrode 20. In addition, the gate-drain overlap capacitance can be reduced by suppressing the diffusion of the boron ions.

Therefore, the present invention can improve the electrical characteristics of the semiconductor device by reducing the parasitic capacitance of the PMOS transistor.

Referring to FIG. 2F, an insulating film, for example, a nitride film is deposited on the liner oxide film 23 by a chemical vapor deposition process, and the gate is formed by etching the nitride film by a dry etching process having anisotropic etching characteristics. Spacers 50 are formed on both sidewalls of the electrode 20.

Subsequently, P-type impurities such as boron (B) ions for forming source / drain regions in the active region of the semiconductor substrate 10 using the gate electrode 20 and the spacer 50 as ion implantation masks. (29) is ion implanted at an ion implantation energy of 3 to 20 KeV and an ion implantation concentration of 1E15 to 5E15 ions / cm ² .

In this case, an ion implantation masking layer (not shown) is exposed on the semiconductor substrate 10 to expose a region for the PMOS transistor of the semiconductor substrate 10 and to mask a region (not shown) for the NMOS transistor of the semiconductor substrate 10. ), For example, after the pattern of the photosensitive film is formed, the boron (B) ion 29 is ion implanted.

Similarly, an ion implantation masking layer on the semiconductor substrate 10 to expose a region (not shown) for the NMOS transistor of the semiconductor substrate 10 and to mask a region for the PMOS transistor of the semiconductor substrate 10. (Not shown), for example, after forming a pattern of a photoresist layer, impurities, such as arsenide (As) ions, for forming a source / drain region of the NMOS transistor are formed in the semiconductor substrate 10 in the region for the NMOS transistor. Ion implantation.

Thereafter, a thermal treatment process, for example, a rapid thermal treatment process, activates ions for source / drain formation to finally bond the P + type source / drain region 60 to the N + type source / drain region (not shown). Form.

Referring to FIG. 2G, the source / drain region is then removed by removing the liner oxide layer 23 on the source / drain region 60 and the gate electrode 20 using the spacer 50 as an etch mask layer. Along with 60 and the gate electrode 20, the source / drain regions and the gate electrode of the NMOS transistor formation region are exposed.

Thereafter, a silicide layer 70 is formed on the source / drain region and the gate electrode of the NMOS transistor forming region together with the source / drain region 60 and the gate electrode 20 using a conventional salicide process.

Next, although not shown in the drawing, a manufacturing process of the present invention is performed by performing a series of subsequent processes such as a silicide process, a contact process, a metal wiring process, and the like, which form a silicide layer on the source / drain region and the gate electrode. To complete. Detailed description thereof is not relevant to the gist of the present invention and will be omitted for convenience of description. Thus, the process of manufacturing the semiconductor device of the present invention is completed.

Therefore, in the present invention, by using the gate electrode of the PMOS transistor as an ion implantation mask layer, after ion implantation of nitrogen ions into the active region of the semiconductor substrate, the LEDs and the halo regions are formed to diffuse boron ions to the edge of the channel region. Can be suppressed.

Accordingly, the present invention reduces the sidewall junction capacitance of the edge portion of the gate electrode by suppressing the accumulation of boron ions on the semiconductor substrate under the edge portion of the gate electrode. In addition, the gate-drain overlap capacitance can be reduced by suppressing the diffusion of the boron ions.

Therefore, the present invention can improve the electrical characteristics of the semiconductor device by reducing the parasitic capacitance of the PMOS transistor.

In addition, according to the present invention, the short channel effect and the reverse short channel effect of the PMOS transistor can be suppressed as in the conventional art by forming a halo region on the semiconductor substrate for the PMOS transistor.

As described in detail above, in the method of manufacturing a semiconductor device according to the present invention, a gate electrode is formed on an active region of a semiconductor substrate, and ion implanted with nitrogen ions into the active region of the semiconductor substrate. Thereafter, an LED region, a halo region, and a source / drain region for forming a PMOS transistor are formed in an active region of the semiconductor substrate.

Therefore, in the present invention, by using the gate electrode of the PMOS transistor as an ion implantation mask layer, after ion implantation of nitrogen ions into the active region of the semiconductor substrate, the LEDs and the halo regions are formed to diffuse boron ions to the edge of the channel region. Can be suppressed.

Accordingly, the present invention reduces the sidewall junction capacitance of the edge portion of the gate electrode by suppressing the accumulation of boron ions on the semiconductor substrate under the edge portion of the gate electrode. In addition, the gate-drain overlap capacitance can be reduced by suppressing the diffusion of the boron ions.

Therefore, the present invention can improve the electrical characteristics of the semiconductor device by reducing the parasitic capacitance of the PMOS transistor.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

1 is a cross-sectional structural view showing a semiconductor device according to the prior art.

2A to 2G are cross-sectional process diagrams illustrating a method for manufacturing a semiconductor device according to the present invention.

Claims (2)

Forming a gate electrode on an active region of the semiconductor substrate; Implanting nitrogen ions into an active region of the semiconductor substrate by using the gate electrode as an ion implantation mask layer to suppress diffusion of boron ions to an edge portion of a channel region of the semiconductor substrate; Forming an LED region by implanting boron ions at low concentration into an active region of the semiconductor substrate; Forming a halo region by implanting halo ions into the active region of the semiconductor substrate at a predetermined inclination angle; Forming a spacer on sidewalls of the gate electrode; Forming a source / drain region by implanting boron ions at a high concentration into the active region of the semiconductor substrate; And Forming a silicide layer on the gate electrode and the source / drain regions. The method of manufacturing a semiconductor device according to claim 1, wherein the nitrogen ions are implanted at an energy of 10 to 50 KeV and a concentration of 1E14 to 5E14 ions / cm ² .