KR20050069008A - Method for fabricating liquid crystal display device - Google Patents

Abstract

The present invention provides a method for manufacturing a liquid crystal display device suitable for improving productivity by reducing the number of masks. To achieve the above object, a method of manufacturing a liquid crystal display device includes: a pixel portion in which first and second regions are defined, and a third method. A first step of depositing a semiconductor layer on a substrate divided by a driving circuit unit in which a fourth region is defined; A first conductive type ion is implanted into the semiconductor layer of the first, second, and fourth regions of the pixel portion and the driving circuit portion by using the same mask to form a first source / drain region, a storage doped region, and a third source / A second step of forming a drain region; Etching the semiconductor layer to form first to fourth active layers in respective regions of the pixel portion and the driving circuit portion; A fourth step of forming a gate insulating film and first to fourth gate electrodes on the first to fourth active layers, respectively; A fifth step of forming a second source / drain region by implanting second conductivity type ions into one region of the driving circuit unit; Forming a first to third source / drain electrodes to be in contact with the pixel portion and the first to third source / drain regions of the driving circuit portion; And forming a pixel electrode in the pixel region in contact with the first drain electrode of the pixel portion.

Description

Method for fabricating Liquid Crystal Display Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD). More particularly, a liquid crystal display device and a method of manufacturing the same, which can increase productivity by reducing the number of masks when simultaneously manufacturing a pixel portion and a driving circuit portion having a CMOS structure. It is about.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal displays (LCDs), plasma display panels (PDPs), electro luminescent displays (ELDs), and vacuum fluorescent displays (VFDs) have been developed. Various flat panel display devices have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for the use of mobile image display device because of the excellent image quality, light weight, thinness, and low power consumption, and mobile type such as monitor of notebook computer. In addition, it is being developed in various ways, such as a television for receiving and displaying broadcast signals, and a monitor of a computer.

As described above, although various technical advances have been made in order for the liquid crystal display device to serve as a screen display device in various fields, the task of improving the image quality as the screen display device has many advantages and disadvantages.

Therefore, in order for a liquid crystal display device to be used in various parts as a general screen display device, development of high quality images such as high definition, high brightness, and large area is maintained while maintaining the characteristics of light weight, thinness, and low power consumption. It can be said.

Among the liquid crystal display devices, an active matrix LCD, which is used for a large-scale and high-definition liquid crystal display device, includes a thin film transistor for pixel driving that is formed for each pixel to operate the pixel. The driving circuit unit is configured to operate the pixel driving thin film transistor and to apply a signal to a gate bus lini and a data bus line.

The driving circuit unit can be generally divided into two types. One is an external signal line driving integrated circuit connected to the liquid crystal panel by forming an integrated circuit separate from the pixel driving TFT on the external substrate of the liquid crystal panel. It is a driving circuit integrated TFT formed on the liquid crystal panel integrally with the driving TFT. The driving circuit integrated TFT is a polysilicon (p-Si) CMOS (Complimentary Metal Oxide Semiconductor) TFT having a large field effect mobility.

In general, a polysilicon-thin film transistor (hereinafter referred to as Poly-TFT) forms a polysilicon film by crystallizing the amorphous silicon film by excimer laser annealing. At this time, N + polysilicon-TFT is formed in the cell array, and CMOS circuits of N + polysilicon-TFT and P + polysilicon TFT are formed in the peripheral circuit.

In addition, since the driving circuit-integrated TFT made of CMOS TFT can be manufactured in one process with the pixel driving TFT, that is, it is possible to form the cell array and the peripheral circuit on the same substrate.

Hereinafter, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

1A to 1I illustrate a method of manufacturing a driving circuit-integrated liquid crystal display device according to the related art, wherein the substrate 1 is divided into a pixel portion and a driving circuit portion, respectively. The pixel portion is divided into an NMOS TFT portion and a storage portion, and the driving circuit portion is divided into a PMOS TFT and an NMOS TFT region, respectively.

For convenience of description, the NMOS TFT portion and the storage portion of the pixel portion are defined as areas A and B, and the PMOS TFT and the NMOS TFT region of the driving circuit portion are defined as areas C and D.

First, as shown in FIG. 1A, after forming the buffer layer 2 on the substrate 1, a polysilicon (p-Si) layer is deposited and patterned to form the first, second, and third circuit parts. And fourth semiconductor layers 3a, 3b, 3c, and 3d. Two semiconductor layers are formed in the pixel portion and the driving circuit portion, respectively. The first and second semiconductor layers 3a and 3b formed in the pixel portion are for the pixel TFT and The third and fourth semiconductor layers 3c and 3d, which are storage lower electrodes and formed in the driving circuit section, are for PMOS and NMOS, respectively.

As shown in FIG. 1B, after the first photoresist 4 is applied to the entire surface of the substrate 1, the first photoresist 4 is selectively subjected to an exposure and development process so that only the second semiconductor layer 3b is exposed. Pattern. Thereafter, impurity ions are implanted using the first photoresist 4 as a mask to dope the second semiconductor layer 3b, and the first photoresist 4 is removed.

Next, an insulating film such as SiO2 or SiNx, a metal film such as Al, Al alloy or Cr, and a second photoresist are sequentially formed over the entire substrate 1, and then the gate forming mask is removed as shown in FIG. 1C. After the second photoresist is patterned by the photolithography process, the metal layer and the insulating layer are sequentially patterned using a mask to form the gate insulating layer 5 and the first, second, third and fourth gate electrodes 6a and 6b. , 6c, 6d). At this time, the first gate electrode 6a of the pixel portion is a gate electrode of the NMOS TFT, the second gate electrode 6b is a storage upper electrode as a previous gate line, and the third and fourth gate electrodes 6c and 6d of the driving circuit portion. ) Are gate electrodes of PMOS and NMOS.

Afterwards, a low concentration of n ions is doped into each semiconductor layer on both sides of the gate electrode using each gate electrode as a mask. As a result of the low concentration of n doping throughout the substrate 1, since the first to fourth gate electrodes 6a, 6b, 6c, and 6d block the ions, the first, third, and fourth semiconductor layers Channel layers 7a and n-layers 7b are formed in (3a, 3c, 3d), respectively.

Then, as shown in FIG. 1D, in order to form a light doped drain (LDD) structure in the A and D regions of the pixel portion and the driving circuit portion, the third photoresist 8 is coated and patterned to form the pixel portion and the driving circuit portion. A high concentration of n + doping is performed in a state where the first and fourth gate electrodes 6a and 6d and the first and fourth semiconductor layers 3a and 3d in the A and D regions are blocked. That is, the third photoresist 8 formed on the pixel portion and the driving circuit portion is formed to cover the first and fourth gate electrodes 6a and 6d and the part of the first and fourth semiconductor layers 3a and 3d. The n + doping causes the ions to be doped only in part of n− (7b). Accordingly, n + doping forms n + layers 7c in the first and fourth semiconductor layers 3a and 3d in the A and D regions of the pixel portion and the driving circuit portion to form an LDD structure.

Subsequently, when the third photoresist 8 is removed and the fourth photoresist 9 is applied and patterned again, high concentration p + doping is performed while blocking the A, B, and D regions of the pixel portion and the driving circuit portion. The p + layer 7d is formed in the C region of the driving circuit portion. Since the concentration of ions doped in the third semiconductor layer 3c at n-doping is about 10 ¹⁴ , and the concentration of ions doped in the third semiconductor layer 3c at p + doping is about 10 ¹⁸ -10 ¹⁹ . n-layer 7b is converted to p + layer 7d by p + doping. This doping method is called a counter doping method.

Accordingly, a thin film transistor having an LDD structure of n + layer 7c and n-layer 7b is formed in the pixel portion, and an NMOS TFT having an n + layer 7c and a PMOS TFT having ap + layer 7d formed in the driving circuit portion. CMOS TFTs are formed.

Thereafter, as shown in FIG. 1F, the fourth photoresist 9 is removed, an interlayer insulating film 10 such as SiNx is deposited over the entire substrate 1, and then patterned to form a source and drain contact hole 11a, 11b).

Subsequently, as shown in FIG. 1G, a metal such as Al is deposited and patterned to form source / drain electrodes 12a and 12b in the source and drain contact holes 11a and 11b, respectively.

As shown in FIG. 1H, after the planarization film 13 is deposited on the entire surface of the substrate 1, the drain electrode 12b of the pixel portion is exposed. The contact hole 14 is formed.

Subsequently, as shown in FIG. 1I, an ITO (Induim Tin Oxide) is deposited and patterned on the entire surface of the planarization film 13 including the contact hole 14 to form the pixel electrode 15. And a storage capacitor, and a driving circuit-integrated liquid crystal display device having a CMOS is formed in the driving circuit unit.

However, the liquid crystal display device according to the prior art formed by the above method is

Since the mask process for doping the semiconductor layer formed in the storage portion of the pixel portion as a storage lower electrode and the mask for forming the source / drain regions are separately required, there is a limit in reducing the number of masks, thereby improving productivity. There is a problem that makes it difficult.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a liquid crystal display device suitable for improving productivity by reducing the number of masks.

In order to achieve the above object, a method of manufacturing a liquid crystal display device of the present invention is to deposit a semiconductor layer on a substrate divided into a pixel portion in which first and second regions are defined and a driving circuit portion in which third and fourth regions are defined. A first step of making; A first conductive type ion is implanted into the semiconductor layer of the first, second, and fourth regions of the pixel portion and the driving circuit portion by using the same mask to form a first source / drain region, a storage doped region, and a third source / A second step of forming a drain region; Etching the semiconductor layer to form first to fourth active layers in respective regions of the pixel portion and the driving circuit portion; A fourth step of forming a gate insulating film and first to fourth gate electrodes on the first to fourth active layers, respectively; A fifth step of forming a second source / drain region by implanting second conductivity type ions into one region of the driving circuit unit; Forming a first to third source / drain electrodes to be in contact with the pixel portion and the first to third source / drain regions of the driving circuit portion; And forming a pixel electrode in the pixel region in contact with the first drain electrode of the pixel portion.

After the second step, ashing the mask to implant LDN structures by injecting low-concentration first conductivity-type ions into the first and fourth regions of the pixel portion and the driving circuit portion, respectively. It is characterized by.

The first and second regions of the pixel portion are NMOS TFT portions and storage portions, respectively, and the third and fourth regions of the driving circuit portion are PMOS TFTs and NMOS TFT regions, respectively.

The storage doped region and the second gate electrode may be a storage lower electrode and a storage upper electrode, respectively.

The first and fourth gate electrodes may be formed to have a wider width than the mask of the second step.

After the fifth step, depositing an interlayer insulating film on the entire surface of the substrate;

And forming source / drain contact holes in the pixel portion and the first, second, and third source / drain regions, respectively.

After the sixth step, the method may further include forming a planarization film on the entire surface of the substrate, and forming a contact hole in one region of the first drain electrode of the pixel portion.

In general, a liquid crystal display device adjusts a desired light by changing a light transmittance according to a twist degree of a liquid crystal due to a potential difference with a common electrode formed on an upper substrate as an image display area.

A liquid crystal display device having the above characteristics requires a storage capacitor in order to improve the liquid crystal voltage holding capability until a next refresh time for each pixel. This auxiliary capacitance is a storage capacitor, connected in parallel with Clc (liquid crystal cap.), And the storage voltage Vst is induced so that the liquid crystal drive voltage Vlc varies during thin film transistor TFT off time. It serves to reduce. Therefore, storage capacitors are a necessary configuration for all LCDs.

In the case of poly-Si TFT, Cst is generally formed of N + active and gate metal, and N + doping is essential when using a line inversion method. When using dot inversion, a capacitor can be formed by an intrinsic state and a gate metal without N + doping. However, in order to form a capacitor, an additional voltage application is required and n + doping is required in the active region (semiconductor layer) used as the lower electrode of the storage capacitor in terms of low voltage and low power consumption of the mobile.

The present invention further reduces the number of mask processes by simultaneously performing storage doping and source / drain masking by additionally forming an N + mask at the source / drain electrode forming portion when fabricating a mask for storage doping, which is essential in a small high-aperture structure. There is a characteristic.

Hereinafter, a liquid crystal display and a manufacturing method thereof according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

2A to 2I are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention.

Prior to explaining the manufacturing method of the liquid crystal display device according to the present invention, the liquid crystal display device of the present invention is divided into a pixel portion and a driving circuit portion, and the pixel portion is divided into an NMOS TFT portion and a storage portion, and the driving circuit portion is respectively It is divided into PMOS TFT and NMOS TFT area.

Hereinafter, for convenience of description, the NMOS TFT portion and the storage portion of the pixel portion are defined and described as A and B regions, respectively, and the PMOS TFT and the NMOS TFT region of the driving circuit portion are defined as C and D regions, respectively.

First, as shown in FIG. 2A, after forming the buffer layer 32 on the substrate 31, the semiconductor layer 33 is deposited. Subsequently, the first photoresist 34 is coated on the semiconductor layer 33, and the first and second photoresists 34 are exposed and developed to expose only n + doped regions of the B region of the pixel portion and the A and D regions of the pixel portion and the driving circuit portion. The photoresist 34 is patterned. The semiconductor layer 33 is made of amorphous silicon.

Next, n + ions are doped into the semiconductor layer 33 using the patterned first photoresist 34 as a mask. The semiconductor layer 33 is activated by a laser crystallization method.

Next, as shown in FIG. 2B, the first photoresist 34 is ashed to a width to form the LDD region, and n-doping is performed to channel the A region of the pixel portion and the D region of the driving circuit portion, respectively. The layer 33a, the n− layer 33b, and the n + layer 33c are formed to form a light doped drain (LDD) structure. Thereafter, the first photoresist 34 is removed.

Subsequently, after the second photoresist is applied and selectively patterned by an exposure and development process, the semiconductor layer 33 is etched with a mask, and as shown in FIG. And third and fourth semiconductor layers 35a, 35b, 35c, and 35d. Two semiconductor layers are formed in the pixel portion and the driving circuit portion, respectively. The first and second semiconductor layers 35a and 35b formed in the pixel portion are formed for the pixel TFT and The third and fourth semiconductor layers 35c and 35d which are storage lower electrodes and are formed in the driving circuit section are for PMOS and NMOS, respectively.

Subsequently, an insulating film such as SiO2 or SiNx, a metal film such as Al, Al alloy or Cr, and a third photoresist are sequentially formed over the substrate 31, and then the third photoresist is performed by a photolithography process using a gate forming mask. Pattern. Thereafter, the metal film and the insulating film are sequentially patterned using a mask, and as shown in FIG. 2D, the gate insulating film 36 and the first, second, third, and fourth gate electrodes 37a, 37b, 37c, and 37d are shown in FIG. ). At this time, the first gate electrode 37a of the pixel portion is a gate electrode of the NMOS TFT, and the second gate electrode 37b is a storage upper electrode as a previous gate line, and the third and fourth gate electrodes 37c and 37d of the driving circuit portion. ) Are gate electrodes of PMOS and NMOS TFTs.

The patterned third photoresist (mask) of the A and D regions of the pixel portion and the driving circuit portion is formed to be 1 to 1.5 μm longer than the first photoresist (mask) patterned on this region to offset the offset. A gate overlap structure is formed that eliminates the problem. The reason for doing this is that when the gate electrodes are formed in the state where the channel layer 33a, the n-layer 33b, and the n + layer 33c are already formed, a misalignment occurs and TFTs are formed asymmetrically. To prevent it.

Subsequently, the third photoresist is removed, and as shown in FIG. 2E, the fourth photoresist 38 is coated and patterned to block the A, B, and D regions of the pixel portion and the driving circuit portion. When doping, a p + layer 33d is formed in the C region of the driving circuit portion.

Accordingly, a thin film transistor having an LDD structure composed of n + layers 33c and n− layers 33b is formed in the B region of the pixel portion and the D region of the driving circuit portion, and the NMOS TFT and p + having the n + layer 33c formed on the driving circuit portion. A CMOS TFT made of the PMOS TFT in which the layer 33d is formed is formed.

Thereafter, as shown in FIG. 2F, the fourth photoresist 38 is removed, and an interlayer insulating film 39 such as SiNx is deposited over the entire substrate 31, and then patterned to form a source and drain contact hole 40a, respectively. 40b).

Subsequently, as illustrated in FIG. 2G, a metal such as Al is deposited and patterned to form source / drain electrodes 41a and 41b in the source and drain contact holes 40a and 40b, respectively.

As shown in FIG. 2H, after the planarization film 42 is deposited on the entire surface of the substrate 31, the contact hole 43 is formed to expose the drain electrode 41b of the pixel portion.

Thereafter, as shown in FIG. 2I, ITO (Induim Tin Oxide) is deposited on the planarization film 42 including the contact hole 43 to be in contact with the drain electrode 41b of the pixel portion, and patterned to remain only in the pixel region. The electrode 44 is formed.

By such a process, an NMOS TFT and a storage capacitor are formed in the pixel portion, and a drive circuit-integrated liquid crystal display element having a CMOS is formed in the drive circuit portion.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention is not limited to the contents described in the above embodiments, but may be modified within the scope obvious to those skilled in the art.

The manufacturing method of the liquid crystal display device according to the present invention having the above configuration has the following effects.

By forming the n + doping process for storage doping and source / drain regions using one mask, the number of masks can be reduced and thus productivity can be improved.

1A to 1I are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to the prior art.

2A through 2I are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention.

Explanation of symbols on main parts of drawing

31 substrate 32 buffer layer

33: semiconductor layer 33a: channel layer

33b: n-layer 33c: n + layer

33d: p + layer 34: first photoresist

35a, 35b, 35c, 35d: first, second, third and fourth semiconductor layers

36: gate insulating film

37a, 37b, 37c, 37d: first, second, third and fourth gate electrodes

38 fourth photoresist 39 interlayer insulating film

40a, 40b: source and drain contact holes 41a, 41b: source and drain electrodes

42: planarization film 43: contact hole

44: pixel electrode

Claims (7)

Depositing a semiconductor layer on a substrate divided into a pixel portion in which first and second regions are defined and a driving circuit portion in which third and fourth regions are defined; A first conductive type ion is implanted into the semiconductor layer of the first, second, and fourth regions of the pixel portion and the driving circuit portion by using the same mask to form a first source / drain region, a storage doped region, and a third source / A second step of forming a drain region; Etching the semiconductor layer to form first to fourth active layers in respective regions of the pixel portion and the driving circuit portion; A fourth step of forming a gate insulating film and first to fourth gate electrodes on the first to fourth active layers, respectively; A fifth step of forming a second source / drain region by implanting second conductivity type ions into one region of the driving circuit unit; Forming a first to third source / drain electrodes to be in contact with the pixel portion and the first to third source / drain regions of the driving circuit portion; And forming a pixel electrode in the pixel area in contact with the first drain electrode of the pixel portion. The method of claim 1, After the second step, ashing the mask to implant LDN structures by injecting low-concentration first conductivity-type ions into the first and fourth regions of the pixel portion and the driving circuit portion, respectively. Method of manufacturing a liquid crystal display device, characterized in that. The method of claim 1, Wherein the first and second regions of the pixel portion are NMOS TFT portions and storage portions, respectively, and the third and fourth regions of the driving circuit portion are PMOS TFTs and NMOS TFT regions, respectively. The method of claim 1, And the storage doped region and the second gate electrode are a storage lower electrode and a storage upper electrode, respectively. The method of claim 1, And the first and fourth gate electrodes are formed to have a wider width than the mask of the second step. The method of claim 1, After the fifth step, depositing an interlayer insulating film on the entire surface of the substrate; And forming source / drain contact holes in the pixel portion and the first, second, and third source / drain regions of the driving circuit portion, respectively. The method of claim 1, After the sixth step, forming a planarization film on the entire surface of the substrate; And forming a contact hole in one region of the first drain electrode of the pixel portion.