KR20030073569A - A method for manufacturing of thin film transistor liquid crystal display - Google Patents
A method for manufacturing of thin film transistor liquid crystal display Download PDFInfo
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- KR20030073569A KR20030073569A KR1020020013199A KR20020013199A KR20030073569A KR 20030073569 A KR20030073569 A KR 20030073569A KR 1020020013199 A KR1020020013199 A KR 1020020013199A KR 20020013199 A KR20020013199 A KR 20020013199A KR 20030073569 A KR20030073569 A KR 20030073569A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133514—Colour filters
- G02F1/133519—Overcoatings
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
- G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
Abstract
Description
본 발명은 박막 트랜지스터-액정 표시 장치의 제조방법에 관한 것으로, 특히 마스크 공정을 줄일 수 있는 박막 트랜지스터 액정표시장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor-liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor liquid crystal display device capable of reducing a mask process.
일반적으로 평판표시장치(Flat Panel Display)의 일종인 LCD(Liquid Crystal Display)는 액체의 유동성과 결정의 광학적 성질을 겸비하는 액정에 전계를 인가하여 광학적 이방성을 변화시켜 얻어지는 명암의 차이로 화상을 얻는 장치이다.In general, liquid crystal displays (LCDs), which are a type of flat panel display, obtain an image with a difference in contrast obtained by changing an optical anisotropy by applying an electric field to a liquid crystal having both liquidity and optical properties of a crystal. Device.
그리고 사용되는 액정의 종류에 따라 TN(Twisted Nematic), STN(Super TN), 강유전성(Ferro electric) LCD 등으로 나누어지고, 화소의 스위칭 소자인 TFT를 각 화소마다 내장하는 TFT LCD 등이 사용되고 있다.According to the type of liquid crystal used, TN (Twisted Nematic), STN (Super TN), Ferroelectric (LCD), etc. are divided into TFT LCDs, etc., in which TFTs, which are switching elements of pixels, are incorporated for each pixel.
또한, 화면을 수만에서 수십만개로 분할하여 각 화소에 구동소자를 제작하고 스위칭 특성을 이용하여 화소의 동작을 제어하는 방식의 AMLCD 등이 사용되고 있다.In addition, AMLCD and the like are used in which a driving device is manufactured for each pixel by dividing the screen into tens of thousands and hundreds of thousands, and the operation of the pixel is controlled using switching characteristics.
이러한 LCD는 종래 음극선관(Cathode Ray Tube)에 비해 소비전력이 낮고, 경박단소화가 용이하며 칼라화, 대형화 및 고정세화가 가능하여 차츰 사용 범위가 넓어지고 있으며, 최근에는 액정의 응답속도가 빠르고 고화질화에 유리한 TFT-LCD가 주목받고 있다.These LCDs have lower power consumption, easier light weight and shorter size than conventional cathode ray tubes, and can be used in color, large size, and high resolution, and are gradually expanding their range of use. Advantageous TFT-LCDs have attracted attention.
이하, 첨부된 도면을 참조하여 종래의 박막트랜지스터 액정표시장치의 제조방법에 대하여 설명하기로 한다.Hereinafter, a manufacturing method of a conventional thin film transistor liquid crystal display device will be described with reference to the accompanying drawings.
도 1a 내지 도 1e는 종래의 4 마스크를 이용한 박막트랜지스터 액정표시장치의 제조방법을 나타낸 공정 단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a thin film transistor liquid crystal display using a conventional four mask.
도 1a에 도시한 바와 같이 절연 기판 예컨대 유리기판(11) 상부에 소정의 금속막을 증착한 후, 제 1 마스크 공정을 이용한 식각공정을 통해 소정 부분 패터닝하여 게이트 전극(12)을 형성한다.As shown in FIG. 1A, a predetermined metal film is deposited on an insulating substrate, for example, a glass substrate 11, and then a predetermined portion is patterned through an etching process using a first mask process to form a gate electrode 12.
이어, 상기 결과물 상부에 게이트 절연막(13)을 증착한 후, 상기 게이트 절연막(13)상에 도핑되지 않는 비정질 실리콘 재질의 활성층(14)과, 도핑된 비정질 실리콘 재질의 n+채널층(15) 그리고 소오스/드레인 전극용 금속층(16)을 차례로 증착한다.Subsequently, after the gate insulating layer 13 is deposited on the resultant layer, the undoped amorphous silicon material active layer 14 and the doped amorphous silicon material n + channel layer 15 are formed on the gate insulating film 13. Then, the source / drain electrode metal layer 16 is sequentially deposited.
도 1b에 도시한 바와 같이 상기 소오스/드레인 전극용 금속층(16)상에 그레이-톤 포토레지스트(17)를 증착하고, 노광 및 현상공정을 이용하여 패터닝한다.As shown in FIG. 1B, a gray-tone photoresist 17 is deposited on the source / drain electrode metal layer 16, and patterned using an exposure and development process.
그리고 상기 패터닝된 그레이-톤 포토레지스트(17)를 제 2 마스크로 이용한 식각공정을 통해 상기 소오스/드레인 전극용 금속층(16)을 식각한다.The metal layer 16 for source / drain electrodes is etched through an etching process using the patterned gray-tone photoresist 17 as a second mask.
도 1c에 도시한 바와 같이 상기 소오스/드레인 전극용 금속층(16)이 노출되도록 상기 패터닝된 그레이-톤 마스크 포토레지스트(17)에 에싱(Ashing) 공정을 실시한 후, 상기 도핑된 비정질 실리콘 재질의 활성층(15)과, 상기 비정질 실리콘 재질의 채널층(14) 식각한다. 이때, 상기 소오스/드레인 전극용 금속층(16) 사이의 n+ 채널층(14)은 소오스/드레인 전극용 금속층(16) 식각을 막아준다.As shown in FIG. 1C, an ashing process is performed on the patterned gray-tone mask photoresist 17 to expose the source / drain electrode metal layer 16, and then the active layer of the doped amorphous silicon material. 15 and the channel layer 14 of the amorphous silicon material is etched. In this case, the n + channel layer 14 between the source / drain electrode metal layer 16 prevents etching of the source / drain electrode metal layer 16.
그리고 상기 소오스/드레인 전극용 금속층(16)을 다시 식각한다. 이때, 상기 채널층(14)의 소오스/드레인 전극(16)이 식각된 후, n+ 채널층(15)을 선택적으로 식각한다.The source / drain electrode metal layer 16 is etched again. In this case, after the source / drain electrodes 16 of the channel layer 14 are etched, the n + channel layer 15 is selectively etched.
이어, 상기 에싱된 그레이-톤 포토레지스트(17)를 마스크로 이용하여 상기소오스/드레인 전극용 금속층(16)을 식각한 후, n+채널층(15)을 선택적으로 식각한다.Subsequently, the source / drain electrode metal layer 16 is etched using the ashed gray-tone photoresist 17 as a mask, and then the n + channel layer 15 is selectively etched.
도 1d에 도시한 바와 같이 상기 에싱된 그레이-톤 포토레지스트(17)를 제거한 후, 상기 소오스/드레인 전극용 금속층(16)을 포함한 기판(11) 전면에 보호막(18)을 형성한다.After removing the ashed gray-tone photoresist 17 as shown in FIG. 1D, a protective film 18 is formed on the entire surface of the substrate 11 including the metal layer 16 for the source / drain electrodes.
이어, 제 3 마스크 공정을 이용한 식각공정을 통해 상기 소오스/드레인 전극용 금속층(16)이 선택적으로 노출되도록 콘택홀(19)을 형성한다.Next, the contact hole 19 is formed to selectively expose the source / drain electrode metal layer 16 through an etching process using a third mask process.
도 1e에 도시한 바와 같이 상기 콘택홀(19)을 포함한 상기 보호막(18)상에 ITO 물질을 증착하고, 제 4 마스크 공정을 이용한 식각공정을 통해 상기 콘택홀(19)을 통하여 상기 소오스/드레인 전극용 금속층(16)과 접촉되는 화소전극(20)을 형성한다.As shown in FIG. 1E, an ITO material is deposited on the passivation layer 18 including the contact hole 19, and the source / drain is formed through the contact hole 19 through an etching process using a fourth mask process. The pixel electrode 20 in contact with the electrode metal layer 16 is formed.
그러나 상기와 같은 종래의 박막 트랜지스터 액정표시장치의 제조방법에 있어서는 다음과 같은 문제점이 있었다.However, the above-described conventional manufacturing method of the thin film transistor liquid crystal display device has the following problems.
패턴을 형성하기 위하여 설계된 마스크는 매우 고가이어서 공정에 적용되는 마스크 수가 증대되면 액정표시소자를 제조하는 비용이 이에 비례하여 상승한다.The mask designed to form the pattern is very expensive, and as the number of masks applied to the process increases, the cost of manufacturing the liquid crystal display device increases proportionally.
따라서, 4개의 마스크를 가지고 식각 공정이 진행되므로 장비간 잦은 이동에 의한 공정시간 증가 등으로 공정이 매우 복잡하다.Therefore, since the etching process is performed with four masks, the process is very complicated due to an increase in process time due to frequent movement between equipments.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 마스크 수를 감소시켜 비용 절감 및 생산 능력을 향상시킬 수 있는 박막트랜지스터 액정표시장치의 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of manufacturing a thin film transistor liquid crystal display device that can reduce the number of masks to improve the cost and production capacity to solve the above problems.
도 1a 내지 도 1e는 종래의 4 마스크를 이용한 박막트랜지스터 액정표시장치의 제조방법을 나타낸 공정 단면도1A to 1E are cross-sectional views illustrating a method of manufacturing a thin film transistor liquid crystal display device using a conventional four mask.
도 2a 내지 도 2c는 본 발명의 일실시예에 따른 박막트랜지스터 액정표시장치의 제조방법을 나타낸 공정 평면도2A through 2C are process plan views illustrating a method of manufacturing a thin film transistor liquid crystal display according to an exemplary embodiment of the present invention.
도 3a 내지 도 3d는 도 2의 A-A에 따른 단면도3A to 3D are cross-sectional views taken along line A-A of FIG.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
101 : 유리기판 102a : 게이트 라인101: glass substrate 102a: gate line
103a : 화소전극 104 : 제 1 포토레지스트103a: pixel electrode 104: first photoresist
105 : 게이트 절연막 106 : 활성층105: gate insulating film 106: active layer
107 : 채널층 108 : 제 2 포토레지스트107: channel layer 108: second photoresist
109 : 소오스/드레인 전극 110 : 보호막109: source / drain electrode 110: protective film
111 : 제 3 포토레지스트 112 : 배리어막111: third photoresist 112: barrier film
상기와 같은 목적을 달성하기 위한 본 발명의 박막트랜지스터 액정표시장치의 제조방법은 절연기판상에 게이트용 메탈과 투명물질을 순차적으로 증착한 후, 제 1 마스크를 이용하여 게이트 라인과 화소전극을 정의하는 단계와, 상기 결과물 상부에 게이트 절연막과 활성층, 채널층을 순차적으로 증착한 후, 제 2 마스크를 이용하여 선택적으로 식각하는 단계와, 상기 결과물 상부에 소오스/드레인용 메탈과 보호막을 증착하는 단계와, 상기 보호막상에 선택적으로 풀-톤 및 하프-톤 영역을 갖는 제 3 마스크를 형성하는 단계와, 상기 풀-톤 영역의 제 3 마스크를 이용하여 상기 소오스/드레인용 메탈과 보호막을 식각하는 단계와, 상기 하프-톤 영역의 제 3 마스크를 에싱공정을 이용하여 제거하는 단계와, 상기 노출된 채널층상를 플라즈마 처리하는 단계를 포함하는 것을 특징으로 한다.In the method of manufacturing the thin film transistor liquid crystal display device according to the present invention for achieving the above object, the gate metal and the transparent material are sequentially deposited on an insulating substrate, and then the gate line and the pixel electrode are defined using a first mask. And sequentially depositing a gate insulating layer, an active layer, and a channel layer on the resultant, and selectively etching using a second mask, and depositing a source / drain metal and a protective layer on the resultant. And forming a third mask having selectively full-tone and half-tone regions on the passivation layer, and etching the source / drain metal and the passivation layer using the third mask of the full-tone region. Removing the third mask of the half-tone region using an ashing process; and plasma treating the exposed channel layer. It is characterized by including.
또한, 상기 투명물질은 ITO, IXO, IZO중 어느 하나를 사용하는 것이 바람직하다.In addition, the transparent material is preferably any one of ITO, IXO, IZO.
또한, 상기 게이트용 메탈과 소오스/드레인용 메탈은 Al, Cr/Al, Cr, Mo, Mo/Al, Mo/Al/MoTa, Ti/AlSi/Ti, Mo/MoSi, CrMo, Al-Nd, Mo/Al-Nd/Mo, Mo/Al-Nd, Al-Ti, Ti/Al/Ti중 어느 하나를 사용하는 것이 바람직하다.In addition, the gate metal and the source / drain metal are Al, Cr / Al, Cr, Mo, Mo / Al, Mo / Al / MoTa, Ti / AlSi / Ti, Mo / MoSi, CrMo, Al-Nd, Mo It is preferable to use any one of / Al-Nd / Mo, Mo / Al-Nd, Al-Ti, Ti / Al / Ti.
또한, 상기 게이트 절연막은 SiNx, SiON중 어느 하나를 사용하고, 상기 보호막은 SiNx를 사용하는 것이 바람직하다.Further, the gate insulating film using any one of SiN x, SiON, the protective film is preferably used in the SiN x.
이하, 첨부된 도면을 참조하여 본 발명의 박막트랜지스터 액정표시장치의 제조방법에 대하여 상세히 설명하기로 한다.Hereinafter, a method of manufacturing a thin film transistor liquid crystal display of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 일실시예에 따른 박막트랜지스터 액정표시장치의 제조방법을 나타낸 공정 평면도이고, 도 3a 내지 도 3d는 도 2의 A-A에 따른 단면도이다.2A to 2C are plan views illustrating a method of manufacturing a thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention, and FIGS. 3A to 3D are cross-sectional views taken along line A-A of FIG. 2.
도 2a 내지 도 3a에 도시한 바와 같이 절연 기판 예컨대 유리기판(101)상에 게이트 영역과 화소영역을 정의한 후, 상기 기판(101) 전면에 게이트 라인용 금속막(102)과 화소전극용 투명물질(103)을 증착한다. 이때, 상기 게이트 라인용 금속막(102)은 Al, Cr/Al, Cr, Mo, Mo/Al, Mo/Al/MoTa, Ti/AlSi/Ti, Mo/MoSi, CrMo, Al-Nd, Mo/Al-Nd/Mo, Mo/Al-Nd, Al-Ti, Ti/Al/Ti중 어느 하나를 사용하고, 상기 투명물질(103)은 ITO, IXO, IZO중 어느 하나를 사용한다.As shown in FIGS. 2A to 3A, the gate region and the pixel region are defined on an insulating substrate such as a glass substrate 101, and then the gate line metal film 102 and the transparent material for the pixel electrode are formed on the entire substrate 101. (103) is deposited. In this case, the gate line metal film 102 may include Al, Cr / Al, Cr, Mo, Mo / Al, Mo / Al / MoTa, Ti / AlSi / Ti, Mo / MoSi, CrMo, Al-Nd, Mo / Al-Nd / Mo, Mo / Al-Nd, Al-Ti, Ti / Al / Ti is used, and the transparent material 103 uses any one of ITO, IXO, and IZO.
그리고 상기 투명물질(103)상에 제 1 포토레지스트(104)를 증착하고, 노광 및 현상공정을 이용하여 선택적으로 패터닝한 후, 상기 패터닝된 제 1 포토레지스트(104)를 이용한 식각공정을 통해 상기 게이트 라인용 금속막(102)과 화소전극용 투명물질(103)을 선택적으로 패터닝하여 게이트 라인(102a)과 화소전극(103a)을 형성한다.After depositing the first photoresist 104 on the transparent material 103, and selectively patterning the photoresist 104 using an exposure and development process, the etching process using the patterned first photoresist 104 is performed. The gate line 102a and the pixel electrode 103a are formed by selectively patterning the gate line metal film 102 and the pixel electrode transparent material 103.
도 2b 및 도 3b에 도시한 바와 같이 상기 결과물 상부에 게이트 절연막(105)을 증착하고, 상기 게이트 절연막(105)상에 도핑되지 않는 비정질 실리콘 재질의 활성층(106)과, 도핑된 비정질 실리콘 재질의 n+채널층(107)을 차례로 증착한다.이때, 상기 게이트 절연막은 SiNx, SiON중 어느 하나를 사용한다.As shown in FIGS. 2B and 3B, a gate insulating layer 105 is deposited on the resultant, an active layer 106 of an amorphous silicon material that is not doped, and a doped amorphous silicon material of the doped amorphous silicon material. n + channel layers 107 are sequentially deposited. At this time, the gate insulating film uses any one of SiN x and SiON.
그리고 상기 n+채널층(107)상에 제 2 포토레지스트(108)를 증착하고, 노광 및 현상공정을 이용하여 패터닝한 후, 상기 패터닝된 제 2 포토레지스트(108)를 마스크로 이용하여 상기 화소영역의 화소전극(103a)이 노출되도록 상기 활성층(106)과 n+채널층층(107) 그리고 게이트 라인용 금속막(102)을 선택적으로 식각한다.The second photoresist 108 is deposited on the n + channel layer 107, and is patterned by using an exposure and development process. The patterned second photoresist 108 is used as a mask. The active layer 106, the n + channel layer layer 107, and the gate line metal film 102 are selectively etched to expose the pixel electrode 103a in the region.
도 2c 및 도 3c에 도시한 바와 같이 상기 결과물 상부에 소오스/드레인 전극용 금속막(109)과 보호막(110)을 차례로 증착하고, 상기 보호막(110)상에 제 3 포토레지스트(111)를 증착한 후, 노광 및 현상공정을 이용하여 풀-톤 영역과, 하프-톤 영역을 갖도록 선택적으로 패터닝하다. 이때, 상기 소오스/드레인 전극용 금속막(109)은 Al, Cr/Al, Cr, Mo, Mo/Al, Mo/Al/MoTa, Ti/AlSi/Ti, Mo/MoSi, CrMo, Al-Nd, Mo/Al-Nd/Mo, Mo/Al-Nd, Al-Ti, Ti/Al/Ti중 어느 하나를 사용하고, 상기 보호막(110)은 SiNx를 사용한다.As shown in FIGS. 2C and 3C, the metal film 109 for source / drain electrodes and the passivation layer 110 are sequentially deposited on the resultant, and the third photoresist 111 is deposited on the passivation layer 110. Thereafter, the patterning is performed to have a full-tone region and a half-tone region using an exposure and development process. At this time, the source / drain electrode metal film 109 may include Al, Cr / Al, Cr, Mo, Mo / Al, Mo / Al / MoTa, Ti / AlSi / Ti, Mo / MoSi, CrMo, Al-Nd, Mo / Al-Nd / Mo, Mo / Al-Nd, Al-Ti, Ti / Al / Ti is used, and the protective film 110 uses SiN x .
이어, 상기 패터닝된 제 3 포토레지스트(111)를 마스크로 이용하여 상기 채널층(107)이 선택적으로 노출되도록 상기 보호막(110)과 소오스/드레인 전극용 금속막(109)을 식각한 후, 상기 하프-톤 영역의 제 3 포토레지스트(111)에 에싱공정을 실시한다.Subsequently, the passivation layer 110 and the metal layer for source / drain electrodes 109 are etched to selectively expose the channel layer 107 using the patterned third photoresist 111 as a mask. An ashing process is performed on the third photoresist 111 in the half-tone region.
도 2c 및 도 3d에 도시한 바와 같이 상기 노출된 채널층(107)에 O2플라즈마 처리하여 SiO2배리어막(112)을 형성한 후, 상기 제 3 포토레지스트(111)를 제거한다.As shown in FIGS. 2C and 3D, after forming the SiO 2 barrier layer 112 by performing O 2 plasma treatment on the exposed channel layer 107, the third photoresist 111 is removed.
이상에서 설명한 바와 같이 본 발명의 박막트랜지스터 액정표시장치의 제조방법에 의하면, 3개의 마스크를 이용하여 식각 공정을 진행하므로 4개의 마스크를 이용하는 종래와 비교하여 제작비용이 감소하고, 공정을 단순화할 수 있다.As described above, according to the method of manufacturing the thin film transistor liquid crystal display device of the present invention, since the etching process is performed using three masks, the manufacturing cost is reduced and the process can be simplified compared with the conventional method using four masks. have.
따라서, 수율 및 양산 능력을 증가시킬 수 있다.Thus, yield and mass production capacity can be increased.
또한, 화소전극이 소오스/드레인 전극 및 게이트 라인 하부에 존재하므로 화소전극의 성분에 의한 불량이 발생하지 않는다.In addition, since the pixel electrode exists under the source / drain electrodes and the gate line, defects due to the components of the pixel electrode do not occur.
그리고 축전용량 형성시 소오스/드레인 전극에 따라 블랙매트릭스의 역할을 하게되므로 정렬마진 증가에 의한 고개구율화가 가능하다.In addition, since the black matrix is used as the source / drain electrode when the capacitance is formed, it is possible to increase the high opening ratio by increasing the alignment margin.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100781430B1 (en) * | 2004-01-09 | 2007-12-03 | 비오이 하이디스 테크놀로지 주식회사 | An array panel manufacturing method of FFS mode liquid crystal display |
| KR100917654B1 (en) * | 2006-11-10 | 2009-09-17 | 베이징 보에 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 | TFT-LCD pixel unit and method for manufacturing the same |
| US7960199B2 (en) | 2004-06-25 | 2011-06-14 | Lg Display Co., Ltd. | Thin film transistor (TFT) array substrate and fabricating method thereof that protect the TFT and a pixel electrode without a protective film |
| US7994706B2 (en) | 2007-05-15 | 2011-08-09 | Samsung Mobile Display Co., Ltd. | Organic light emitting diode display device and method of fabricating the same |
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| KR100372306B1 (en) * | 1998-11-19 | 2003-08-25 | 삼성전자주식회사 | Manufacturing Method of Thin Film Transistor |
| KR100590753B1 (en) * | 1999-02-27 | 2006-06-15 | 삼성전자주식회사 | Thin film transistor substrate for liquid crystal display and manufacturing method thereof |
| JP4034470B2 (en) * | 1999-05-31 | 2008-01-16 | 株式会社アドバンスト・ディスプレイ | Liquid crystal display device and manufacturing method thereof |
| KR100590750B1 (en) * | 1999-03-08 | 2006-06-15 | 삼성전자주식회사 | a manufacturing methods of thin film transistor substrates for liquid crystal displays |
| KR100494703B1 (en) * | 2001-12-31 | 2005-06-13 | 비오이 하이디스 테크놀로지 주식회사 | A method for manufacturing of thin film transistor liquid crystal display |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100781430B1 (en) * | 2004-01-09 | 2007-12-03 | 비오이 하이디스 테크놀로지 주식회사 | An array panel manufacturing method of FFS mode liquid crystal display |
| US7960199B2 (en) | 2004-06-25 | 2011-06-14 | Lg Display Co., Ltd. | Thin film transistor (TFT) array substrate and fabricating method thereof that protect the TFT and a pixel electrode without a protective film |
| KR101126396B1 (en) * | 2004-06-25 | 2012-03-28 | 엘지디스플레이 주식회사 | Thin film transistor array substrate and fabricating method thereof |
| KR100917654B1 (en) * | 2006-11-10 | 2009-09-17 | 베이징 보에 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 | TFT-LCD pixel unit and method for manufacturing the same |
| US7892897B2 (en) | 2006-11-10 | 2011-02-22 | Beijing Boe Optoelectronics Technology Co., Ltd. | TFT-LCD pixel unit and method for manufacturing the same |
| US8134158B2 (en) | 2006-11-10 | 2012-03-13 | Beijing Boe Optoelectronics Technology Co., Ltd. | TFT-LCD pixel unit and method for manufacturing the same |
| US7994706B2 (en) | 2007-05-15 | 2011-08-09 | Samsung Mobile Display Co., Ltd. | Organic light emitting diode display device and method of fabricating the same |
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