KR20080060534A - Method of manufacturig thin film transistor substrate - Google Patents

Abstract

A method for manufacturing a TFT substrate is provided to perform an impurity doping process simultaneously in the active layer of a TFT and a lower storage electrode included into a storage capacitor, thereby simplifying the process. A method for manufacturing a TFT(Thin Film Transistor) substrate comprises the following steps of: forming a patterned poly silicon layer to first and second areas on a substrate(101); forming a gate insulating layer(112) on the poly silicon layer; forming source and drain areas(134S,134D) doped with first impurities on the poly silicon layer of the first area, and a first conductive metal pattern including a first gate electrode and a conductive layer on the gate insulating layer; forming source and drain areas doped with second impurities on the poly silicon layer of the second area, a lower storage electrode formed by extending a part of the poly silicon layer, and a second conductive metal pattern including a storage line(206) and a second gate electrode; forming an interlayer insulating layer(126) including a storage contact hole(224) on the first and second metal pattern, a storage hole(218), and plural contact holes which the source and drain contact holes(124S,124D) have; and forming the storage contact hole, an upper storage electrode(208) on the storage hole, and source and drain electrodes(108,110) in the source and drain contact holes.

Description

The manufacturing method of a thin film transistor substrate {METHOD OF MANUFACTURIG THIN FILM TRANSISTOR SUBSTRATE}

1 is a cross-sectional view illustrating a display area and a driving circuit area according to an exemplary embodiment of the present invention.

2 is a cross-sectional view for describing a first mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present disclosure.

3 is a cross-sectional view illustrating a second mask process in the method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 4A to 4C are cross-sectional views illustrating a second mask process of the present invention in detail.

5 is a cross-sectional view illustrating a third mask process in the method of manufacturing the thin film transistor substrate according to the embodiment, and FIGS. 6A and 6B are cross-sectional views illustrating the third mask process of the present invention in detail.

FIG. 7 is a cross-sectional view illustrating a fourth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 8A to 8D are cross-sectional views illustrating a fourth mask process of the present invention in detail.

9 is a cross-sectional view for describing a fifth mask process in the method of manufacturing the thin film transistor substrate according to the embodiment.

<Description of the symbols for the main parts of the drawings>

101 substrate 106,146 gate electrode

108,158: source electrode 110,160: drain electrode

114,134: active layer 116: buffer film

124S, 154S: Source Contact Hole 124D, 154D: Drain Contact Hole

206: storage line 208: storage upper electrode

218: storage hole 224: storage contact hole

234: lower storage electrode

The present invention relates to a thin film transistor substrate using low temperature polysilicon, and more particularly, to a method of manufacturing a thin film transistor substrate capable of reducing the number of processes.

A liquid crystal display (LCD) displays an image by causing each of the liquid crystal subpixels arranged in a matrix form on a liquid crystal display panel (hereinafter, referred to as a liquid crystal panel) to adjust light transmittance according to a video signal. The liquid crystal display uses a thin film transistor (TFT) as a switch element for driving an active matrix. The TFT uses an amorphous silicon thin film or a low temperature poly silicon (LTPS) thin film. The LTPS thin film is a thin film obtained by crystallizing an amorphous silicon thin film by a laser annealing method, so the electron mobility is very high, and the circuit is highly integrated, and thus, the driving circuit of the image display unit may be embedded on the substrate. The driving circuit incorporated in the liquid crystal panel using LTPS includes a plurality of PMOS TFTs, NMOS TFTs, and CMOS TFTs.

Each of the liquid crystal subpixels arranged in a matrix form in the image display portion of the liquid crystal panel includes a TFT connected to the gate line and the data line, and a liquid crystal capacitor and a storage capacitor connected in parallel with the TFT. Here, in the image display unit of the liquid crystal panel, the active layer constituting the storage capacitor becomes conductive by impurity doping. In this case, an additional mask process is required to dope impurities into the active layer constituting the storage capacitor, thereby increasing the number of processes.

Therefore, the conventional liquid crystal display device has a problem in that the number of processes is complicated as a mask process for forming an active layer of a TFT and a storage capacitor and a mask process for doping impurities in an active layer of a storage capacitor are required.

Accordingly, the technical problem of the present invention is to provide a method for manufacturing a thin film transistor substrate which can reduce the number of processes.

In order to achieve the above technical problem, a method of manufacturing a thin film transistor substrate according to the present invention comprises the steps of forming a polysilicon layer patterned into first and second regions on the substrate; Forming a gate insulating film on the polysilicon layers of the first and second regions; Forming a first conductive metal pattern and a conductive layer including a source and a drain region doped with a first impurity in the polysilicon layer of the first region and a first gate electrode on the gate insulating layer; A source and drain region doped with a second impurity in the polysilicon layer of the second region, a storage lower electrode formed by extending a portion of the polysilicon layer, and the conductive layer is patterned to include a storage line and a second gate electrode Forming a second conductive metal pattern; Forming an interlayer insulating layer on the first and second metal patterns, the interlayer insulating layer including a plurality of contact holes included in the storage contact hole, the storage hole, the source and the drain contact hole; And forming source and drain electrodes in the storage contact hole, a storage upper electrode on the storage hole, and a source and drain contact hole.

Here, the second impurity in the polysilicon layer of the second region may be simultaneously doped in the source region, the drain region and the storage lower electrode.

In addition, the first impurity may be doped with p impurities.

The source and drain regions doped with the second impurity may be doped with n + impurities.

In this case, the n- impurity may be further doped into the source and drain regions doped with the second impurity to further include first and second LED regions.

Meanwhile, forming an interlayer insulating layer including a plurality of contact holes included in the storage contact hole, the storage hole, the source and the drain contact hole on the first and second metal patterns may be formed on the interlayer insulating layer. Forming a first and a second photoresist pattern; Removing a portion of the interlayer insulating layer by a first etching process using the first and second photoresist patterns as a mask; Ashing the first and second photoresist patterns to remove the second photoresist pattern thinner than the first photoresist pattern; Removing the interlayer insulating film and the gate insulating film by a second etching process using the first photoresist pattern as a mask to form a storage hole, a storage contact hole, a source and a drain contact hole; Removing the first photoresist pattern by a strip process.

The electrode may be formed of the same electrode as the source and drain electrodes and the storage upper electrode.

Other technical problems and features of the present invention in addition to the above technical problem will become apparent through the description of the embodiments with reference to the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a display area and a driving circuit area according to an exemplary embodiment of the present invention.

The thin film transistor substrate according to the present invention is divided into a display area in which a plurality of sub pixels are arranged in a matrix to display an image, and a drive circuit area in which a driving circuit for driving the display area is formed. The driving circuit of the thin film transistor substrate is composed of a plurality of signal lines and CMOS TFTs in which a plurality of NMOS TFTs, PMOS TFTs, NMOS TFTs, and PMOS TFTs are connected in parallel.

One sub-pixel in the display area shown in FIG. 1 has gate lines and data lines intersecting on the lower substrate 101 with an interlayer insulating film 126 interposed therebetween, NMOS TFTs formed at each intersection thereof, and an intersection structure thereof. A pixel electrode (not shown) formed in the provided pixel region and a storage capacitor Cst for preventing a variation of the pixel voltage signal charged in the pixel electrode (not shown) are provided.

The gate line supplies the scan signal from the gate driver to the gate electrode 106 of the NMOS TFT. The data line supplies the video signal to the source electrode 108 of the NMOS TFT from the data driver. The gate line and the data line cross each other to form a pixel area.

The NMOS TFT 130 charges the video signal to the pixel electrode (not shown). To this end, the NMOS TFT includes a gate electrode 106 connected to the gate line, a source electrode 108 included in the data line, a drain electrode 110 connected to the pixel electrode through a pixel contact hole penetrating through the passivation layer, and a gate electrode. And an active layer 114 forming a channel between the source electrode 108 and the drain electrode 110 by 106.

The active layer 114 is formed on the lower substrate 101 with the buffer layer 116 interposed therebetween. The gate electrode 106 connected to the gate line is formed to overlap the channel region 114C of the active layer 114 and the gate insulating layer 112 therebetween. The source electrode 108 and the drain electrode 110 are formed to be insulated with the gate electrode 106 and the interlayer insulating layer 126 interposed therebetween. The source electrode 108 and the drain electrode 110 included in the data line 104 may have a source contact hole 124S and a drain contact hole 124D passing through the interlayer insulating layer 126 and the gate insulating layer 112. The n + impurity is connected to each of the source region 114S and the drain region 114D through each of them. In addition, the active layer 114 may include first and second lightly doped drains (LDDs) in which n− impurities are implanted between the channel region 114C and the source and drain regions 114S and 114D to reduce the off current. ) Further comprises an area.

The pixel electrode (not shown) extends and is connected to the drain electrode 110 of the NMOS TFT through the pixel contact hole 120 and is formed on an organic passivation layer (not shown) applied to the entire surface of the substrate 101. The pixel electrode (not shown) is formed of a transparent conductive film.

The storage capacitor Cst serves to suppress a voltage variation of the pixel electrode 122. The storage capacitor Cst is formed by overlapping the storage upper electrode 208 with the gate insulating layer 112 interposed between the storage lower electrode 234 made of an LTPS thin film doped with n + impurities and extending from the active layer 114. . In other words, the storage upper electrode 208 is formed in the hole 218 and overlaps the storage lower electrode 234 with the gate insulating layer 112 interposed therebetween. The storage upper electrode 208 is connected to the storage line 206 through the storage contact hole 224 penetrating the interlayer insulating layer 126. Accordingly, the storage line 206 connected to the storage upper electrode 208 supplies the storage voltage to the storage upper electrode 208. The storage line 206 is formed of the same electrode as the gate electrodes 106 and 146, and the storage upper electrode 208 is formed of the same metal layer as the source and drain electrodes 108, 110, 158 and 160.

Meanwhile, the storage channel region 214C overlaps the storage line 206 with the gate insulating layer 112 interposed therebetween, and the storage LED region 214L is between the storage channel region 214C and the storage lower electrode 234. Is formed. At this time, by forming the storage line 206 thin, n- impurity is injected into the storage LED region 214L and n + impurity is simultaneously injected into the storage lower electrode 234 during the n- and n + impurity doping process in the active layer 114. This eliminates the need for additional processing. In addition, the region of the hole 218 where the storage lower electrode 234 is formed may be formed in one mask process using a halftone mask or a diffraction exposure mask when forming the contact holes of the NMOS TFT and the PMOS TFT. Accordingly, since the number of mask processes is reduced, the process can be simplified and manufacturing cost can be reduced.

The NMOS TFT and PMOS TFT in the driving circuit region will be described. The NMOS TFT of the drive circuit has the same configuration as the NMOS TFT of the display area described above. The PMOS TFT includes an active layer 134 formed on the buffer layer 116 on the substrate 101 and a gate electrode overlapping the channel region 134C of the active layer 134 with the gate insulating layer 112 therebetween. 146 and a source electrode 158 and a drain respectively connected to the source region 134S and the drain region 134D of the active layer 134 through the contact holes 154C and 154D passing through the interlayer insulating layer 126, respectively. An electrode 160 is provided. The source region 134S and the drain region 134D of the active layer 114 of the PMOS TFT are formed by doping P + impurities.

2 to 9 are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

2 is a cross-sectional view for describing a first mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present disclosure.

As illustrated in FIG. 2, a buffer film 116 is formed on the lower substrate 101, and an active layer 514 of the display area and the driving circuit area is formed on the lower substrate 101.

In detail, the buffer layer 116 is formed by depositing an inorganic insulating material such as SiO ₂ on the lower substrate 101. The buffer layer 116 is formed by depositing an inorganic insulating material such as SiO ₂ on the lower substrate 101. The active layer 514 deposits amorphous silicon on the buffer film 216 and crystallizes the amorphous silicon with a laser to become poly-silicon, and then the poly-silicon is subjected to a photolithography process using a first mask. And patterning in the etching process to form the display area and the driving circuit area.

3 is a cross-sectional view illustrating a second mask process in the method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 4A to 4C are cross-sectional views illustrating a second mask process of the present invention in detail.

Referring to FIG. 3, the conductive layer 506 is formed on the lower substrate 101 on which the buffer layer 116 and the active layer 514 are formed, and the gate line and the gate metal 146 are formed in the region where the PMOS TFT is to be formed. The first conductive pattern group including the source and drain regions 134S and 134D doped with p + impurities are formed in the active layer 514.

In detail, as illustrated in FIG. 4A, the gate insulating layer 112 and the gate metal layer 512 are formed on the lower substrate 101 on which the buffer layer 116 and the active layer 514 are formed. The gate insulating layer 112 is formed by depositing an inorganic insulating material such as SiO ₂ on the buffer layer 116 and the active layer 514 by PECVD. Subsequently, the gate metal layer 512 is formed on the gate insulating layer 112 by a deposition method such as a sputtering method. As the gate metal layer 512, molybdenum (Mo), aluminum (Al), chromium (Cr), or an alloy thereof is stacked and used. As shown in FIG. 4B, the gate metal layer is patterned by a photolithography process and an etching process using a second mask process to form a first conductive pattern group including a gate metal 146 and a gate line in a region where a PMOS TFT is to be formed. The conductive layer 506 is also formed in the NMOS TFT and the storage region. At this time, the photoresist pattern 518 is removed by a strip process. As shown in FIG. 4C, the source layer 134S and the drain region 134D doped with impurities are formed by doping the p + impurity into the active layer 134 of the region where the PMOS TFT is to be formed.

5 is a cross-sectional view illustrating a third mask process in the method of manufacturing the thin film transistor substrate according to the embodiment, and FIGS. 6A and 6B are cross-sectional views illustrating the third mask process of the present invention in detail.

Referring to FIG. 5, source and drain regions 114S and 114D, first and second LED regions 114L1 and 114L2 doped with n + impurities in an active layer of a region where an NMOS TFT is to be formed by a third mask process, The storage LED area 214L is formed. A second conductive pattern group including the gate line and the gate electrode 106, the storage line 206, and the storage lower electrode 234 of the NMOS TFT is formed.

Specifically, as shown in FIG. 5, the conductive layer is patterned by a photolithography process and an etching process using a third mask, so that the gate electrode 106 and the gate line are formed in the NMOS TFT region, and the storage line 206 is formed in the storage region. A second conductive pattern group containing is formed. At this time, as shown in FIG. 6B, n + and n− impurities are implanted into the active layer 514 of the NMOS TFT region and the storage region through the exposed region by removing the photoresist pattern from the NMOS TFT region and the storage region. Accordingly, the source region 114S and the drain region 114D and the storage lower electrode 234 doped with n + impurity are formed, and the first and second LED regions 114L1 and 114L2 doped with n− impurity are formed. The storage LED area 214L is formed. At this time, the photoresist pattern 520 is removed by a strip process.

FIG. 7 is a cross-sectional view illustrating a fourth mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 8A to 8D are cross-sectional views illustrating a fourth mask process of the present invention in detail.

Referring to FIG. 7, an interlayer insulating layer including a plurality of contact holes 124S, 124D, 154S, and 154D of NMOS TFTs and PMOS TFTs, holes 218 of a storage area, and storage contact holes 224 in a fourth mask process. 126 is formed.

Specifically, as shown in FIG. 8A, the interlayer insulating layer 126 is formed by depositing an inorganic insulating material such as SiO ₂ on the gate insulating layer 112 and the first and second conductive pattern groups.

Subsequently, a photoresist is applied on the interlayer insulating layer 126, and then the photoresist is exposed and developed by a photolithography process using a halftone mask or a slit mask, thereby forming first and second layers having different thicknesses as shown in FIG. 8B. 2 photoresist patterns 312 and 314 are formed.

Specifically, the halftone mask includes a blocking region S31 having a blocking layer formed on a quartz substrate, a semi-transmissive region S32 having a partially transmitting layer formed on a quartz substrate, and a transmitting region S33 having only a quartz substrate. Equipped. The blocking region S31 is positioned in a region corresponding to the first and second conductive pattern groups to block ultraviolet rays during the exposure process, thereby leaving the first photoresist pattern 312 as shown in FIG. 8B after the developing process. The transflective region S32 is positioned in the region where the storage hole is to be formed and partially transmits ultraviolet rays, so that the second photoresist pattern thinner than the first photoresist pattern 312 as shown in FIG. 314) remains. The transmissive region S33 is positioned in a region where a plurality of contact holes and storage contact holes of the NMOS TFT and the PMOS TFT are to be formed and transmits all ultraviolet rays, thereby removing the photoresist as shown in FIG. 8B.

As shown in FIG. 8C, a portion of the interlayer insulating layer exposed by the first etching process using the first and second photoresist patterns 312 and 314 as a mask is patterned. In addition, as illustrated in FIG. 8C, the thickness of the first photoresist pattern 312 is reduced by the ashing process using an oxygen (O ₂ ) plasma, and the second photoresist pattern 314 is removed. Then, as shown in FIG. 8D, the interlayer insulating layer 126 and the gate insulating layer 112 exposed by the second etching process using the ashed first photoresist pattern 312 as a mask are removed. Accordingly, source and drain contact holes 112S, 112D, which penetrate the interlayer insulating layer 126 and the gate insulating layer 112 to expose the source and drain regions 114S, 114D, 134S, and 134D of the active layer 114, respectively. 154S and 154D are formed. In addition, the storage hole 218 of the storage area is formed through the interlayer insulating layer 126.

9 is a cross-sectional view for describing a fifth mask process in the method of manufacturing the thin film transistor substrate according to the embodiment.

9, a third conductive pattern group including source electrodes 108 and 158, drain electrodes 110 and 160, and a storage upper electrode 208 is formed on the interlayer insulating layer.

Specifically, the third conductive pattern group is formed by forming a source / drain metal layer on the interlayer insulating film 126 and then patterning the source / drain metal layer by a photolithography process and an etching process.

The source electrodes 108 and 158 and the drain electrodes 110 and 160 are connected to the source and drain regions 114S and 134S and the drain regions 114D and 134D of the active layers 114 and 134 through the source and drain contact holes 124S, 124D, 154S and 154D, respectively. It is connected with each. In addition, the storage upper electrode 208 is connected to the storage line 206 through the storage contact hole 224.

On the other hand, a protective film is formed on the NMOS TFT and the storage upper electrode in the NMOS TFT and the storage area included in the display area, a pixel contact hole penetrating the protective film is formed, and a fourth conductive pattern group including the pixel electrode is formed. It may further include.

As described above, the method of manufacturing the thin film transistor substrate according to the present invention can simplify the process by simultaneously performing an impurity doping process on the active layer of the TFT and the lower storage electrode included in the storage capacitor. As a result, productivity can be improved and manufacturing costs can be reduced by simplifying the process.

In addition, the storage bottom electrode, the source and the drain electrode may be simultaneously formed using the halftone mask.

Although the detailed description of the present invention described above has been described with reference to a preferred embodiment of the present invention, those skilled in the art or those skilled in the art, those skilled in the art, described in the claims below It will be understood that various modifications and changes can be made in the present invention without departing from the spirit and scope of the invention.

Claims (7)

Forming a polysilicon layer patterned into first and second regions on the substrate; Forming a gate insulating film on the polysilicon layers of the first and second regions; Forming a first conductive metal pattern and a conductive layer including a source and a drain region doped with a first impurity in the polysilicon layer of the first region and a first gate electrode on the gate insulating layer; A source and drain region doped with a second impurity in the polysilicon layer of the second region, a storage lower electrode formed by extending a portion of the polysilicon layer, and the conductive layer is patterned to include a storage line and a second gate electrode Forming a second conductive metal pattern; Forming an interlayer insulating layer on the first and second metal patterns, the interlayer insulating layer including a plurality of contact holes included in the storage contact hole, the storage hole, the source and the drain contact hole; And forming source and drain electrodes in the storage contact hole, the storage upper electrode, the source and drain contact holes on the storage hole. The method of claim 1, And a second impurity in the polysilicon layer of the second region is simultaneously doped into the source region, the drain region and the storage lower electrode. The method of claim 1, And the first impurity is doped with p impurity. The method of claim 1, The source and drain regions doped with the second impurity are doped with n + impurities. The method of claim 4, wherein And doping the n- impurity to the source and drain regions doped with the second impurity to further include first and second LED regions. The method of claim 1, Forming an interlayer insulating layer including a plurality of contact holes included in the storage contact hole, the storage hole, the source and the drain contact hole on the first and second metal patterns; Forming first and second photoresist patterns having different thicknesses on the interlayer insulating film; Removing a portion of the interlayer insulating layer by a first etching process using the first and second photoresist patterns as a mask; Ashing the first and second photoresist patterns to remove the second photoresist pattern thinner than the first photoresist pattern; Removing the interlayer insulating film and the gate insulating film by a second etching process using the first photoresist pattern as a mask to form a storage hole, a storage contact hole, a source and a drain contact hole; And removing the first photoresist pattern by a strip process. The method of claim 1, And forming the same electrode as the source and drain electrodes and the storage upper electrode.

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