KR20050067740A - Method for fabricating tft-lcd - Google Patents
Method for fabricating tft-lcd Download PDFInfo
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- KR20050067740A KR20050067740A KR1020030098754A KR20030098754A KR20050067740A KR 20050067740 A KR20050067740 A KR 20050067740A KR 1020030098754 A KR1020030098754 A KR 1020030098754A KR 20030098754 A KR20030098754 A KR 20030098754A KR 20050067740 A KR20050067740 A KR 20050067740A
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000010408 film Substances 0.000 claims abstract description 36
- 239000010409 thin film Substances 0.000 claims abstract description 34
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 238000002161 passivation Methods 0.000 claims abstract 3
- 239000007789 gas Substances 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 6
- 239000012495 reaction gas Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 68
- 239000004065 semiconductor Substances 0.000 description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 description 18
- 238000005530 etching Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 230000035484 reaction time Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
Abstract
본 발명은 BCE(Back Channel Etch)타입 박막트랜지스터 액정표시장치에 있어서, 채널영역에 해당되는 오믹콘택층 부위에 BCE공정 대신 산화공정을 진행시켜 절연체화하여 소오스전극과 드레인전극을 분리시키는 박막트랜지스터 액정표시장치의 제조방법에 관해 개시한 것으로서, 절연기판에 게이트전극을 형성하는 단계와, 기판 상에 상기 게이트전극을 덮는 게이트절연막을 형성하는 단계와, 게이트절연막 위에 상기 게이트전극과 대응되는 부위에 잔류되도록 동일형상의 패턴을 가지는 활성층 및 오믹콘택층을 형성하는 단계와, 결과물 위에 상기 오믹콘택층에 각각 연결되는 소오스전극 및 드레인전극을 형성하는 단계와, 소오스전극 및 드레인전극에 의해 노출된 오믹콘택층 부위에 산화공정을 진행하여 절연막을 형성하는 단계와, 상기 구조 전면에 상기 드레인전극을 노출시키는 콘택홀을 가진 보호막을 형성하는 단계와, 보호막 상에 상기 콘택홀을 덮어 상기 드레인전극과 연결되는 화소전극을 형성하는 단계를 포함한다.The present invention provides a thin film transistor liquid crystal display which insulates the source electrode and the drain electrode by performing an oxidation process instead of the BCE process in the ohmic contact layer corresponding to the channel region. A method of manufacturing a display device, the method comprising: forming a gate electrode on an insulating substrate, forming a gate insulating film covering the gate electrode on a substrate, and remaining on a portion corresponding to the gate electrode on the gate insulating film. Forming an active layer and an ohmic contact layer having a pattern of the same shape, forming a source electrode and a drain electrode respectively connected to the ohmic contact layer on the resultant, and an ohmic contact exposed by the source electrode and the drain electrode Performing an oxidation process on the layer part to form an insulating film, Forming a passivation layer having a contact hole exposing the drain electrode, and forming a pixel electrode connected to the drain electrode by covering the contact hole on the passivation layer.
Description
본 발명은 박막트랜지스터 액정표시장치의 제조방법에 관한 것으로, 보다 구체적으로는 BCE(Back Channel Etch)타입 박막트랜지스터 액정표시장치에 있어서, 채널영역에 해당되는 오믹콘택층 부위에 BCE공정 대신 산화공정을 진행시켜 절연체화하여 소오스전극과 드레인전극을 분리시키는 박막트랜지스터 액정표시장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device. More specifically, in a back channel etching (BCE) type thin film transistor liquid crystal display device, an oxidation process is applied to an area of an ohmic contact layer corresponding to a channel region instead of a BCE process. The present invention relates to a method of manufacturing a thin film transistor liquid crystal display device which is insulated to separate source and drain electrodes.
액정표시소자는 CRT(Cathod-ray tube)를 대신하여 개발되어져 왔다. 특히, 각 화소마다 스위칭 소자로서 박막 트랜지스터가 구비되는 박막트랜지스터 액정표시장치는 CRT에 필적할만한 화면의 고화질화, 대형화 및 컬러화 등을 실현하였으며, 최근에 들어서는, 노트북 PC 및 모니터 시장에서 크게 각광 받고 있다. Liquid crystal displays have been developed in place of the CRT (Cathod-ray tube). In particular, a thin film transistor liquid crystal display device having a thin film transistor as a switching element for each pixel realizes high quality, large size, and color screen comparable to a CRT. Recently, the thin film transistor liquid crystal display device has been attracting much attention in the notebook PC and monitor market.
이와 같은 박막트랜지스터 액정표시장치는 개략적으로 박막트랜지스터 및 화소전극이 구비된 어레이 기판과, 컬러필터 및 상대전극이 구비된 컬러필터 기판이 액정층의 개재하에 합착된 구조를 갖는다. Such a thin film transistor liquid crystal display device has a structure in which an array substrate including a thin film transistor and a pixel electrode, and a color filter substrate including a color filter and a counter electrode are bonded to each other under a liquid crystal layer.
한편, 이와 같은 박막트랜지스터 액정표시장치를 제조함에 있어서, 그 제조 공정 수, 특히, 상기 어레이 기판의 제조 공정수를 감소시키는 것은 매우 중요하다. 왜냐하면, 제조공정 수를 감소시킬수록 박막트랜지스터 액정표시장치의 제조 비용 및 시간을 감소시킬 수 있고, 그래서, 더 저렴한 값에 보다 많은 양의 박막트랜지스터 액정표시장치를 보급할 수 있기 때문이다. On the other hand, in manufacturing such a thin film transistor liquid crystal display device, it is very important to reduce the number of manufacturing steps, in particular, the number of manufacturing steps of the array substrate. This is because, as the number of manufacturing processes is reduced, the manufacturing cost and time of the thin film transistor liquid crystal display device can be reduced, so that a larger amount of thin film transistor liquid crystal display device can be supplied at a lower cost.
여기서, 제조 공정수의 감소는 마스크 수의 감소에 의해 실현되며, 통상의 어레이 기판은 7-마스크 공정을 통해 양산되어 왔으나, 최근에는 BCE(Back Channel Etch)기술을 적용한 5-마스크 공정을 통해 양산되고 있다.Here, the reduction in the number of manufacturing processes is realized by the reduction in the number of masks, and conventional array substrates have been mass-produced through a 7-mask process, but recently mass-produced through a 5-mask process using BCE (Back Channel Etch) technology It is becoming.
도 1a 내지 도 1c는 종래기술에 따른 BCE 타입 박막트랜지스터 액정표시장치의 제조방법을 설명하기 위한 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a BCE type thin film transistor liquid crystal display device according to the related art.
종래기술에 따른 BCE타입 박막트랜지스터 액정표시장치의 제조방법은, 도 1a에 도시된 바와 같이, 투명성 절연기판인 유리기판(1)의 적소에 게이트전극(3)을 형성하고, 그 위에 게이트 절연막(5)과 반도체층(a-Si)(미도시)과 도핑된 반도체층(n+a-Si)(미도시)을 연속적으로 형성한다. 이때, 상기 반도체층(a-Si)은 1700∼2000Å두께로 형성한다. 또한, 상기 도핑된 반도체층(n+a-Si)은 PECVD(Plasma Enhanced Chemical Vapor Deposition)방법으로 증착하며, 양호한 오믹(ohmic)특성을 얻기 위해 증착 시에 인(phosphorus)을 도핑한다. 여기서, 상기 도핑된 반도체층(n+a-Si)은 이후의 공정을 거쳐 오믹콘택층이 되며, 상기 오믹콘택층이 양호한 오믹접촉을 해야 박막 트랜지스터 구동 시 전류가 누설되지 않으며, 박막 트랜지스터의 동작특성이 향상된다.In the method of manufacturing a BCE type thin film transistor liquid crystal display device according to the related art, as shown in FIG. 1A, a gate electrode 3 is formed in place of a glass substrate 1, which is a transparent insulating substrate, and a gate insulating film is formed thereon. 5) and the semiconductor layer a-Si (not shown) and the doped semiconductor layer n + a-Si (not shown) are formed successively. At this time, the semiconductor layer (a-Si) is formed to a thickness of 1700 ~ 2000Å. In addition, the doped semiconductor layer (n + a-Si) is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) and doped with phosphorus during deposition to obtain good ohmic properties. Here, the doped semiconductor layer n + a-Si becomes an ohmic contact layer through a subsequent process, and when the ohmic contact layer has good ohmic contact, current does not leak when driving the thin film transistor, and the thin film transistor operates. Characteristics are improved.
그 다음, 도핑된 반도체층(n+ a-Si) 및 반도체층(a-Si)을 사진식각공정에 의하여 동시에 패터닝하여 오믹콘택층(9) 및 활성층(7)을 형성한다. Then, the doped semiconductor layer (n + a-Si) and the semiconductor layer (a-Si) are simultaneously patterned by a photolithography process to form the ohmic contact layer 9 and the active layer 7.
이후, 도 1b에 도시된 바와 같이, 상기 활성층(7)을 포함한 기판 전면에 소오스/드레인 전극을 형성하기 위한 도전층(미도시)을 형성하고 나서, 상기 도전층 위에 소오스전극 및 드레인전극영역을 덮는 감광막패턴(17)을 형성한다. 이어, 상기 감광막패턴(17)을 마스크로 하여 상기 도전층을 식각하여 소오스전극(11S)과 드레인전극(11D)을 형성한다. 다시, 상기 감광막패턴(17)을 마스크로하여 그 하단에 있는 오믹콘택층을 RIE(Reactive Ion Etch) 또는 PE(Plasma Etch) 등의 건식식각방법으로 소오스전극(15S)과 드레인전극(15D)의 사이의 활성층(7)의 채널영역에 해당되는 오믹콘택층 부분을 제거한다. 여기서, 상기 채널영역에 해당되는 오믹콘택층을 식각하는 것을 BCE라 한다. Thereafter, as shown in FIG. 1B, a conductive layer (not shown) for forming a source / drain electrode is formed on the entire surface of the substrate including the active layer 7, and then a source electrode and a drain electrode region are formed on the conductive layer. A covering photoresist pattern 17 is formed. Subsequently, the conductive layer is etched using the photoresist pattern 17 as a mask to form a source electrode 11S and a drain electrode 11D. Again, the ohmic contact layer at the bottom of the photoresist pattern 17 as a mask is used to dry the source electrode 15S and the drain electrode 15D by a dry etching method such as reactive ion etching (RIE) or plasma etching (PE). The portion of the ohmic contact layer corresponding to the channel region of the active layer 7 is removed. The etching of the ohmic contact layer corresponding to the channel region is referred to as BCE.
한편, 이 과정에서 활성층(7)의 채널영역이 노출되며, 상기 식각공정에서 오믹콘택층(9)뿐만 아니라 오믹콘택층(9) 하부의 활성층(7)도 일부 식각되어 최종적으로 식각 후 잔류되는 활성층(7) 두께는 1200Å이 된다.Meanwhile, in this process, the channel region of the active layer 7 is exposed, and in the etching process, not only the ohmic contact layer 9 but also the active layer 7 under the ohmic contact layer 9 is partially etched and finally remains after etching. The thickness of the active layer 7 is 1200 kPa.
그런다음, 감광막패턴을 제거하고 나서, 도 1c에 도시된 바와같이, 상기 노출된 기판 전면에 PECVD에 의한 증착기술에 의하여 절연물질을 증착하여 보호막(13)을 형성한다. 이후, 상기 보호막(13)을 선택식각하여 드레인전극(11D)의 일부를 노출시키는 콘택홀(13a)을 형성한다. 이어, 상기 결과물 전면에 ITO 등의 투명도전층(미도시)을 형성한 후, 투명도전층을 사진식각공정에 의하여 패터닝하여 콘택홀(13a)을 매립시켜 드레인전극(11D)과 연결되는 화소전극(15)을 형성한다.Then, after removing the photoresist pattern, as shown in FIG. 1C, an insulating material is deposited on the entire surface of the exposed substrate by PECVD to form a protective film 13. Thereafter, the protective layer 13 is selectively etched to form a contact hole 13a exposing a part of the drain electrode 11D. Subsequently, a transparent conductive layer (not shown) such as ITO is formed on the entire surface of the resultant, and then the transparent conductive layer is patterned by a photolithography process to fill the contact hole 13a to connect the pixel electrode 15 to the drain electrode 11D. ).
그러나, 종래의 기술에서는 활성층의 채널영역을 노출시키도록 오믹콘택층 을 건식식각 시에 발생하는 강한 전계에 의해 이온이 가속되며, 이러한 가속된 이온충격(ion bambardment)에 의해 도핑된 반도체층 및 반도체층에 2000Å 두께로 데미지(damage)를 주게된다. 이러한 데미지에 의해 오프특성을 향상시키기가 어려운 문제점이 있다. However, in the related art, ions are accelerated by a strong electric field generated during dry etching of the ohmic contact layer to expose the channel region of the active layer, and the semiconductor layer and semiconductor doped by this accelerated ion bambardment Damage to the layer is 2000 microns thick. There is a problem that it is difficult to improve the off characteristics by such damage.
또한, 기존의 7-마스크 공정에서는 반도체층(a-Si)을 500Å두께로 형성하여 양호한 박막 트랜지스터 특성을 구현하였으나, BCE타입의 5-마스크공정에서는 이후의 오믹콘택층 식각공정에서 반도체층도 소정두께가 식각되므로, 반도체층(a-Si)을 500Å보다 두꺼운 1700∼2000Å로 형성해야 한다. 이때, 상기 BCE타입의 5-마스크공정에서는 고가의 건식식각장비를 이용하여 채널영역의 오믹콘택층을 식각해야 하는 공정을 수행한다. 따라서, 공정이 복잡해지고, 박막 트랜지스터 특성 저하 및 반도체층(a-Si)두께 증가에 의한 장비 가동율이 저하되는 문제점도 있다.In addition, in the conventional 7-mask process, the semiconductor layer (a-Si) is formed to have a thickness of 500 Å to realize good thin film transistor characteristics. However, in the 5-mask process of the BCE type, the semiconductor layer is also prescribed in the subsequent ohmic contact layer etching process. Since the thickness is etched, the semiconductor layer (a-Si) should be formed to be 1700 to 2000 GPa thicker than 500 GPa. At this time, in the BCE type 5-mask process, an ohmic contact layer of a channel region is etched using an expensive dry etching equipment. Therefore, there is a problem in that the process becomes complicated and the equipment operation rate decreases due to the decrease in thin film transistor characteristics and the increase in the thickness of the semiconductor layer (a-Si).
상기 문제점을 해결하고자, 본 발명의 목적은 BCE(Back Channel Etch)타입 박막트랜지스터 액정표시장치에 있어서, 채널영역에 해당되는 오믹콘택층 부위를 산화시켜 절연체화하여 소오스전극과 드레인전극을 분리시킴으로써, BCE공정을 생략할 수 있어 공정을 단순화시키고, 뿐만 아니라 BCE공정에 따른 식각데미지를 최소화시켜 박막트랜지스터 특성을 향상시킬 수 있는 박막트랜지스터 액정표시장치의 제조방법을 제공하려는 것이다.In order to solve the above problems, an object of the present invention is to provide a back channel etching (BCE) type thin film transistor liquid crystal display device by oxidizing and insulating an ohmic contact layer corresponding to a channel region to separate an source electrode and a drain electrode, Since the BCE process can be omitted, the present invention is to provide a method of manufacturing a thin film transistor liquid crystal display device which can simplify the process and minimize the etching damage caused by the BCE process to improve the thin film transistor characteristics.
상기 목적을 달성하고자, 본 발명의 박막트랜지스터 액정표시장치의 제조방법은 절연기판에 게이트전극을 형성하는 단계와, 기판 상에 상기 게이트전극을 덮는 게이트절연막을 형성하는 단계와, 게이트절연막 위에 상기 게이트전극과 대응되는 부위에 잔류되도록 동일형상의 패턴을 가지는 활성층 및 오믹콘택층을 형성하는 단계와, 결과물 위에 상기 오믹콘택층에 각각 연결되는 소오스전극 및 드레인전극을 형성하는 단계와, 소오스전극 및 드레인전극에 의해 노출된 오믹콘택층 부위에 산화공정을 진행하여 절연막을 형성하는 단계와, 상기 구조 전면에 상기 드레인전극을 노출시키는 콘택홀을 가진 보호막을 형성하는 단계와, 보호막 상에 상기 콘택홀을 덮어 상기 드레인전극과 연결되는 화소전극을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a thin film transistor liquid crystal display device of the present invention comprises the steps of forming a gate electrode on an insulating substrate, forming a gate insulating film covering the gate electrode on a substrate, and the gate on the gate insulating film Forming an active layer and an ohmic contact layer having the same shape pattern so as to remain in a portion corresponding to the electrode, forming a source electrode and a drain electrode respectively connected to the ohmic contact layer on the resultant; Forming an insulating film by performing an oxidation process on the portion of the ohmic contact layer exposed by the electrode, forming a protective film having a contact hole exposing the drain electrode on the entire surface of the structure, and forming the contact hole on the protective film. Forming a pixel electrode overlying and connected to the drain electrode; .
상기 활성층은 500Å두께로 형성한다.The active layer is formed to a thickness of 500 kPa.
상기 절연막은 산화막 및 질화막 중 어느 하나를 이용한다.The insulating film uses any one of an oxide film and a nitride film.
상기 산화막은 반응가스로 O2, O2 /N2혼합가스, O2/N2O혼합가스, O2/NH2혼합가스 또는 N2O 중 어느하나를 공급하여 형성한다.The oxide film is formed by supplying any one of O2, O2 / N2 mixed gas, O2 / N2O mixed gas, O2 / NH2 mixed gas, or N2O as a reaction gas.
상기 질화막은 반응가스로 NH3/N2가스를 공급하여 형성한다.The nitride film is formed by supplying NH 3 / N 2 gas as a reaction gas.
(실시예)(Example)
이하, 첨부된 도면을 참고로하여 본 발명에 따른 박막트랜지스터 액정표시장치의 제조방법을 설명하기로 한다.Hereinafter, a method of manufacturing a thin film transistor liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 박막트랜지스터 액정표시장치의 제조방법을 설명하기 위한 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention.
본 발명에 따른 박막트랜지스터 액정표시장치의 제조방법은, 도 2a에 도시된 바와 같이, 투명성 절연기판인 유리기판(21)의 적소에 게이트전극(23)을 형성하고, 그 위에 게이트 절연막(25)과 반도체층(a-Si)(미도시)과 도핑된 반도체층(n+a-Si)(미도시)을 연속적으로 형성한다. 본 발명에서는 별도의 오믹콘택층 식각공정이 진행되지 않으므로, 상기 반도체층(a-Si)을 5-마스크 공정과 동일하게 500Å두께로 형성한다. 또한, 상기 도핑된 반도체층(n+a-Si)은 PECVD방법으로 증착하며, 증착 시 양호한 오믹(ohmic)특성을 얻기 위해 인을 도핑한다. 여기서, 상기 도핑된 반도체층(n+a-Si)은 이후의 공정을 거쳐 오믹콘택층이 되며, 상기 오믹콘택층이 양호한 오믹접촉을 해야 박막 트랜지스터 구동 시 전류가 누설되지 않으며, 박막 트랜지스터의 동작특성이 향상되기 때문에 인 등의 불순물을 도핑하는 것이다.In the method of manufacturing the thin film transistor liquid crystal display device according to the present invention, as shown in FIG. 2A, the gate electrode 23 is formed in place on the glass substrate 21, which is a transparent insulating substrate, and the gate insulating film 25 is formed thereon. And a semiconductor layer (a-Si) (not shown) and a doped semiconductor layer (n + a-Si) (not shown) are successively formed. In the present invention, since no additional ohmic contact layer etching process is performed, the semiconductor layer (a-Si) is formed to have a thickness of 500 kV in the same manner as the 5-mask process. In addition, the doped semiconductor layer (n + a-Si) is deposited by PECVD, and doped with phosphorus to obtain good ohmic characteristics during deposition. Here, the doped semiconductor layer n + a-Si becomes an ohmic contact layer through a subsequent process, and when the ohmic contact layer has good ohmic contact, current does not leak when driving the thin film transistor, and the thin film transistor operates. Since the properties are improved, doping of impurities such as phosphorus is performed.
이어, 도핑된 반도체층(n+ a-Si) 및 반도체층(n+ a-Si)을 사진식각공정에 의하여 동시에 패터닝하여 오믹콘택층(29) 및 활성층(27)을 형성한다. Subsequently, the doped semiconductor layer (n + a-Si) and the semiconductor layer (n + a-Si) are simultaneously patterned by a photolithography process to form an ohmic contact layer 29 and an active layer 27.
이후, 도 2b에 도시된 바와 같이, 상기 활성층(27)을 포함한 기판 전면에 소오스/드레인 전극을 형성하기 위한 도전층(미도시)을 형성하고 나서, 상기 도전층위에 감광막을 도포하고 노광 및 현상하여 소오스전극 및 드레인전극영역을 덮는 감광막패턴(37)을 형성한다. 이어, 상기 감광막패턴(37)을 마스크로 하여 도전층을 식각하여 소오스전극(31S)과 드레인전극(31D)을 형성한다. Thereafter, as shown in FIG. 2B, a conductive layer (not shown) for forming a source / drain electrode is formed on the entire surface of the substrate including the active layer 27, and then a photosensitive film is coated on the conductive layer and exposed and developed. The photosensitive film pattern 37 is formed to cover the source electrode and the drain electrode region. Subsequently, the conductive layer is etched using the photoresist pattern 37 as a mask to form a source electrode 31S and a drain electrode 31D.
그런다음, 상기 감광막패턴(37)을 제거하고 나서, 도 2c에 도시된 바와 같이, 소오스전극(31S)과 드레인전극(31D)에 의해 노출된 오믹콘택층(29)에 산화공정(40)을 진행하여 절연막(30)을 형성한다. 이때, 상기 산화공정(40)은 PECVD, RIE 또는 PE 장비를 이용하며, 절연막(30)으로는 산화막(SiON) 또는 질화막(SiN)을 이용한다.Then, after the photoresist pattern 37 is removed, an oxidation process 40 is performed on the ohmic contact layer 29 exposed by the source electrode 31S and the drain electrode 31D, as shown in FIG. 2C. Proceeding to form the insulating film 30. In this case, the oxidation process 40 uses PECVD, RIE, or PE equipment, and uses an oxide film (SiON) or a nitride film (SiN) as the insulating film 30.
상기 산화막(SiON)의 형성공정을 알아보면, 반응가스로 O2, O2 /N2혼합가스, O2/N2O혼합가스, O2/NH2혼합가스 또는 N2O 중 어느하나를 공급하면서, 상기 산화공정을 진행하기 위한 장비 내의 파워, 온도 및 반응시간을 적절히 조절하면서 진행한다. 상기 질화막(SiN) 형성공정은 반응가스로 NH3/N2가스를 공급하며, 마찬가지로, 장비 내의 파워, 온도 및 반응시간을 적절히 조절하면서 진행한다.Looking at the formation process of the oxide film (SiON), while supplying any one of O2, O2 / N2 mixed gas, O2 / N2O mixed gas, O2 / NH2 mixed gas or N2O as a reaction gas, to proceed with the oxidation process Proceed with proper adjustment of power, temperature and reaction time in the equipment. The nitride film (SiN) forming process supplies NH 3 / N 2 gas as a reaction gas, and likewise proceeds with appropriate control of power, temperature and reaction time in the equipment.
이외에도, 상기 절연막(30)으로 열산화(thermal oxidation)공정에 의한 열산화막을 이용할 수도 있다.In addition, a thermal oxidation film by a thermal oxidation process may be used as the insulating film 30.
한편, 상기 산화공정(40) 결과, 오믹콘택층(29) 뿐만 아니라 그 하부의 활성층(27)도 일부 산화되며, 이때, 최종적으로 잔류되는 활성층(27) 두께는 500Å이 된다.On the other hand, as a result of the oxidation process 40, not only the ohmic contact layer 29 but also the active layer 27 beneath it is partially oxidized. At this time, the thickness of the active layer 27 remaining finally becomes 500 kPa.
이후, 도 2d에 도시된 바와 같이, 상기 노출된 기판 전면에 PECVD에 의한 증착기술에 의하여 절연물질을 증착하여 보호막(23)을 형성한 다음, 상기 보호막(23)을 식식각하여 드레인전극(31D)의 일부를 노출시키는 콘택홀(33a)을 형성한다. 이어, 상기 결과물 전면에 ITO 등의 투명도전층(미도시)을 형성한 후, 투명도전층을 사진식각공정에 의하여 패터닝하여 콘택홀(33a)을 덮어켜 드레인전극(31D)과 연결되는 화소전극(35)을 형성한다.Thereafter, as shown in FIG. 2D, an insulating material is deposited on the entire surface of the exposed substrate by PECVD to form a protective film 23, and then the protective film 23 is etched to drain the drain electrode 31D. A contact hole 33a exposing a part of) is formed. Subsequently, after forming a transparent conductive layer (not shown) such as ITO on the entire surface of the resultant, the transparent conductive layer is patterned by a photolithography process to cover the contact hole 33a and connect the pixel electrode 35 to the drain electrode 31D. ).
이상에서와 같이, 본 발명은 BCE타입 박막트랜지스터 액정표시장치에 있어서, 채널영역에 해당되는 오믹콘택층 부위를 산화시켜 절연체화하여 소오스전극과 드레인전극을 분리시킴으로써, 기존의 BCE공정을 생략할 수 있어 제조공정이 단순화되며, 뿐만 아니라 BCE공정에 따른 식각데미지를 최소화시켜 박막트랜지스터 특성을 향상시킬 수 있다.As described above, in the BCE type thin film transistor liquid crystal display device, the conventional BCE process can be omitted by separating the source electrode and the drain electrode by oxidizing and insulating the ohmic contact layer corresponding to the channel region. Therefore, the manufacturing process is simplified, and the thin film transistor characteristics can be improved by minimizing the etching damage caused by the BCE process.
또한, 본 발명은 기존의 BCE공정을 생략가능함으로써, 반도체층(a-Si)의 두께를 최소화할 수 있으며, 고가의 건식식각장비가 불필요한 이점이 있다.In addition, the present invention can omit the existing BCE process, it is possible to minimize the thickness of the semiconductor layer (a-Si), there is an advantage that expensive dry etching equipment is unnecessary.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
도 1a 내지 도 1c는 종래기술에 따른 BCE 타입 박막트랜지스터 액정표시장치의 제조방법을 설명하기 위한 공정단면도.1A to 1C are cross-sectional views illustrating a method of manufacturing a BCE type thin film transistor liquid crystal display device according to the related art.
도 2a 내지 도 2d는 본 발명에 따른 BCE 타입 박막트랜지스터 액정표시장치의 제조방법을 설명하기 위한 공정단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a BCE type thin film transistor liquid crystal display device according to the present invention;
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| KR100759086B1 (en) * | 2007-02-23 | 2007-09-19 | 실리콘 디스플레이 (주) | Thin film transistor using part oxidation and method for manufacturing thereof |
| KR101294235B1 (en) * | 2008-02-15 | 2013-08-07 | 엘지디스플레이 주식회사 | Liquid Crystal Display Device and Method of Fabricating the same |
| US9391099B2 (en) | 2008-02-15 | 2016-07-12 | Lg Display Co., Ltd. | Array substrate and liquid crystal display module including TFT having improved mobility and method of fabricating the same |
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|---|---|---|---|---|
| CN102769039A (en) * | 2012-01-13 | 2012-11-07 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
| CN105097944A (en) * | 2015-06-25 | 2015-11-25 | 京东方科技集团股份有限公司 | Thin film transistor, fabrication method thereof, array substrate and display device |
-
2003
- 2003-12-29 KR KR1020030098754A patent/KR100687341B1/en active IP Right Grant
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100759086B1 (en) * | 2007-02-23 | 2007-09-19 | 실리콘 디스플레이 (주) | Thin film transistor using part oxidation and method for manufacturing thereof |
| KR101294235B1 (en) * | 2008-02-15 | 2013-08-07 | 엘지디스플레이 주식회사 | Liquid Crystal Display Device and Method of Fabricating the same |
| US9391099B2 (en) | 2008-02-15 | 2016-07-12 | Lg Display Co., Ltd. | Array substrate and liquid crystal display module including TFT having improved mobility and method of fabricating the same |
| US9881944B2 (en) | 2008-02-15 | 2018-01-30 | Lg Display Co., Ltd. | Array substrate and liquid crystal display module including TFT having improved mobility and method of fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100687341B1 (en) | 2007-02-27 |
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