CN102769039A - Thin film transistor, manufacturing method thereof, array substrate and display device - Google Patents
Thin film transistor, manufacturing method thereof, array substrate and display device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract
An embodiment of the invention provides a thin film transistor, a manufacturing method thereof, an array substrate and a display device, and relates to the technical field of manufacture of display devices. Characteristics of the thin film transistor are improved. The thin film transistor comprises a gate electrode, a gate insulating layer, a semiconductor active layer, an etched barrier layer and a source/drain electrode layer which are sequentially formed on a transparent substrate; a layered optimization scheme is adopted for the semiconductor active layer, so that a low-oxygen and high-conductivity semiconductor bottom layer and a high-oxygen and low-conductivity semiconductor top layer are formed; low off-state current Ioff and high on-state current Ion are realized; and influence to the semiconductor active layer is also reduced in a technological process owing to the layered optimization scheme. The thin film transistor with the structure, the array substrate with the structure and the display device driven by the thin film transistor and the array substrate are manufactured according to the embodiment of the invention.
Description
Technical field
The present invention relates to the display device manufacturing technology, relate in particular to thin-film transistor and manufacturing approach thereof, array base palte and display device.
Background technology
The initial research of OTFT (Oxide Thin Film Transistor, oxide thin film transistor) technology is in order to reduce the energy consumption of active display device, to make display device thinner lighter, the faster and technology of research and development of response speed.Begin to move towards the trial period about earlier 2000s greatly.
Fig. 1 is the structural representation of thin-film transistor in the prior art.Prior art forms grid 11, gate insulation layer 12, semiconductor active layer 13, etching barrier layer 14, source electrode 15a, drain electrode 15b, passivation layer 16 and pixel electrode 18 successively through 6 exposed masks (Mask) technology on glass substrate 10, drain electrode 15b is connected with pixel electrode 18 through via hole 17.Wherein, the manufacturing materials of semiconductor active layer 13 is selected metal oxide for use, such as materials such as indium gallium zinc oxide IGZO.
The performance of active layer has determined the characteristic of thin-film transistor; And possesses low off-state current Ioff when can't realize high ON state current Ion based on existing oxide thin film transistor shown in Figure 1; And then can't guarantee the performance of oxide thin film transistor finally to influence performance of products.
Summary of the invention
Embodiments of the invention provide a kind of thin-film transistor and manufacturing approach, array base palte and display device, possess low off-state current Ioff when realizing high ON state current Ion, improve the characteristic of thin-film transistor.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of thin-film transistor is provided, comprises: grid, gate insulation layer, semiconductor active layer, etching barrier layer, source/drain electrode layer; Wherein,
Said semiconductor active layer is a sandwich construction, comprises the semiconductor underlayer of low oxygen content and the semiconductor top layer of elevated oxygen level at least.
A kind of method of manufacturing thin film transistor is provided, comprises:
On transparency carrier, form the process of gate metal layer, gate insulation layer, semiconductor active layer, etching barrier layer, source/drain electrode layer; Wherein,
The process of said formation semiconductor active layer comprises:
Be formed with the semiconductor underlayer of making low oxygen content on the transparency carrier of gate insulation layer;
Be formed with the semiconductor top layer of making elevated oxygen level on the transparency carrier of said semiconductor underlayer.
A kind of array base palte is provided, comprises above-mentioned thin-film transistor.
A kind of display device is provided, comprises above-mentioned array base palte.
The embodiment of the invention provides a kind of thin-film transistor and manufacturing approach, array base palte and display device, on transparency carrier, forms gate metal layer, gate insulation layer, semiconductor active layer, etching barrier layer, source/drain electrode layer; Wherein, the forming process of semiconductor active layer comprises: layering prepares the semiconductor underlayer of low oxygen content and the semiconductor top layer of elevated oxygen level; Further; The semiconductor active layer that forms comprises two-layer and two-layer above structure; And its aim is that the bottom of semiconductor active layer is formed by the semiconductor layer of low oxygen content, high ducting capacity; Realize high ON state current Ion, the top layer of semiconductor active layer is formed by the semiconductor layer of elevated oxygen level, low ducting capacity, realizes low off-state current Ioff.Can realize low off-state current Ioff and high ON state current Ion simultaneously through the semiconductor active layer that adopts the hierarchy optimization preparation like this,, finally guarantee performance of products to improve the characteristic of oxide thin film transistor.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of thin-film transistor in the prior art;
The structural representation of the thin-film transistor that Fig. 2 provides for the embodiment of the invention;
The schematic flow sheet of the manufacturing array substrate that Fig. 3 provides for the embodiment of the invention;
Fig. 4 A is first sketch map of the array base palte manufacture process that provides of the embodiment of the invention;
Fig. 4 B is second sketch map of the manufacturing array substrate that provides of the embodiment of the invention;
Fig. 4 C is the 3rd sketch map of the manufacturing array substrate that provides of the embodiment of the invention;
Fig. 4 D is the 4th sketch map of the manufacturing array substrate that provides of the embodiment of the invention;
Fig. 4 E is the 5th sketch map of the manufacturing array substrate that provides of the embodiment of the invention;
Fig. 4 F is the 6th sketch map of the manufacturing array substrate that provides of the embodiment of the invention;
Fig. 4 G is the 7th sketch map of the manufacturing array substrate that provides of the embodiment of the invention;
Fig. 4 H is the 8th sketch map of the manufacturing array substrate that provides of the embodiment of the invention;
Fig. 4 I is the 9th sketch map of the manufacturing array substrate that provides of the embodiment of the invention;
Fig. 4 J is the tenth sketch map of the manufacturing array substrate that provides of the embodiment of the invention;
Fig. 4 K is the 11 sketch map of the manufacturing array substrate that provides of the embodiment of the invention;
Fig. 4 L is the 12 sketch map of the manufacturing array substrate that provides of the embodiment of the invention;
Fig. 4 M is the 13 sketch map of the manufacturing array substrate that provides of the embodiment of the invention;
The structural representation of the thin-film transistor that Fig. 5 provides for another embodiment of the present invention;
The schematic flow sheet of the manufacturing array substrate that Fig. 6 provides for another embodiment of the present invention;
Fig. 7 A is first sketch map of the manufacturing array substrate that provides of another embodiment of the present invention;
Fig. 7 B is second sketch map of the manufacturing array substrate that provides of another embodiment of the present invention;
Fig. 7 C is the 3rd sketch map of the manufacturing array substrate that provides of another embodiment of the present invention;
Fig. 7 D is the 4th sketch map of the manufacturing array substrate that provides of another embodiment of the present invention;
Fig. 7 E is the 5th sketch map of the manufacturing array substrate that provides of another embodiment of the present invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
The embodiment of the invention provides a kind of thin-film transistor, and this thin-film transistor comprises: grid, gate insulation layer, semiconductor active layer, etching barrier layer, source/drain electrode layer; Wherein,
Said semiconductor active layer is a sandwich construction, comprises the semiconductor underlayer of low oxygen content and the semiconductor top layer of elevated oxygen level at least.
To combine Fig. 2 and Fig. 5 to introduce two kinds of implementations of improving structures of the thin-film transistor that the embodiment of the invention provides below.
As shown in Figure 2; A kind of thin-film transistor that the embodiment of the invention provides comprises: be formed on grid 202, gate insulation layer 203, semiconductor underlayer 204, semiconductor top layer 205, etching barrier layer 206, metallized semi conductor layer, data wire metal level on the transparency carrier 201 successively; Wherein, semiconductor underlayer 204 constitutes semiconductor active layer with semiconductor top layer 205, and this semiconductor active layer adopts metal oxide materials; Etching barrier layer 206 is on oxide semiconductor active layer; Above oxide semiconductor active layer, also be formed with the metallized semi conductor layer 207a and the 207b that are positioned at etching barrier layer 206 both sides, and said data wire metal level comprises the source electrode 208a and the drain electrode 208b of data wire, thin-film transistor.
Oxide semiconductor active layer adopts the scheme of hierarchy optimization; Formed by two-layer or multilayer, as shown in Figure 2, the bottom of oxide semiconductor active layer is a semiconductor underlayer 204; The top layer of oxide semiconductor active layer is that semiconductor top layer 205 forms; But the aim that oxide semiconductor active layer forms is bottom and adopts the semiconductor of low oxygen content, high ducting capacity, in order to improve the ducting capacity of device, promptly improves the ON state current (Ion) of device; The semiconductor of top layer adopts the oxide semiconductor of elevated oxygen level, low ducting capacity, in order to the leakage current of control device, promptly reduces the off-state current (Ioff) of device, thereby improves device performance.
After having made above-mentioned active layer oxide semiconductor, form etching barrier layer above that shown in 206 among Fig. 2.After etching barrier layer 206 forms; The Plasma (plasma) that the oxide semiconductor active layer that is exposed to the etching barrier layer both sides is carried out gases such as hydrogen, N2O, CF4 or Ar handles; Form metallized semi conductor layer, 207a as shown in Figure 2 and 207b on the oxide semiconductor active layer surface.The metallized semi conductor layer can reduce the contact resistance of oxide semiconductor active layer and source/drain electrode, and then improves the ohmic contact characteristic of device.Oxide semiconductor active layer, metallized semi conductor layer and source/drain electrode combine and can realize the output of device performance preferably.
Another kind of thin-film transistor as shown in Figure 5, that the embodiment of the invention provides comprises: be formed at the bottom of grid 602 on the transparent glass substrate 601, gate insulation layer 603, the semiconductor 604 successively, semiconductor top layer 605, etching barrier layer 606; Wherein, on patterned etching barrier layer 606, be formed with semiconductor transition zone 607a and the 607b that one deck low oxygen content, height are led; Above semiconductor transition zone 607a and 607b, form active electrode 608a and drain electrode 608b.Wherein, the thickness of semiconductor transition zone 607a and 607b is at 5-50nm.
Semiconductor transition zone with high ducting capacity can reduce the contact resistance between oxide semiconductor active layer and the source/drain electrode, and then improves the ohmic contact characteristic of device.Oxide semiconductor active layer, semiconductor transition zone and source/drain electrode combine; Form the TFT device of a sandwich structure; Not only can have high ON state current Ion and low off-state current Ioff simultaneously; And can solve the ohmic contact problem of source/drain electrode, thereby farthest improve the performance of TFT device.Major technology characteristics of the present invention be exactly in the process of making Oxide TFT, adopt the hierarchy optimization scheme of above-mentioned sandwich structure, improve the performance of device.
Thin-film transistor provided by the invention; Because the oxide semiconductor active layer of hierarchy optimization both can improve the ON state current (Ion) of TFT device; Off-state current that simultaneously can control device reduces the leakage current (Ioff) of device, can improve the characteristic of TFT to greatest extent; The semiconductor transition zone can solve the ohmic contact problem of source/drain electrode and active layer, improves the fan-out capability of device, thereby improves device performance to greatest extent, has improved the yields of whole base plate, has reduced production cost.
To above thin-film transistor different at the process sequence of the oxide semiconductor active layer that forms hierarchy optimization and metallized semi conductor layer/oxide semiconductor transition zone, the embodiment of the invention provides two kinds of method of manufacturing thin film transistor.
The making of thin-film transistor is a pith in the array base palte manufacturing process; To combine a kind of manufacture method of array base palte to introduce the manufacturing process of the thin-film transistor that provides in the foregoing description in the present embodiment.
To introduce the manufacture process of thin-film transistor shown in Figure 2 below through method one.Particularly, the manufacturing process of thin-film transistor can describe with reference to the manufacture process of the array base palte shown in Fig. 3, Fig. 4 A～Fig. 4 M, and its concrete steps comprise:
S401, on substrate, form gate metal layer;
Shown in Fig. 4 A, on Glass substrate 501, form gate metal layer 502.In the manufacturing process of TFT, gate metal layer adopts the method for magnetron sputtering to prepare more, and grid material can be selected according to different device architectures and technological requirement.Common adopted gate metal layer has Mo, and Mo-Al-Mo alloy, Mo/Al-Nd/Mo build up metal level, Cu and Titanium and alloy thereof of structure etc., and make its square resistance remain on a relatively low level.
S402, gate metal layer is carried out graphically;
Shown in Fig. 4 B, general using composition technology through the method for wet etching, is carried out graphically gate metal layer 502, forms like grid 502a among Fig. 4 B and grid line 502b.
S403, on grid, form gate insulation layer;
Shown in Fig. 4 C, after gate patternsization, through Pre-clean technology (cleaning before the film forming); Through plasma reinforced chemical vapor deposition (PECVD) method, preparation gate insulation layer 503 on the substrate that is formed with grid and grid line, its material is used more extensive; Like silicon dioxide (SiO2) film, silicon nitride film (SiNx), silicon oxynitride film (SiOxNy); Aluminium oxide (Al2O3) film, the film of TiOx film and the sandwich construction that meets.
S404, gate insulation layer is carried out surface treatment;
Utilize plasma process that gate electrode insulation surface is handled, the roughness of film surface is descended, interface metastable state material is removed, and stays more stable interface, can improve an effect mobility, and the stability of TFT is improved.
S405, formation semiconductor underlayer;
Shown in Fig. 4 D, form semiconductor underlayer 504, it is exactly the making of semiconductor active layer that oxide TFT makes the most key link.The formation of semiconductor underlayer is very important; The semiconductor underlayer that under hypoxic atmosphere, forms; Form the state of a rich metal ion in film inside, formed the oxygen room simultaneously, and then improved the ducting capacity of charge carrier; Make semiconductor underlayer possess low oxygen content, high ducting capacity, in order to improve the ON state current Ion of TFT device.The oxide semiconductor that widely uses now has the complex of indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO) or indium-zinc oxide (IZO) etc. and relative different proportion.Main manufacture method has magnetron sputtering deposition (Sputter) and solwution method etc.
S406, formation semiconductor top layer;
The material itself of making the selected usefulness of semiconductor top layer is as broad as long with semiconductor underlayer, at making details semiconductor-on-insulator top layer and semiconductor underlayer very big difference is arranged.At first, in order to prevent leakage current, the conductive capability of semiconductor top layer will be weaker than the semiconductor top layer; Under hyperoxia atmosphere, form the semiconductor top layer; At the inner state that forms the oxygen enrichment ion of semiconductor layer, restriction has been played in the conducting of charge carrier, and then leakage current that can control device; Be the low ducting capacity oxide semiconductor that the semiconductor top layer adopts elevated oxygen level, shown in 505 among Fig. 4 E.In order to the leakage current of control device, reduce the off-state current (Ioff) of device, improve device performance to greatest extent.
S407, oxide semiconductor active layer is carried out graphically;
S408, formation etching barrier layer;
Shown in Fig. 4 G; On patterned oxide semiconductor active layer, directly form etching barrier layer (Etch Stop Layer, ESL) 506, its material is different to the difference of separately technological requirement because of different producers; Usually need to use like SiOx, SiNx; Inorganic insulating materials such as SiOxNy, Al2O3, TiOx, Y2O3, its purpose are exactly in order to reduce in the patterned process of data wire, and oxide semiconductor thin-film is damaged; Can improve simultaneously the stability of TFT device effectively, avoid the influence of external environment the TFT device.
S409, etching barrier layer is carried out graphically;
Method through dry etching is carried out graphically etching barrier layer, shown in the 506a among Fig. 4 H.The making key point of this step process is how to control to prevent in the etching barrier layer etching process crossing of gate insulation layer carved.Can cause Gate metal wire and middle short circuit or the punch-through of source-drain electrode in the process of not making Panel fortunately if control, thereby cause Panel to lose efficacy.If on material is selected, select material respectively for use, will well avoid the problems referred to above with big etching selection ratio.The mode that can adopt dry method and wet etching to combine simultaneously also can well be avoided the problems referred to above.
Further; Etching barrier layer be formed with two kinds of schemes, first kind of scheme is after having deposited oxide semiconductor active layer, continues the deposition-etch barrier layer; Through composition technology; Etching exposes source/drain electrode and the semi-conductive via hole that contacts, and the peripheral edge pattern of etching barrier layer and the pattern of oxide semiconductor layer are consistent, can directly define the ohmic contact zone of oxide semiconductor active layer through the via hole of etching barrier layer; Second kind of scheme is after having deposited oxide semiconductor active layer; Carry out graphical earlier; And then carrying out the deposition of etching barrier layer, etching barrier layer covers the whole base plate that forms behind the oxide semiconductor active layer, then etching barrier layer is carried out graphically; Only need expose the position that source/drain electrode contacts with active layer, other regional etching barrier layers still are retained on the substrate.
S410, carry out metallized Plasma and handle;
After having prepared etching barrier layer, formation source/drain electrode.Such production program matches with oxide semiconductor active layer can realize the output of a reasonable device performance.Preferably, before formation source/drain electrode, can utilize the Plasma of gases such as hydrogen, N2O, CF4 or Ar that the surface of oxide semiconductor is handled earlier, and then improve the device ohmic contact characteristic, shown in Fig. 4 I.
S411, formation data wire metal level, and graphically form source/drain electrode;
Shown in Fig. 4 J, after S409 and S410 technical process, form the data wire metal level.At first, deposition layer of metal layer utilizes composition technology, forms data wire and source electrode 508a and drain electrode 508b.Metal level adopts the method for magnetron sputtering to prepare more.Electrode material can be selected according to different device architectures and technological requirement.Usually the electrode metal that adopts has electrode, Cu and Titanium and alloy thereof, ITO electrode, Ti/Al/Ti, the Mo/ITO of Mo, Mo-Al-Mo alloy, Mo/Al-Nd/Mo laminated construction etc., makes its square resistance remain on a relatively low level.After metal electrode layer forms, it is carried out graphical technology.Method through adopting wet etching is carried out graphically it, shown in source electrode 508a among Fig. 4 J and drain electrode 508b.
So far, the making of thin-film transistor is accomplished; But, the making of array base palte also comprises: the formation of passivation layer and the formation of pixel electrode, the forming process to passivation layer and pixel electrode is described in detail below.
The formation of S412, passivation layer and Via hole etching;
Shown in Fig. 4 K, after source/drain electrode is graphical, on whole base plate, form one deck passivation layer, need to use like SiOx, SiNx inorganic insulating materials such as SiOxNy, Al2O3, TiOx, Y2O3 usually; When using in AMOLED (active matrix organic light-emitting diode (AMOLED) panel) field simultaneously, excellent more for follow-up preparation condition, also can adopt organic insulator, like resin material and acrylic based material etc.After passivation layer forms, utilize composition technology, carry out the etching of via hole, in order to being connected of realization drain electrode and pixel electrode, shown in via hole 509a and via hole 509b among Fig. 4 K.
The formation of S413, pixel electrode and graphical;
Shown in Fig. 4 L; After Via hole (via hole) forms, form pixel electrode layer 510, and carry out composition technology through the method for wet etching; What pixel electrode widely adopted now is indium tin oxide, finally forms oxide thin film transistor and array base palte shown in Fig. 4 M.
Like this, under the situation that does not increase operation, the structural design of the semiconductor active layer through hierarchy optimization makes the TFT device have high ON state current Ion and low off-state current Ioff, and then has improved the performance of TFT device.Further, after etching barrier layer is graphical, semiconductor active layer is carried out Plasma handle, the ohmic contact problem of solution source/drain electrode and oxide semiconductor active layer, and then improved the TFT characteristic, guarantee properties of product.
To introduce the manufacturing process of thin-film transistor shown in Figure 5 below through the description of method two.Particularly, the manufacturing process of thin-film transistor can describe with reference to the manufacturing approach of the array base palte shown in process flow diagram Fig. 6, Fig. 7 A～Fig. 7 E.
The embodiment of the invention except the formation of oxide semiconductor transition zone and data wire metal level and oxide semiconductor transition zone graphical (here for the technology production order of S710～S711) and the enforcement of said method one (be S410～S411) different, all the other steps all can be with reference to the foregoing description.
Promptly as shown in Figure 6, its step comprises:
S701, on substrate, form gate metal layer.
S702, gate metal layer is carried out graphically.
S703, on grid, form gate insulation layer.
S704, gate electrode insulation surface is handled.
S705, formation semiconductor underlayer.
S706, formation semiconductor top layer, semiconductor underlayer and semiconductor top layer are formed oxide semiconductor active layer.
S707, oxide semiconductor active layer is carried out graphically.
S708, formation etching barrier layer.
S709, etching barrier layer is carried out graphically;
Is consistent with method one before the S709, just different with technical process such as S410～S411, the processing step that after S412, is carried out is also identical, so the S710～S711 that the present invention is directed in the method two describes.
S710, formation semiconductor transition zone;
Shown in Fig. 7 A; Sketch map for after S701～709 technologies completion forms grid 802a and grid line 802b on substrate 801, behind the formation gate insulation layer 803; Form successively again after semiconductor underlayer 804, semiconductor top layer 805 and the etching barrier layer 806; Before the data wire metal level forms, the oxide semiconductor layer that formation one deck hypoxemia, height are led on patterned etching barrier layer, i.e. semiconductor transition zone.The thickness of this oxide semiconductor transition zone is at 5-50nm, shown among Fig. 7 B 807.Between data wire metal level and oxide semiconductor active layer, form a transition zone, the ohmic contact between realization source/drain electrode and the oxide semiconductor active layer farthest reduces the contact resistance of device, and then improves the performance of device.Oxide semiconductor active layer, semiconductor transition zone and source/drain electrode combine, and form the scheme of the device of a sandwich structure, and it can farthest improve the performance of device.
Major technology characteristics of the present invention be exactly in making the process of thin-film transistor, adopt the hierarchy optimization scheme of above-mentioned sandwich structure, improve the performance of device.The material that the material of semiconductor transition zone and semiconductor active layer can adopt the height of homogeneity or homology to lead, the oxide semiconductor active layer material that widely uses now has the complex of indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium-zinc oxide (IZO) etc. and relative different proportion.As long as control its technical process well, realize the performance of its high conducting, to reduce the ohmic contact between source/drain electrode and the oxide semiconductor active layer simultaneously.Main manufacture method has magnetron sputtering deposition (Sputter) and solwution method etc.Because of the technological requirement difference can be selected different lithographic methods.
S711, form the data wire metal level, and data wire metal level and semiconductor transition zone are carried out graphically;
Shown in Fig. 7 C, after accomplishing S710 technology, on the semiconductor transition zone, form data wire metal level 808.Metal electrode adopts the method for magnetron sputtering to prepare more, and electrode material can be selected according to different device architectures and technological requirement.Common adopted electrode metal has electrode, Cu and Titanium and alloy thereof, ITO electrode, Ti/Al/Ti, Mo/ITO of Mo, Mo-Al-Mo alloy, Mo/Al-Nd/Mo laminated construction etc., makes its square resistance remain on a relatively low level.After the data wire metal level forms, it is carried out graphical technology.Method through adopting wet etching is carried out graphically it, obtains source electrode 808a and the drain electrode 808b shown in Fig. 7 D.In this step etching process, necessarily be noted that the synchronous etching of realization source/drain electrode and oxide semiconductor transition zone, so not only improved the performance of device but also do not increased whole technical process, can not increase production cost.
The formation of S712, passivation layer and Via hole etching.
The formation of S713, pixel electrode layer and composition;
Finally form oxide thin film transistor and array base palte shown in Fig. 7 E, wherein, 809 is passivation layer shown in Fig. 7 E, and 810 is pixel electrode layer, and so far, the oxide thin film transistor array base palte is made and finished.
Like this; Under the situation that does not increase operation; The device scheme of the sandwich structure through hierarchy optimization can well improve the performance of device, not only has high ON state current Ion and low off-state current Ioff, and because the existence of semiconductor transition zone; Solve the ohmic contact problem between source/drain electrode and the active layer, and then guaranteed device property and performance of products.The present invention is having breakthrough design concept to the performance of improving the TFT device; Thereby to the lifting of whole base plate yield, reduce cost and play very crucial effect, and then improved the performance of TFT device; Improve the yields of whole base plate, reduced production cost.
The present invention also provides a kind of array base palte, and it comprises the thin-film transistor described in the foregoing description, and concrete can be with reference to Fig. 2 and structure shown in Figure 5.
The present invention simultaneously provides a kind of display device, and said display device specifically can be LCD, OLED display, active electronic paper display and other display unit of using above-mentioned thin-film transistor, array base palte to drive.
The above; Be merely embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technical staff who is familiar with the present technique field is in the technical scope that the present invention discloses; Can expect easily changing or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of said claim.
Claims (12)
1. thin-film transistor comprises: grid, gate insulation layer, semiconductor active layer, etching barrier layer, source/drain electrode layer, it is characterized in that,
Said semiconductor active layer is a sandwich construction, comprises the semiconductor underlayer of low oxygen content and the semiconductor top layer of elevated oxygen level at least.
2. thin-film transistor according to claim 1 is characterized in that,
The semiconductor transition zone that low oxygen content is arranged between said etching barrier layer and said source/drain electrode layer;
Said semiconductor active layer, said semiconductor transition zone and said source/drain electrode layer forms hierarchy.
3. thin-film transistor according to claim 1 is characterized in that,
The surface that on said semiconductor active layer, does not cover etching barrier layer is formed with the metallized semi conductor layer;
Said semiconductor active layer, source/drain electrode layer and said metallized semi conductor layer form hierarchy.
4. a method of manufacturing thin film transistor comprises: the process that on transparency carrier, forms gate metal layer, gate insulation layer, semiconductor active layer, etching barrier layer, source/drain electrode layer; It is characterized in that,
The process of said formation semiconductor active layer comprises:
Be formed with the semiconductor underlayer of making low oxygen content on the transparency carrier of gate insulation layer;
Be formed with the semiconductor top layer of making elevated oxygen level on the transparency carrier of said semiconductor underlayer.
5. according to the method for manufacturing thin film transistor described in the claim 4, it is characterized in that, after forming said etching barrier layer and before forming said source/drain electrode layer, also comprise:
Utilize plasma process that metalized is carried out on the surface that does not cover etching barrier layer on the said semiconductor active layer, form the metallized semi conductor layer on the semiconductor active layer surface.
6. according to the method for manufacturing thin film transistor described in the claim 4, it is characterized in that, after forming said etching barrier layer and before forming said source/drain electrode layer, also comprise:
Be formed with on the transparency carrier of said etching barrier layer pattern, form the semiconductor transition zone of low oxygen content.
7. according to the method for manufacturing thin film transistor described in the claim 6, it is characterized in that said semiconductor transition zone is identical with the material that the semiconductor underlayer in the said semiconductor active layer is selected for use.
8. method of manufacturing thin film transistor according to claim 6 is characterized in that, the thickness of the semiconductor transition zone of said low oxygen content is 5～50nm.
9. according to the method for manufacturing thin film transistor described in the claim 4, it is characterized in that the process of said formation semiconductor active layer and etching barrier layer comprises:
Be formed with on the transparency carrier of gate insulation layer, forming semiconductor active layer film and etching barrier layer film successively;
Form said semiconductor active layer and etching barrier layer through a composition technology.
10. according to each described method of manufacturing thin film transistor in the claim 4 to 9, it is characterized in that said semiconductor active layer material is a metal oxide materials.
11. an array base palte is characterized in that, said array base palte comprises each described thin-film transistor in the claim 1 to 3.
12. a display device is characterized in that, said display device comprises the described array base palte of claim 11.
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