KR20050063102A - Method of manufacturing a semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device, by forming a capacitor using a trench of the STI structure formed in the semiconductor substrate, it is possible to form a capacitor having a large area in a narrow horizontal length, it is possible to reduce the size of the capacitor In addition, by changing the junction of the lower portion of the trench to form the depletion capacitance to improve the capacitance of the capacitor, it is possible to form a large number of devices in the wafer provides a method of manufacturing a semiconductor device that can increase the yield.

Description

Method of manufacturing a semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a system on chip (SOC).

In the development of existing SOC devices, only the poly gate area of the MOS capacitor portion is increased to increase the solution of the MOS capacitor. However, this shows a result contrary to the trend of the wiring and gate length of the device being miniaturized. In addition, if the area of the MOS capacitor is excessively increased in order to have a sufficient capacitance value, the number of devices to be formed per unit wafer is reduced. In order to solve this problem, a separate DRAM capacitor may be used. However, in order to implement a separate DRAM capacitor, many photoresist pattern processes and high temperature heat treatments may cause high cost and unstable device characteristics. In addition, the implementation of the existing logic device eliminates the advantage of merging the memory (Merge).

Accordingly, the present invention provides a method of manufacturing a semiconductor device capable of forming a capacitor having an STI structure to form a MOS capacitor having a sufficient capacitance in a narrow horizontal area to solve the above problems.

Forming a device isolation film in the device isolation region and the MOS capacitor region by performing a device isolation process on a semiconductor substrate in which the device isolation region, the MOS transistor region, and the MOS capacitor region according to the present invention are defined; Removing the formed device isolation film, forming an oxide film for a dielectric film of a capacitor and a gate insulating film of a transistor along the step on the entire structure, and then forming a polysilicon film over the entire structure, and patterning the polysilicon film to Forming a gate electrode for a MOS transistor in a MOS transistor region, forming a MOS capacitor electrode in the MOS capacitor region, forming an LDD ion layer on the semiconductor substrate on both sides of the gate electrode, and the gate electrode and the MOS capacitor Form spacers on electrode sidewalls Thereafter, a method of manufacturing a semiconductor device, the method including forming a source / drain on the semiconductor substrate by performing high concentration ion implantation.

The method may further include performing a predetermined ion implantation process of implanting a dopant of a type opposite to that of the well of the semiconductor substrate after removing the device isolation layer.

Preferably, the ion implantation process uses a dopant of 5E12 to 5E13 atoms / cm 2, but uses indium (In) or BF ₂ when the P type is used as the dopant, and an acenic type when the N type is used. (As) or antimony (Sb) is used.

Preferably, the dielectric film of the capacitor and the oxide film for the gate insulating film of the transistor are formed by flowing 400 to 600 sccm of TCE gas or by flowing about 500 to 700 sccm of N ₂ gas.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

As semiconductor memory devices are becoming more integrated, so-called silicon on chips, in which different devices with different functions are implemented on one chip, allowing two or more devices to operate organically on one chip. Chip; SoC). Therefore, the manufacturing process of SoC becomes more complicated and difficult. The manufacturing process for implementing one device having different functions on one chip may be a process that satisfies the characteristics of only one device, but each device may have two or more devices having different functions on one chip. Processes that meet all the required properties become very complex and in some cases additional processes are added. An embedded memory device, which is one of SOC devices, implements a memory device and a logic device on a single chip, and computes a cell area in which a plurality of memory cells are located and information stored in the cell area. It is composed of logic areas that generate information. In order to manufacture such a device, a planar DRAM device, in which a unit cell is formed of one MOS transistor and one MOS capacitor, is manufactured.

1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

1A to 1B, a device isolation process is performed by performing a device isolation process on a semiconductor substrate 110 in which a device isolation region A, a MOS transistor region B, and a MOS capacitor region C are defined. And an isolation layer 118 is formed in the MOS capacitor region C.

Since the defect of the semiconductor substrate 110 is very sensitive to the memory merged device, it is preferable to anneal the minimum pure silicon wafer for 30 minutes at a temperature of about 1100 to 1200 ° C. and an N ₂ gas atmosphere before the device separation process. . Through this, the defect of the silicon semiconductor substrate 110 may be removed. Ion implantation may be performed on the semiconductor substrate 110 to form a predetermined well.

The device isolation process is preferably a shallow trench isolation (STI) process.

After the pad oxide film 112 and the pad nitride film 114 are formed on the semiconductor substrate 110, the pad oxide film 112 and the pad nitride film 114 are patterned. The trench 116 is formed by etching the semiconductor substrate 110 through an etching process using the patterned pad oxide layer 112 and the pad nitride layer 114 as an etching mask. The trench 116 is buried into an oxide film and then the pad nitride film 114 is removed.

The pad oxide layer 112 and the pad nitride layer 114 are sequentially formed, and then a photolithography pattern using the photoresist layer is performed to open the device isolation region A and the MOS capacitor region C. ). The pad oxide layer 112 and the pad nitride layer 114 may be etched through the etching process using the photoresist pattern as an etching mask to expose the semiconductor substrate 110. It is preferable to remove the photoresist pattern through a predetermined strip process. The trench 116 is formed by etching the exposed semiconductor substrate 110 through an etching process using the pad nitride layer 114 as an etching mask. The trench 116 is preferably formed to have a slop of about 83 to 89 degrees.

SC-1 (Standard Cleaning-1) consisting of DHF (Dilute HF) and NH ₄ OH, H ₂ O ₂ and H ₂ O with 50: 1 mixture ratio of H ₂ O and HF was formed before the pad oxide layer 112 was formed. Pre-cleaning process using SC-1 consisting of BOE (Buffered Oxide Etch) with NH ₄ F and HF mixing ratio of 100: 1 to 300: 1 and NH ₄ OH, H ₂ O ₂ and H ₂ O It is effective to carry out.

The pad oxide film 112 is formed to a thickness of 50 to 200 kPa by a dry or wet oxidation method, and after the pad oxide film 112 is deposited, a pad heat treatment process is performed by using N ₂ at a temperature of 900 to 910 ° C. for 20 to 30 minutes. The defect density at the interface between the oxide film 112 and the semiconductor substrate 110 may be minimized.

The pad nitride film 114 may be formed by chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), or atmospheric pressure chemical vapor deposition (Atmospheric Pressure). It is preferable to form a nitride film by CVD (APCVD) method.

It is preferable to perform a dry oxidation process to compensate for the etching damage of the sidewalls of the trench 116 by etching. It is preferable to form the device isolation film 118 by depositing an insulating film with a thickness of about 7000 to 9000 Å over the entire structure, and then performing a planarization process using the pad nitride film as a stop film. The corner of the trench 116 may be rounded through a dry oxidation process. As the insulating film, it is preferable to use an oxide-based material film using a high density plasma (HDP) method, a PE-CVD method, an HLD method, and an HDP method. The planarization process is preferably carried out a chemical mechanical polishing process.

To remove the pad nitride film 114, it is preferable to etch the pad nitride film 114 remaining through wet etching with a high temperature H 3 PO 4 solution. After the pad nitride film 114 is removed, it is preferable to perform annealing for 20 to 40 minutes at a temperature of 1000 to 1200 ° C. for the purpose of densification and rounding the upper corner of the device isolation film 118. Due to the high temperature heat treatment, the upper portion of the device isolation layer 118, that is, the edge portion of the region adjacent to the device isolation layer 118 and the semiconductor substrate 110 is rounded.

Referring to FIG. 1C, the device isolation layer 118 in the MOS capacitor region C is removed and then an ion implantation process is performed to form a predetermined ion layer 123.

After the photoresist is coated on the entire structure, a photoresist pattern 120 for opening the device isolation layer 118 in the MOS capacitor region C is formed. It is preferable to form the trench 122 for the MOS capacitor by removing the device isolation layer 118 through an etching process using the photoresist pattern 120 as an etching mask. In the etching process, after wet etching using an aqueous HF solution, it is preferable to remove all of the oxide film remaining in the BOE solution. At this time, the wet etching using the BOE solution may cause a loss of the semiconductor substrate 110 on the trench 122 for the MOS capacitor, thereby rounding the upper edge.

An ion implantation process may be performed using the photosensitive film pattern 120 as an ion implantation mask. It is desirable to inject a certain concentration of dopant of the opposite type to the wells of the silicon substrate below the capacitor. This may allow a junction to be formed later to form a depletion capacitor. If the source / drain connecting the capacitor and the normal transistor is a conductive line, the capacitance of the capacitor oxide film (dielectric film) and the depletion capacitance due to the junction formation are connected in parallel. Therefore, the overall capacitance is the sum of the oxide capacitance Co and the depletion capacitance Cd (Ctotal = Co + Cd). It is preferable that the density | concentration of the dopant injected is 5E12-5E13 atoms / cm <2>. In addition, the implanted dopants are preferably such that they have a maximum concentration at about 300 to 500 Hz from the interface of the trench 122 for the MOS capacitor. In the case of using the P type as the dopant, it is preferable to use indium (In) or BF ₂ , and to use the N type, it is preferable to use Arsenic (As) or Antimony (Sb).

Referring to FIG. 1D, the photoresist pattern 120 is removed through a predetermined strip process. The oxide film remaining on the semiconductor substrate 110 is removed through the cleaning process. The oxide film 130 for the gate insulating film of the transistor and the dielectric of the capacitor is formed on the entire structure along the step. A polysilicon film 132 is deposited on the entire structure.

In order to improve the quality of the oxide film, the oxide film 130 for the dielectric and gate insulating films preferably flows 400-600 sccm (Standard Cubic-Centimeter Per Minute) gas of TCE (Thrichloroethylane: O ₂ + Cl ₂ mixed) gas. Preferably, 500 sccm of TCE gas is passed. 'Cl' of the TCE gas itself increases the oxidation rate, and 'Cl' improves the quality of the oxide film. That is, it reduces the mobile ion charge in the SiO ₂ (changes Na +, K +, etc. into NaCl, KCl form) and reduces defects in the oxide film.

In addition, when forming the oxide film 130 for the dielectric and gate insulating film, N ₂ gas may be flowed about 500 to 700 sccm to form the oxide film as a nitride-based nitride oxide film, thereby increasing the dielectric constant of the dielectric and the gate insulating film and increasing its durability. .

After the oxide film 130 is formed, the polysilicon film 132 is formed without a time delay. Instead of the polysilicon film, a conductive material film may be used.

Referring to FIG. 1E, the polysilicon film 132 is patterned to form a MOS transistor gate electrode 134 in the MOS transistor region C, and a MOS capacitor electrode 136 is formed in the MOS capacitor region C. .

It is preferable to perform a predetermined ion implantation process before the patterning process to dope the polysilicon film in the MOS capacitor region (C). To this end, it is preferable to form a predetermined mask that opens only the MOS capacitor region C, and then ion implantation using the mask as an ion implantation mask to implant only the MOS capacitor region C. It is effective to form a mask using a photosensitive film. After ion implantation, the mask is removed.

After the photosensitive film is coated on the polysilicon film, a photosensitive film mask pattern 137 for forming the gate electrode 134 and the MOS capacitor electrode 136 is formed. An etching process using the photoresist mask pattern 137 as an etching mask is performed to remove the polysilicon film, thereby forming the gate electrode 134 and the MOS capacitor electrode 136. The photoresist mask pattern 137 is removed through a predetermined strip process.

Referring to FIG. 1F, Daisy Curing in the etching process for forming the gate electrode 134 and the MOS capacitor electrode 136, and oxidation for activating and diffusing dopants implanted in the MOS capacitor electrode 136. And a heat treatment step. Through the oxidation and heat treatment process, a predetermined barrier oxide layer 138 is formed on the gate electrode 134 and the MOS capacitor electrode 136 along the step. The heat treatment step is preferably performed at a temperature of 800 to 950 ° C. for about 10 to 40 seconds in an O ₂ gas atmosphere.

Ion implantation is performed to form the LDD ion layer to form the LDD ion layer 140 on the semiconductor substrate 110 on both sides of the gate electrode 134. At this time, in order to form an NMOS transistor and a PMOS transistor, a photoresist pattern 137 for opening the NMOS transistors is formed, followed by ion implantation, a photoresist pattern 137 for opening the PMOS transistor region is formed, and then ion implantation is performed. It is preferable to carry out.

Referring to FIG. 1G, spacers 142 are formed on sidewalls of the gate electrode 134 and the MOS capacitor electrode 136 of the MOS transistor. High concentration ion implantation is performed to form the source / drain 144 on the semiconductor substrate 110 on both sides of the gate electrode 134.

The spacer 142 may be formed by removing a nitride film in a region except for sidewalls of the gate electrode 134 and the MOS capacitor electrode 136 by forming a nitride film over the entire structure and then performing an entire surface etching process. After the nitride film spacer 142 is formed, heat treatment using RTP is preferably performed. This may prevent the impurity ions implanted due to the LDD ion implantation process from being excessively diffused by a thermal process later.

Referring to FIG. 1H, a silicide layer (not shown) is formed on the gate electrode 134, the MOS capacitor electrode 136, and the source / drain 144 through a sally side process. The first interlayer insulating film 150 for insulation is formed on the entire structure. The first interlayer insulating layer 150 is patterned to form a contact hole for electrical contact with the gate electrode 134, a contact hole for electrical contact with the MOS capacitor electrode 138, and a contact for electrical contact with the source / drain 144. After the hole is formed, the contact plug 152 is formed by embedding the hole into a conductive film. Thereafter, a metal wiring process is performed to form metal wiring (not shown) for electrical contact with the plugs.

According to the present invention, by forming a trench of the STI structure, and filling the silicon oxide trench with a trench in the MOS capacitor region, the doped polysilicon is used as a capacitor electrode. In addition, by changing the junction in the lower semiconductor substrate, it is possible to form a depletion capacitance to further increase the capacitance.

As described above, the present invention can form a capacitor using a trench of an STI structure formed in a semiconductor substrate, thereby forming a capacitor having a large area in a narrow horizontal length.

In addition, the size of the capacitor can be reduced, and the capacitance of the capacitor can be improved by forming the depletion capacitance by changing the junction under the trench.

In addition, a large number of devices can be formed in the wafer, thereby increasing the yield.

1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

110 semiconductor substrate 112 pad oxide film

114: pad nitride film 116, 122: trench

118: device isolation layer 120, 137: photoresist pattern

123: ion layer 130, 138: oxide film

132: polysilicon film 132: gate electrode

136 capacitor electrode 140 LDD ion layer

142: spacer 144: source / drain

150: interlayer insulating film 152: contact plug

Claims (4)

Forming a device isolation film in the device isolation region and the MOS capacitor region by performing a device isolation process on a semiconductor substrate in which device isolation regions, MOS transistor regions, and MOS capacitor regions are defined; Removing the device isolation layer formed in the MOS capacitor region; Forming an oxide film for the dielectric of the capacitor and the gate insulating film of the transistor along the step on the entire structure, and then forming a polysilicon film on the entire structure; Patterning the polysilicon film to form a gate electrode for a MOS transistor in the MOS transistor region, and forming a MOS capacitor electrode in the MOS capacitor region; Forming an LDD ion layer on the semiconductor substrate on both sides of the gate electrode; And And forming a spacer on sidewalls of the gate electrode and the MOS capacitor electrode, and then performing a high concentration ion implantation to form a source / drain on the semiconductor substrate. The method of claim 1, wherein after removing the device isolation layer, And performing a predetermined ion implantation process for implanting a dopant of a type opposite to the well of the semiconductor substrate. The method of claim 2, In the ion implantation process, a dopant of 5E12 to 5E13 atoms / cm 2 is used, but indium (In) or BF ₂ is used when the P type is used as the dopant, and when the N type is used, it is acenic (As). A method for manufacturing a semiconductor device using antimony or antimony (Sb). The method of claim 1, The dielectric of the capacitor and the oxide film for the gate insulating film of the transistor are formed by flowing 400 to 600sccm of TCE gas, or about 500 to 700sccm of N ₂ gas.