KR100763556B1 - Mask rom cell, nor type mask rom device and method for manufacturing the sames - Google Patents

Abstract

A mask ROM(Read Only Memory) cell, a NOR type mask ROM device with the same and a manufacturing method thereof are provided to improve the level of integration and a junction breakdown voltage, and to simplify manufacturing processes, and to economize fabrication costs. A mask ROM cell includes a substrate(100) defined with an on-cell region and an off-cell region, a gate oxide layer(102) on the substrate, a first gate electrode(104a) on the gate oxide layer of the on-cell region, a second gate electrode(104b) on the gate oxide layer of the off-cell region, first and second spacers(110a,110b) at both sidewalls of the first and the second gate electrodes, first doped regions and second doped regions. The first doping regions(120) includes a first doping portion and a second doping portion. The first doping portion has a first impurity concentration. The first doping portion is located at predetermined portions adjacent to both sidewalls of the first gate electrode. The second doping portion has a second impurity concentration larger than the first impurity concentration. The second doping portion contacts the first doping portion. The second doping portion is located at a side of the first spacer under the surface of the substrate. The second doping regions(122) are formed within the off-cell region. The second doping regions are spaced apart from both sidewalls of the second gate electrode.

Description

Mask ROM cell, noah type mask ROM device including the same, and a method of manufacturing the same. {Mask ROM cell, nor type mask ROM device and method for manufacturing the sames}

1 is a cross-sectional view illustrating cells of a mask ROM device according to Embodiment 1 of the present invention.

2 to 4 are cross-sectional views for describing a method of forming cells of the mask ROM device illustrated in FIG. 1.

5 is a cross-sectional view illustrating a mask ROM device according to Embodiment 2 of the present invention.

6 is a plan view illustrating a cell region of a mask ROM device according to Embodiment 2 of the present invention.

7 to 13 are cross-sectional views illustrating a method of manufacturing the mask ROM device illustrated in FIGS. 5 and 6.

The present invention relates to a ROM device and a method of manufacturing the same. More specifically, it relates to a mask rom cell, a quinoa mask rom element, and a manufacturing method thereof.

The ROM device is a nonvolatile memory device in which stored data does not change even when a power supply is interrupted. The ROM device may include a mask ROM, a programmable ROM (PROM), an electrically programmable ROM (EPROM), or an erasable EEPROM (EEPROM). and Electrically Programmable ROM).

Among the ROM devices, a mask ROM is coded using a mask having data desired by a user during a manufacturing process to store data. After the data is stored, data cannot be erased and rewritten, and only the stored data is read. Only operation is possible.

The mask rom is coded to write data into each cell of the mask rom during its manufacturing process. As a conventional method of coding a mask ROM device, first, after forming each cell of the MOS transistor, and selectively implanting impurity ions only to some transistors having "0" data.

Specifically, a photoresist pattern for selectively exposing only MOS transistors for having "0" data is formed on a substrate on which MOS transistors are formed. Thereafter, the channel region of the exposed MOS transistor is doped with an impurity having a conductivity type opposite to that of the source / drain.

In this case, the MOS transistor doped with the impurity has a higher threshold voltage than the MOS transistor without the impurity doped. According to the threshold voltage difference of the transistors, the on / off characteristics of the transistors are changed at a specific gate voltage, and data can be distinguished from each cell using the same. That is, an impurity doped transistor always becomes an off transistor that outputs data "0", and a transistor that is not doped impurity becomes an on transistor that always outputs data "1".

A mask rom production method using the coding process described above is also disclosed in Japanese Laid-Open Patent Publication 2001-351992.

Several problems arise when coding data by the method described above.

First, in order for the off transistor to have a sufficiently high threshold voltage, a high concentration of impurities must be doped in the channel region. However, when the ion implantation process for doping the impurity is performed, impurities having a conductivity type opposite to that of the source / drain are heavily doped not only in the channel region but also under the source / drain region. As a result, the junction breakdown voltage is lowered between the drain and the bulk substrate.

In addition, an ion implantation process using high energy must be performed to inject a high concentration of impurities into the channel region under the gate electrode of the transistor. However, when the ion implantation process is performed, no impurities should be implanted in the region where the on transistor is formed, and therefore, a very thick ion implantation mask should be formed in the region where the on transistor is formed. A photoresist pattern is usually used as the ion implantation mask. However, when the photoresist film is formed thick, patterning in a fine pattern is not easy. As a result, it is very difficult to integrate the mask ROM device highly.

Moreover, high energy ion implantation equipment is required to perform the ion implantation process. As a result, the cost of manufacturing the mask ROM device is increased.

Accordingly, a first object of the present invention is to provide a mask ROM cell having a high junction breakdown voltage.

It is a second object of the present invention to provide a method of forming the above mask rom cell.

A third object of the present invention is to provide a highly integrated quinoa mask ROM device having a high junction breakdown voltage.

It is a fourth object of the present invention to provide a method suitable for manufacturing the quinoa mask ROM device described above.

According to an embodiment of the present invention, a mask ROM cell includes a substrate in which an on cell region and an off cell region are divided, a gate oxide film provided on the substrate, and a gate of the on cell region. Impurity doped under a substrate surface adjacent to the first gate electrode provided on the oxide film, the second gate electrode provided on the gate oxide film of the off cell region, and both sidewalls of the first gate electrode in the on cell region. First impurity regions having a shape and extending at least one end thereof to a position opposite to both side walls of the first gate electrode and below the substrate at a position spaced apart from both side walls of the second gate electrode in the off cell region Second impurity regions having a doped shape with impurities.

First and second spacers may be provided on both sidewalls of the first and second gate electrodes, respectively.

The first impurity region may include a first doped region having a first impurity concentration in a portion adjacent to the sidewall of the first gate electrode, and a substrate surface positioned adjacent to the spacers while in contact with the first doped region. And a second doped region having a second impurity concentration higher than the first impurity concentration.

The second impurity region has the second impurity concentration.

The first gate electrode and the second gate electrode may be made of polysilicon doped with impurities.

Some of the first impurity region and the second impurity region may have a shape in which other ends of the first impurity region and the second impurity region are connected to each other.

As a method of forming a mask rom cell according to an embodiment of the present invention for achieving the second object, a gate oxide film is first formed on a substrate in which an on cell region and an off cell region are divided. An on-cell first gate electrode and an off-cell second gate electrode are formed on the gate oxide films of the on cell region and the off cell region, respectively. Preliminary first impurity regions are formed by implanting first ions of impurities under the substrate surface of the on-cell region positioned on both sides of the first gate electrode. Next, a second ion is implanted into the substrate below the surface of the substrate spaced apart from both sidewalls of the first and second gate electrodes, positioned below the surface of the substrate in the on-cell region, and opposed to both sidewalls of the first gate electrode. A first impurity region extending to a position to be formed and a second impurity region positioned to be spaced apart from both sidewalls of the second gate electrode under the substrate surface of the off cell region are formed.

After forming the preliminary first impurity region, first and second spacers may be formed on both sidewalls of the first and second gate electrodes, respectively.

As a specific method of forming the preliminary first impurity region, an ion implantation mask pattern covering the off cell region is first formed. Impurities are implanted into the on-cell region exposed by the ion implantation mask. Next, the ion implantation mask is removed.

According to another aspect of the present invention, a mask ROM device includes a substrate in which an on cell region, an off cell region, and a logic circuit region are divided, a gate oxide layer provided on the substrate, and the on First and second gate electrodes provided on the gate oxide films of the cell and off-cell regions, respectively, third and fourth gate electrodes provided on the gate oxide films of the logic circuit region, and the first to fourth gates. First to fourth spacers respectively disposed on both sidewalls of the electrode, and doped with dopants under a substrate adjacent to both sidewalls of the first gate electrode in the on-cell region, and at least one end of the first to fourth spacers First impurity regions of a first conductivity type extending to a position opposite to both side walls of the first gate electrode, and under the substrate adjacent to both side walls of the second spacer in the off cell region A substrate having a doped shape of water and having one end thereof facing the bottom surface of the second spacer and adjacent to both sidewalls of the third gate electrode of the logic circuit region; And third impurity regions of the first conductivity type provided below and fourth impurity regions of the second conductivity type provided under the substrate adjacent to both sidewalls of the fourth gate electrode of the logic circuit region.

The semiconductor device may further include an interlayer insulating layer covering the first to fourth gate electrodes and having a contact hole exposing at least one portion of the first to fourth impurity regions, and a contact provided in the contact hole. have.

The substrates corresponding to the on cell region and the off cell region are provided with isolation patterns having isolated shapes having a first direction in a length direction.

The first gate electrode and the second gate electrode correspond to a portion of the conductive line extending in a second direction perpendicular to the first direction.

The first gate electrode and the second gate electrode may be made of polysilicon doped with impurities.

A metal silicide layer is deposited on the top surface of the first gate electrode, the top surface of the second gate electrode, and a substrate surface positioned next to the spacers.

The first impurity regions provided as sources among the first impurity regions adjacent to both sidewalls of the first gate electrode may be connected to each other in an extension direction of the first gate electrode.

In a method of manufacturing a mask ROM device according to an embodiment of the present invention for achieving the fourth object, a gate oxide film is first formed on a substrate in which an on cell region, an off cell region, and a logic circuit region are divided. First and second gate electrodes are formed on the gate oxide layers of the on cell region and the off cell region, and third and fourth gate electrodes are formed on the gate oxide layers of the logic circuit region, respectively. Preliminary first impurity regions and preliminary agents are implanted by first ion implanting impurities of a first conductivity type into a substrate of an on-cell region on both sides of the first gate electrode and a substrate of a logic circuit region on both sides of the third gate electrode Three impurity regions are formed. First to fourth spacers are formed on both sidewalls of the first to fourth gate electrodes, respectively. The second ion is implanted with impurities of the first conductivity type under the surface of the substrate between the first to third spacers, so that one end of the on-cell region is at least opposite to both sidewalls of the first gate electrode. A third impurity region is formed on the extended first impurity region, the second impurity region positioned at one end of the off-cell region to face the bottom surface of the spacer, and a third impurity region on both substrates of the third gate electrode of the logic circuit region; . Next, a third impurity region is formed by implanting a third ion-type impurity under the surface of the substrate between the fourth spacers to form a fourth impurity region.

Additionally, forming an interlayer insulating film covering the first to fourth gate electrodes, and forming a contact hole exposing at least one of the first to fourth impurity regions by etching a portion of the interlayer insulating film. The method may further include forming a contact by filling the contact hole with a conductive material.

The method may further include forming device isolation patterns having isolated shapes having a first direction in a length direction on the substrate corresponding to the on cell area and the off cell area.

In this case, each of the first and second gate electrodes corresponds to a portion of a conductive line extending in a second direction perpendicular to the first direction, and the first and second gate electrodes are electrically conductive on the gate oxide layer. It can be formed by performing a step of forming a film and a step of patterning the conductive film to have a line shape extending in the second direction.

The first to fourth gate electrodes include polysilicon doped with impurities.

A process of forming a metal silicide layer pattern may be further performed on upper surfaces of the first to fourth gate electrodes and a surface of a substrate positioned next to the spacers.

As a specific method for forming the preliminary first and third impurity regions, forming an ion implantation mask pattern covering the off-cell region and the logic circuit region where the fourth gate electrode is formed, and exposing the ion implantation mask by the ion implantation mask. Implanting impurities into the on-cell region and the logic circuit region on which the third gate electrode is formed, and removing the ion implantation mask.

Prior to forming the fourth gate electrode, a process of forming a channel region by injecting impurities of a first conductivity type into a substrate of a logic circuit region for forming the fourth gate electrode may be performed.

In an on-cell transistor and an off-cell transistor in a mask ROM cell according to the present invention, the degree of overlap of each impurity region provided as a source / drain with the gate electrode is different. That is, one end of the impurity region provided to the source / drain of the off-cell transistor is spaced apart from the sidewall portion of the gate electrode. Therefore, the gate electrode of the off cell transistor does not overlap with the impurity region. In this case, even when a voltage is applied to the gate electrode of the off-cell transistor, the channel is not connected to the impurity region. Thus, the off cell transistor is always kept turned off.

On the other hand, when forming the mask ROM cell according to the present invention, it is not necessary to perform data coding by the ion implantation process with high energy as in the prior art. Therefore, it is possible to somewhat solve the problem that the breakdown voltage between the drain and the bulk silicon substrate caused by performing the high energy ion implantation process is lowered.

In addition, since the ion implantation process is not performed, a process of forming a thick ion implantation mask pattern may not be performed.

In the case of manufacturing the quinoa mask ROM device, an ion implantation mask for coding an off-cell transistor may be simultaneously formed in a process of forming an ion implantation mask for selectively masking transistors in a logic circuit region. Therefore, a separate photo process for forming the ion implantation mask of the off-cell transistor is not required, so that the process of the semiconductor element is simplified.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

1 is a cross-sectional view illustrating cells of a mask ROM device according to Embodiment 1 of the present invention.

Referring to FIG. 1, a substrate 100 in which an on cell region and an off cell region are divided is provided. The substrate 100 may be made of single crystal silicon doped with a low concentration of P-type impurities.

The cells of the mask ROM device include an on cell transistor that is always turned on in a read operation and an off cell transistor that is always turned off in a read operation. Therefore, an on cell transistor is formed in the substrate of the on cell region, and an off cell transistor is formed in the substrate of the off cell region. In this embodiment, the on cell transistor is composed of an N-type transistor.

First, an on cell transistor formed in the on cell region will be described.

A gate oxide film 102 is provided on the surface of the substrate 100 in the on cell region. The gate oxide layer 102 may be formed of silicon oxide generated by heat treating the substrate.

The first gate electrode 104a is provided on the gate oxide film 102 in the on cell region. The first gate electrode 104a may be made of a conductive material. Specifically, the first gate electrode 104a may be made of a semiconductor material such as doped polysilicon, a metal material, or the like.

First sidewalls 110a of an insulating material may be provided on both sidewalls of the first gate electrode 104a. The first spacer 110a may include silicon nitride.

First impurity regions 120 having a shape doped with N-type impurities are disposed under the substrate 100 adjacent to both sidewalls of the first gate electrode 104a in the on-cell region. The first impurity regions 120 extend to a position where one end thereof opposes at least two sidewalls of the first gate electrode 104a.

In addition, the first impurity region 120 may include a first doped region 120a having a first impurity concentration at a portion adjacent to the sidewall of the first gate electrode 104a, and the first doped region 120a. And a second doped region 120b positioned below the surface of the substrate 100 on the side of the first spacer 110a and having a second impurity concentration higher than the first impurity concentration. The second doped region 120b has a deeper doping depth than the first doped region 120a.

When a voltage equal to or greater than a threshold voltage is applied to the first gate electrode 104a of the on cell transistor, the channel electrically connected to the first impurity regions 120 is formed on the substrate under the first gate electrode 104a. Is formed and the turn on state is maintained.

Hereinafter, the off cell transistor formed in the off cell region will be described.

A gate oxide film 102 is provided on the surface of the substrate 100 in the off cell region.

The second gate electrode 104b is provided on the gate oxide film 102 in the off cell region. The second gate electrode 104b is made of the same conductive material as the first gate electrode 104a.

Second sidewalls 110b of an insulating material are provided on both sidewalls of the second gate electrode 104b. The second spacer 110b is made of the same material as the first spacer 110a.

Second impurity regions 122 having a shape doped with N-type impurities are disposed under the substrate adjacent to both sidewalls of the second gate electrode 104b in the off cell region. The second impurity regions 122 are positioned such that one end thereof faces the bottom surface of the second spacer 110b. That is, the second impurity regions 122 are positioned not to overlap with the second gate electrode 104b. The second impurity region 122 has the same impurity concentration as the second impurity concentration.

Even when a voltage is applied to the second gate electrode 104b of the off-cell transistor, a channel electrically connected to the second impurity regions 122 is not formed in the substrate under the second gate electrode 104b. . Thus, the off cell transistor is always turned off regardless of the gate voltage.

As shown in FIG. 1, the on cell region and the off cell region may be located adjacent to each other. In this case, some of the first impurity region 120 and the second impurity region 122 may have a shape connected to each other.

2 to 4 are cross-sectional views for describing a method of forming cells of the mask ROM device illustrated in FIG. 1.

Referring to FIG. 2, a gate oxide layer 102 is formed on a substrate 100 in which an on cell region and an off cell region are divided. The substrate 100 may be made of single crystal silicon doped with a low concentration of P-type impurities. In addition, the gate oxide layer 102 may be formed by thermally oxidizing the substrate.

A gate electrode conductive film (not shown) is formed on the gate oxide film 102. Examples of the material that can be used as the conductive film include polysilicon and metals. In the present embodiment, the conductive film is formed using a polysilicon material which can be easily etched through a dry etching process.

Thereafter, the conductive layer is patterned through a photolithography process to form a first gate electrode 104a in the on cell region and a second gate electrode 104b in the off cell region.

An ion implantation mask pattern 106 is formed to cover the off cell region. The ion implantation mask pattern includes a photoresist pattern formed through a photo process. An N-type impurity is ion-implanted into the substrate 100 of the on-cell region exposed by the ion implantation mask pattern 106 to form a preliminary first impurity region 108 having a first impurity concentration.

Next, although not shown, the ion implantation mask pattern 106 is removed. When the ion implantation mask pattern 106 is formed of a photoresist pattern, the ion implantation mask pattern 106 may be removed through an ashing and stripping process.

Referring to FIG. 3, an insulating layer (not shown) for spacers is formed on sidewalls of the first and second gate electrodes 104a and 104b and the gate oxide layer 102. The spacer insulating film may be formed by depositing silicon nitride through a low pressure chemical vapor deposition method. Afterwards, the spacer insulating layer is anisotropically etched to form first and second spacers 110a and 110b on both sidewalls of the first and second gate electrodes 104a and 104b, respectively.

In this case, the first and second spacers 110a and 110b may have a distance greater than a distance at which impurities doped below the substrate surface may diffuse toward the first and second gate electrodes 104a and 104b in a subsequent process. It should be thick. This will be described later.

Referring to FIG. 4, an N-type impurity is ion-implanted under the surface of the substrate between the first and second spacers 110a and 110b to form a first impurity region 120 in the on-cell region. The second impurity region 122 is formed in the region.

The second impurity region 122 formed through the ion implantation process is doped with a higher concentration of impurities than the preliminary first impurity region 108. In addition, the second impurity region 122 formed through the ion implantation process may have a deeper doping depth than the preliminary first impurity region 108 formed by the previous process.

The first impurity region 120 includes a preliminary first impurity region 108 previously formed. Therefore, the first impurity region 120 has a shape in which one end thereof extends to a position facing at least both sidewalls of the first gate electrode 104a. In detail, the first impurity region 120 includes a first doped region 120a having a first impurity concentration at a portion adjacent to the sidewall of the first gate electrode 104a, and the first doped region 120a. ) And an LDD structure including a second doped region 120b having a second impurity concentration under the substrate next to the second spacer 110b.

In addition, the second doped region 120b has a deeper doping depth than the first doped region 120a.

On the other hand, the off-cell region was not doped with any N-type impurities in the previous process. Therefore, the second impurity region 122 formed in the off cell region is positioned such that one end thereof faces the bottom surface of the second spacer 110b. That is, the second impurity regions 122 are positioned not to overlap with the second gate electrode 104b.

Here, the impurities doped in the second impurity region 122 may be somewhat diffused while performing subsequent processes involving high temperature. Therefore, in order to prevent the second impurity region 122 from overlapping with the second gate electrode 104b even when the impurities are diffused in the direction of the second gate electrode 104b, the second spacer 110b may have the impurities. It should be formed thicker than the distance that can be diffused in the direction of the second gate electrode 104b.

By performing the above-described process, an on cell transistor is completed in the on cell region, and an off cell transistor is completed in the off cell region.

According to this embodiment, in forming the off-cell transistor, a process of implanting impurities into the channel region as in the prior art is not required. For this reason, the operation characteristic and reliability of a mask ROM element can be improved.

Example 2

5 is a cross-sectional view illustrating a mask ROM device according to Embodiment 2 of the present invention. 6 is a plan view illustrating a cell region of a mask ROM device according to Embodiment 2 of the present invention.

5 and 6, a substrate 200 in which a cell region including an on cell region and an off cell region and a logic circuit region are divided is provided.

In the cell region, on cell transistors and off cell transistors are arranged as data desired by a user. For example, the C1 region of FIG. 6 may be designated as an off cell region and the remaining region including the C2 region may be designated as an on cell region. In this case, the C1 region is provided with an off cell transistor and the remaining portions are on cell transistors. Is provided.

In addition, the logic circuit region includes N-type transistors and P-type transistor, respectively.

Hereinafter, the transistors formed in each region will be described in more detail.

The substrate 200 may be made of single crystal silicon doped with a low concentration of P-type impurities. The N-type impurity region 202 for providing the channel region is deeply formed in the substrate where the P-type transistor is formed in the logic circuit region.

The substrate 200 includes device isolation layer patterns 204 for defining an active region. Specifically, the cell region is provided with the isolation layer pattern 204 of the isolated shape having a first direction in the longitudinal direction. Each device isolation layer pattern 204 formed in the cell region is repeatedly arranged in parallel with each other. In addition, device isolation layer patterns 204 are provided in the logic circuit region to separate the N-type transistors and the P-type transistor.

A gate oxide film 206 is provided on the surface of the substrate 200. The gate oxide layer 206 may be formed of silicon oxide generated by heat treating the substrate.

A plurality of gate electrode lines 208 (FIG. 6) are provided on the gate oxide layer 206 positioned in the on cell region and the off cell region. The gate electrode lines 208 have a line shape extending in a second direction that is perpendicular to the first direction. In detail, the gate electrode lines 208 are disposed to be orthogonal to the plurality of device isolation layer patterns 204. In addition, two gate electrode lines 208 may be disposed on one isolated device isolation layer pattern 204.

The portion of the gate electrode line 208 via the on cell region is provided to the gate electrode of the on cell transistor, and the portion of the gate cell line 208 is provided to the gate electrode of the off cell transistor. Hereinafter, a portion via the cell region on the gate electrode line is referred to as the first gate electrode 208a and a portion via the off cell region is referred to as a second gate electrode 208b.

Third and fourth gate electrodes 208c and 208d are provided on the gate oxide layer 206 positioned in the logic circuit region.

The first to fourth gate electrodes 208a, 208b, 208c, and 208d may be formed of a semiconductor material such as doped polysilicon, a metal material, or the like. In the present embodiment, the first to fourth gate electrodes 208a, 208b, 208c, and 208d are made of doped polysilicon material.

Spacers formed of an insulating material are provided on both sidewalls of the gate electrode line 208 and the third and fourth gate electrodes 208c and 208d. The spacer may comprise silicon nitride. Hereinafter, the spacers formed on both sidewalls of the first to fourth gate electrodes 208a, 208b, 208c, and 208d will be described as first to fourth spacers 220a, 220b, 220c, and 220d, respectively.

First impurity regions 222 having a shape doped with N-type impurities are disposed under the substrate adjacent to both sidewalls of the first gate electrode 208a in the on-cell region. The first impurity regions 222 extend to a position where one end thereof opposes at least two side walls of the first gate electrode 208a.

 The first impurity region 222 contacts the first doped region 222a having a first impurity concentration at a portion adjacent to the sidewall of the first gate electrode and the first doped region 222a. The second doped region 222b is disposed below the surface of the substrate 200 adjacent to the spacer 220a and has a second impurity concentration higher than the first impurity concentration. The second doped region 222b has a deeper doping depth than the first doped region 222a.

When a voltage equal to or greater than a threshold voltage is applied to the first gate electrode 208a of the on cell transistor, a channel is formed on the substrate under the first gate electrode 208a to maintain a turn on state.

Second impurity regions 226 having a shape doped with N-type impurities are disposed under the substrate adjacent to both sidewalls of the second gate electrode 208b in the off cell region. The second impurity regions 226 are positioned such that one end thereof faces the bottom surface of the second spacer 220b. That is, the second impurity regions 226 are positioned not to overlap with the second gate electrode 208b. The second impurity region 226 has the same impurity concentration as the second impurity concentration.

Even when a voltage is applied to the second gate electrode 208b of the off-cell transistor, no channel is formed on the substrate under the second gate electrode 208b to electrically connect the second impurity regions 226 to each other. . Thus, the off cell transistor is always turned off regardless of the gate voltage.

In addition, referring to the cell region illustrated in FIG. 6, the impurity regions S corresponding to the sources of the on-cell transistors and the off-cell transistors arranged side by side in the second direction may be connected to each other.

Third impurity regions 224 having a shape doped with N-type impurities are disposed under the substrate adjacent to both sidewalls of the third gate electrode 208c in the logic circuit region. The third impurity regions 224 extend to a position where one end thereof opposes at least two side walls of the third gate electrode 208c. Similar to the first impurity region 222, the third impurity region 224 has an LDD structure having a relatively low impurity concentration at a portion adjacent to the sidewall of the third gate electrode 208c.

Fourth impurity regions 228 having a shape doped with P-type impurities are disposed under the substrate adjacent to both sidewalls of the fourth gate electrode 208d in the logic circuit region. The fourth impurity regions 228 extend to a position where one end thereof opposes at least both sidewalls of the fourth gate electrode 208d. The fourth impurity region 228 has the same LDD structure as that of the first and third impurity regions 222 and 224 except that the doped impurities have different conductivity types.

A metal silicide layer pattern 232 is provided on the substrate 100 between the spacers and the device isolation layer pattern. That is, the metal silicide layer pattern 232 is formed on the top surface of the first to fourth impurity regions 222, 226, 224, and 228.

In addition, metal silicide layer patterns 232 may be provided on upper surfaces of the first to fourth gate electrodes 208a, 208b, 208c, and 208d. Since the metal silicide layer pattern 232 is formed, the resistance of the entire structure including the gate electrodes 208a, 208b, 208c, and 208d and the metal silicide pattern 232 may be reduced.

Examples of the material that may be used as the metal silicide layer pattern 232 include tungsten silicide, cobalt silicide, titanium silicide, and the like. These may be used alone or in combination and are preferably used alone.

An interlayer insulating layer 234 covering the first to fourth gate electrodes 208a, 208b, 208c, and 208d is provided on the substrate 100. The interlayer insulating layer 234 is provided with a contact hole 236 exposing a surface of at least one impurity region among the first to fourth impurity regions 222, 226, 224, and 228. The contact hole 236 is provided with contacts in contact with the impurity regions.

In detail, the cell region includes a bit line contact 238a that is connected to an impurity region that is provided as a common drain region in the transistors that pass through the unit device isolation layer pattern 204. In addition, a common source contact 238b connected to the impurity regions provided in the source of each transistor and connected to the second direction in the cell region is provided.

Although not shown, a wiring line connected to the contact is provided. The wiring line includes a bit line and a common source line.

7 to 13 are cross-sectional views illustrating a method of manufacturing the mask ROM device illustrated in FIGS. 5 and 6.

Referring to FIG. 7, a substrate 200 in which a cell region and a logic circuit region are divided is provided. The cell region includes an on cell region and an off cell region. The substrate 200 is made of single crystal silicon doped with a low concentration of P-type impurities.

A first photoresist pattern (not shown) is formed on the substrate 200 to expose a portion where a P-type transistor in a logic circuit region is formed.

Using the first photoresist pattern as an ion implantation mask, a low concentration of N-type impurities is implanted under the exposed substrate surface. By performing the ion implantation process, the N-type impurity region 202 to be provided to the channel region of the P-type transistor is completed.

Thereafter, an isolation layer pattern 204 for defining an active region is formed on the substrate 200.

Specifically, a portion of the substrate 200 is etched to form trenches (not shown) for defining device isolation regions. In this case, an isolated trench having a first direction in the cell direction is formed in the cell region, and a trench is formed in a portion where the N-type transistors and the P-type transistor are separated from each other in the logic circuit region. Thereafter, the isolation layer pattern 204 is completed by filling an insulating material in the trench.

At this time, the trenches isolated in the cell region are formed to be repeatedly arranged in parallel with each other. Therefore, the device isolation layer patterns 204 formed in the cell region are arranged in parallel with each other.

Next, a gate oxide film 206 is formed on the substrate 200 corresponding to the active region. The gate oxide layer 206 may be formed by thermally oxidizing the substrate 200.

A gate electrode conductive film (not shown) is formed on the gate oxide film 206. Examples of the material that can be used as the conductive film include polysilicon and metals. In the present embodiment, the conductive film is formed using a polysilicon material which can be easily etched through a dry etching process.

After that, by patterning the conductive layer through a photolithography process, as shown in FIG. 6, gate electrode lines 208 are formed in the cell region, and at the same time, the gate electrode has an isolated pattern shape in the logic circuit region. Form them.

The gate electrode line 208 formed in the cell region has a line shape extending in a second direction perpendicular to the first direction. In addition, it is preferable that two gate electrode lines 208 extend in parallel with each other on the isolated single isolation pattern 204.

The gate electrode line portion located in the on cell region (FIG. 6, C2) is provided as a gate electrode of the on cell transistor, and the gate electrode line portion (FIG. 6, C1) located in the off cell region is It is provided as a gate electrode. Hereinafter, the gate electrode line portion located in the on cell region is referred to as the first gate electrode 208a, and the gate electrode line portion located in the off cell region is referred to as the second gate electrode 208b.

In addition, the conductive film pattern used as the gate electrode of the NMOS transistor in the logic circuit region is called the third gate electrode 208c, and the conductive film pattern used as the gate electrode of the PMOS transistor is called the fourth gate electrode 208d. .

Referring to FIG. 8, a second photoresist pattern 210 may be formed in the logic circuit region to selectively expose the PMOS transistor formation region.

Thereafter, the second photoresist pattern 210 is used as an etching mask to implant P-type impurities under the substrate surface on both sides of the fourth gate electrode 208d. Through the above process, the preliminary fourth impurity region 212 is formed.

Next, although not shown, the second photoresist pattern 210 is removed through an ashing and stripping process.

Referring to FIG. 9, a third photoresist pattern 214 exposing the NMOS transistor formation region and the on cell region in the logic circuit region is formed. That is, the third photoresist pattern 214 covers the PMOS transistor formation region and the off cell region in the logic circuit region.

Thereafter, using the third photoresist pattern 214 as an etch mask, an N-type below the substrate surface on both sides of the first gate electrode 208a and the substrate surface on both sides of the third gate electrode 208c in the on-cell region. Inject impurities. Through the above process, a preliminary first impurity region 216 having a first impurity concentration is formed on both substrates of the first gate electrode 208a in the on-cell region, and the substrates on both sides of the third gate electrode 208c are formed. The preliminary third impurity region 218 is formed on the surface.

As described above, in the present embodiment, the third photoresist pattern 214 is formed to simultaneously mask the off cell region in the photolithography process for masking the PMOS transistor formation region in the logic circuit region. In other words, by masking the off-cell region as described above, the data is coded into a desired data. Therefore, a separate photo process for data coding and a process of injecting impurities into a channel region as in the prior art are not required.

Next, although not shown, the third photoresist pattern 214 is removed through an ashing and stripping process.

Referring to FIG. 10, an insulating film (not shown) for spacers is formed on sidewalls of the gate electrode lines and the third and fourth gate electrodes 208c and 208d. The spacer insulating film may be formed by depositing silicon nitride.

After that, the spacer insulating layer is anisotropically etched to form spacers on both sidewalls of the gate electrode lines and the third and fourth gate electrodes 208c and 208d. Hereinafter, the spacers formed on sidewalls of the first and second gate electrodes 208a and 208b are referred to as first and second spacers 220a and 220b, respectively, and the third and fourth gate electrodes 208c and 208d may be used. The spacers formed on the sidewalls of the spacers are referred to as third and fourth spacers 220c and 220d, respectively.

Next, a fourth photoresist pattern 221 covering a portion where the P-type transistor is formed in the logic circuit region is formed.

Using the fourth photoresist pattern 221 as an ion implantation mask, a high concentration of N-type impurities are implanted into portions where N-type transistors are formed in the on and off cell regions and the logic circuit region.

By performing the ion implantation process, a first impurity region 222 is formed in the on cell region, the one end portion of which extends to a position facing at least both sidewalls of the first gate electrode 208a. The first impurity region 222 is in contact with the first doped region 222a having a first impurity concentration at a portion adjacent to the sidewall of the first gate electrode 208a and the first doped region 222a. The LDD structure includes a second doped region 222b having a second impurity concentration under a substrate positioned next to the first spacer 220a.

In addition, a third impurity region 224 having the same shape as the first impurity region 222 is also formed in the N-type transistor formation region in the logic circuit region.

On the other hand, in the off cell region, second impurity regions 226 having a shape doped with N-type impurities are formed under the substrate adjacent to both sidewalls of the second gate electrode 208b. In this case, the second impurity regions 226 should be positioned such that one end thereof faces the bottom surface of the second spacer 220b. That is, the second impurity regions 226 should be positioned so as not to overlap with the second gate electrode 208b.

However, impurities doped in the second impurity region 226 may be somewhat diffused while performing subsequent processes involving high temperature. Therefore, in order to prevent the second impurity region 226 from overlapping with the second gate electrode 208b even when the impurities are diffused toward the second gate electrode 208b, the second spacer 220b may be formed of the impurity. It is preferable to form thicker than the distance that can be diffused in the direction of the second gate electrode 208b.

When the ion implantation process is performed, an on cell transistor is formed in the on cell region, an off cell transistor is formed in the off cell region, and an N type transistor is formed in a portion of the logic circuit region.

In addition, as illustrated in FIG. 6, the impurity regions S corresponding to the sources of the on-cell transistors and the off-cell transistors arranged side by side in the second direction have a shape connected to each other.

After performing the ion implantation process, the fourth photoresist pattern 221 used as an ion implantation mask is removed through an ashing and stripping process.

Referring to FIG. 11, a fifth photoresist pattern 230 is formed to selectively expose a portion where a P-type transistor is formed in the logic circuit region. By forming the fifth photoresist pattern 230, portions in which the N-type transistors are formed in the on and off cell regions and the logic circuit region are covered.

Next, using the fifth photoresist pattern 230 as an ion implantation mask, a high concentration of P-type impurities are implanted into a portion where the P-type transistor is formed in the logic circuit region.

By performing the ion implantation process, a fourth impurity region 228 having a shape in which one end thereof extends to a position facing at least both sidewalls of the fourth gate electrode 208d is formed in the P-type transistor forming portion. A portion of the fourth impurity region 228 adjacent to the sidewall of the fourth gate electrode 08d has a low concentration, and a portion under the substrate 200 next to the fourth spacer has an LDD structure having a high concentration.

By performing the above process, a P-type transistor is completed in a portion of the logic circuit region.

After performing the ion implantation process, the fifth photoresist pattern 230 used as an ion implantation mask is removed through an ashing and stripping process.

Referring to FIG. 12, the gate oxide layer 206 remaining on the substrate surface 100 exposed to the spacers 220a, 220b, 220c, and 220d is removed through a cleaning process. When the process is performed, the gate oxide layer 206 remains only under the gate electrodes 208a, 208b, 208c and 208d and the spacers 220a, 220b, 220c and 220d.

Thereafter, a metal film (not shown) is deposited on the exposed substrate 200, the spacers 220a, 220b, 220c, and 220d and the surfaces of the first to fourth gate electrodes 208a, 208b, 208c, and 208d. do. Examples of the metal material that can be used as the metal film include tungsten, cobalt, titanium, and the like. These can be used individually or in mixture.

In some embodiments, a capping layer (not shown) may be further formed on the metal layer. Examples of the material that can be used as the capping film include titanium, titanium nitride and the like. These can be used individually or in mixture. The capping film serves to reduce the interfacial oxide film formed on the surface of the substrate and the first to fourth gate electrodes 208a, 208b, 208c, and 208d in a subsequent heat treatment process, and to allow the silicidation reaction to occur more stably. do.

Next, the substrate 200 is heat-treated to react the surface of the substrate 200 with the surfaces of the first to fourth gate electrodes 208a, 208b, 208c, and 208d and the metal film to form the metal silicide film pattern 232. do. At this time, the metal film formed on the spacer remains without reaction.

When the metal silicide layer pattern 232 is formed, the surface of the substrate 200 and the first to fourth gate electrodes 208a, 208b, 208c, and 208d react with each other to consume a little. Therefore, the metal silicide layer pattern 232 may be thinly formed so that the first to fourth impurity regions 222, 226, 224, and 228 are not excessively consumed.

The heat treatment process for forming the metal silicide layer pattern 232 may be performed by a furnace method or an RTP method. The heat treatment process may be performed only once, or may be performed two or more times at different temperatures.

Thereafter, the unreacted metal film and the capping film remaining on the first to fourth spacers 220a, 220b, 220c, and 220d are removed. The unreacted metal film and the capping film may be removed by a wet etching process.

 Referring to FIG. 13, an interlayer insulating layer 234 is formed on the substrate 200 to cover the first to fourth gate electrodes 208a, 208b, 208c, and 208d. The interlayer insulating layer 234 may be formed by depositing silicon oxide.

Next, a portion of the interlayer insulating layer 234 is etched to form a contact hole 236 exposing a surface of at least one impurity region of the first to fourth impurity regions. In detail, a contact hole 236 is formed in the cell region to selectively expose an impurity region that is used as a common drain region in the transistor that passes through the unit device isolation layer pattern. In addition, a contact hole 236 is formed in the cell region to expose one end of the impurity regions connected in the second direction and serving as a common source.

Thereafter, a conductive material is formed and planarized to fill the inside of the contact hole 236 to form a contact 238 in contact with the impurity regions.

Although not shown, a wiring line connected to the contact 238 is formed. The wiring line includes a bit line and a common source line.

According to this embodiment, a step of injecting impurities into the channel region during data coding of the quinoa mask ROM device is not required. For this reason, the operation characteristic and reliability of a quinoa mask ROM element can be improved. In addition, since a separate photographic process for data coding is not required, the process is simpler, which may reduce the manufacturing cost of the semiconductor device.

As described above, according to the present invention, a mask ROM device having a highly integrated and high junction breakdown voltage may be implemented. In addition, the mask ROM device may be manufactured through a simple process. This improves the reliability of the mask ROM device and reduces the manufacturing cost.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (24)

A substrate in which an on cell region and an off cell region are divided; A gate oxide film provided on the substrate; A first gate electrode provided on the gate oxide film in the on cell region; A second gate electrode on the gate oxide layer in the off cell region; First and second spacers disposed on opposite sidewalls of the first and second gate electrodes, respectively; A first doped region having a first impurity concentration in a portion of the on-cell region adjacent to both sidewalls of the first gate electrode, and positioned below the substrate surface next to the first spacer while contacting the first doped region; First impurity regions comprising a second doped region having a second impurity concentration higher than the first impurity concentration, wherein the channel and the doped region are electrically connected to each other; And Second impurity regions provided in the off-cell region, the second impurity regions having a shape doped with impurities below a substrate at a position spaced apart from both sidewalls of the second gate electrode such that a channel and an impurity doped region are electrically insulated from each other; A mask rom cell, characterized in that. delete delete The mask cell of claim 1, wherein the second impurity region has the second impurity concentration. The mask cell of claim 1, wherein the first gate electrode and the second gate electrode are made of polysilicon doped with impurities. The mask cell of claim 1, wherein some of the first impurity region and the second impurity region have a shape in which the other ends of the first impurity region and the second impurity region are connected to each other. Forming a gate oxide film on a substrate in which the on cell region and the off cell region are divided; Forming on-cell first gate electrodes and off-cell second gate electrodes on the gate oxide films of the on-cell region and off-cell region, respectively; Forming a preliminary first impurity region by implanting first ions of impurities under a substrate surface of an on-cell region on both sides of the first gate electrode; And A second ion is implanted into the substrate below the surface of the substrate spaced apart from both sidewalls of the first and second gate electrodes, and is positioned below the surface of the substrate in the on-cell region and faces the sidewalls of the first gate electrode. Forming a first impurity region extending to and a second impurity region spaced apart from both sidewalls of the second gate electrode under a substrate surface of the off-cell region; . The method of claim 7, wherein after forming the preliminary first impurity region, And forming first and second spacers on both sidewalls of the first and second gate electrodes, respectively. The method of claim 7, wherein forming the preliminary first impurity region comprises: Forming an ion implantation mask pattern covering the off cell region; Implanting impurities into the on-cell region exposed by the ion implantation mask; And Removing the ion implantation mask. A substrate in which an on cell region, an off cell region, and a logic circuit region are divided; A gate oxide film provided on the substrate; First and second gate electrodes provided on the gate oxide layers of the on cell region and the off cell region, respectively; Third and fourth gate electrodes provided on the gate oxide layer of the logic circuit region; First to fourth spacers provided on both sidewalls of the first to fourth gate electrodes, respectively; A first conductivity type in which the dopant is doped under the substrate adjacent to both sidewalls of the first gate electrode in the on-cell region, and one end thereof extends to a position facing at least both sidewalls of the first gate electrode First impurity regions of; A second impurity region of the first conductivity type having a shape doped with an impurity under the substrate adjacent to both sidewalls of the second spacer in the off-cell region and having one end facing the bottom surface of the second spacer field; Third impurity regions of the first conductivity type provided under the substrate adjacent to both sidewalls of the third gate electrode of the logic circuit region; And And a fourth impurity region of a second conductivity type provided under the substrate adjacent to both sidewalls of the fourth gate electrode of the logic circuit region. The method of claim 10, An interlayer insulating layer covering the first to fourth gate electrodes and having a contact hole exposing at least one portion of the first to fourth impurity regions; And Noah type mask rom device further comprises a contact provided in the contact hole. 12. The NOR mask element of claim 10, wherein the substrates corresponding to the on cell region and the off cell region are provided with isolation pattern elements having a first direction in a length direction. The NAM type mask rom device of claim 12, wherein the first gate electrode and the second gate electrode correspond to a portion of a conductive line extending in a second direction perpendicular to the first direction. The quinoa mask ROM device according to claim 10, wherein the first gate electrode and the second gate electrode are made of polysilicon doped with impurities. 15. The neater mask rom device according to claim 14, wherein a metal silicide film is stacked on an upper surface of the first gate electrode, an upper surface of the second gate electrode, and a substrate surface positioned next to the spacer. The NOA mask ROM of claim 10, wherein the first impurity regions provided as sources among the first impurity regions adjacent to both sidewalls of the first gate electrode are connected to each other in an extension direction of the first gate electrode. device. Forming a gate oxide film on a substrate in which the on cell region, the off cell region, and the logic circuit region are divided; Forming first and second gate electrodes on the gate oxide layers of the on cell region and the off cell region, and third and fourth gate electrodes on the gate oxide layers of the logic circuit region, respectively; Preliminary first impurity regions and preliminary agents are implanted by first ion implanting impurities of a first conductivity type into a substrate of an on-cell region on both sides of the first gate electrode and a substrate of a logic circuit region on both sides of the third gate electrode Forming an impurity region; Forming first to fourth spacers on both sidewalls of the first to fourth gate electrodes, respectively; The second ion is implanted with impurities of the first conductivity type under the surface of the substrate between the first to third spacers, so that one end of the on-cell region is at least opposite to both sidewalls of the first gate electrode. Forming a third impurity region on each of the extended first impurity region, a second impurity region positioned at one end of the off cell region to face the bottom surface of the spacer, and a substrate on both sides of the third gate electrode of the logic circuit region; step; And And forming a fourth impurity region by performing third ion implantation of a second conductivity type impurity under the surface of the substrate between the fourth spacers. The method of claim 17, Forming an interlayer insulating film covering the first to fourth gate electrodes; Etching a portion of the interlayer insulating film to form a contact hole exposing at least one of the first to fourth impurity regions; And And filling the inside of the contact hole with a conductive material to form a contact. 18. The method of claim 17, further comprising: forming a device isolation pattern having an isolated shape having a first direction in a length direction on a substrate corresponding to the on cell region and the off cell region. Method of manufacturing the device. The method of claim 19, wherein the first and second gate electrodes respectively correspond to a partial region in the conductive line extending in a second direction perpendicular to the first direction. Forming the first and second gate electrodes, Forming a conductive film on the gate oxide film; And And patterning the conductive film to have a line shape extending in a second direction. 18. The method of claim 17, wherein the first to fourth gate electrodes include polysilicon doped with impurities. 22. The device of claim 21, further comprising forming a metal silicide film pattern on upper surfaces of the first to fourth gate electrodes and a surface of a substrate positioned next to the spacers. Method of preparation. The method of claim 17, wherein forming the preliminary first impurity region comprises: Forming an ion implantation mask pattern covering the off cell region and the logic circuit region where the fourth gate electrode is formed; Implanting an impurity into a logic circuit region in which the on cell region and the third gate electrode are exposed by the ion implantation mask; And And removing the ion implantation mask. 18. The method of claim 17, prior to forming the fourth gate electrode, And forming a channel region by injecting impurities of a first conductivity type into the substrate of the logic circuit region for forming the fourth gate electrode.

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