KR20050058045A - Color filter on thin film transistor array substrate and method for fabricating the same - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate and a method of manufacturing the same, in which a color filter capable of preventing a pattern defect and a decrease in aperture ratio of a color filter is formed.

The present invention provides a thin film transistor array comprising a thin film transistor connected between a gate line and a data line defining a pixel region, and a protective film protecting them; Color filters formed in a horizontal stripe shape on the protective layer such that colors are distinguished based on the gate line; A black matrix formed on the passivation layer along the gate line; Each pixel region includes a pixel electrode formed on a color filter and connected to the thin film transistor.

Description

Thin film transistor substrate with color filter and manufacturing method thereof {Color Filter On Thin Film Transistor Array Substrate And Method For Fabricating The Same}

The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor array substrate having a color filter and a method of manufacturing the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel (hereinafter, referred to as a liquid crystal panel) in which liquid crystal cells are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In general, the liquid crystal panel includes a thin film transistor substrate and a color filter substrate facing each other, a liquid crystal injected between the two substrates, and a spacer for maintaining a cell gap between the two substrates.

The thin film transistor substrate is composed of a pixel electrode formed for each liquid crystal cell region defined by the intersection of a gate line and a data line, a thin film transistor connected between the gate line and the data line and the pixel electrode, a plurality of insulating films, and an alignment film applied thereon.

The color filter substrate includes a color filter formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal in common, and an alignment layer applied thereon.

The thin film transistor substrate and the color filter substrate are bonded to each other to inject and encapsulate a liquid crystal to complete a liquid crystal panel, or to form a liquid crystal on any one of the two substrates and then attach the liquid crystal panel. At this time, the two substrates are aligned and bonded so that the color filter of the color filter substrate corresponds one-to-one with the pixel electrode of the thin film transistor substrate. However, when the alignment of the two substrates is not correct, light leakage defects occur. In order to prevent this, there is a method of forming a wide black matrix width of the color filter substrate, but this causes a decrease in the aperture ratio.

Therefore, in recent years, a color filter on thin film transistor (COT) structure for forming a color filter on a thin film transistor substrate has been proposed.

1 and 2, a COT array substrate includes a thin film transistor array including a gate line 2, a data line 4, a thin film transistor 6, and the like, and a color filter R formed on the thin film transistor array. The pixel electrodes 18 overlap with the color filters R, G, and B with the G, B) and black matrices 30 interposed therebetween.

The gate line 2 and the data line 4 are formed on the substrate 42 to intersect with the gate insulating layer 44 therebetween to define the pixel region.

The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 facing the source electrode 10. . The thin film transistor 6 includes an active layer 46 overlapping with the gate electrode 8 and the gate insulating film 44 therebetween to form a channel between the source electrode 10 and the drain electrode 12, and an active layer thereof. 46 and an ohmic contact layer 48 for reducing contact resistance between the source and drain electrodes 10, 12.

The storage upper electrode 22 overlaps the front gate line 2 and the gate insulating layer 52 to form a storage capacitor. The storage upper electrode 22 is formed in an integrated structure with the drain electrode 12 extending along the pixel area.

The passivation layer 50 is formed on the gate insulating layer 44 to cover the thin film transistor 6, the data line 4, and the storage upper electrode 22.

The color filters R, G, and B are formed on the passivation layer 50 so as to be classified for each pixel area. In detail, each of the color filters R, G, and B may be separated based on the gate line 2 and the data line 4 as shown in FIG. 3 in order to distinguish colors and to secure an exposed area of the storage upper electrode 22. The area is formed in a dot shape.

The black matrix 30 is formed on the passivation layer 50 on which the color filters R, G, and B are formed so as to extend to the adjacent color filters R, G, and B along the gate line 2 and the data line 4. And overlapping with the thin film transistor 6. The black matrix 30 prevents light leakage through the space between the color filters R, G, and B, external light reflection, and light leakage current due to the channel portion of the thin film transistor 6 being exposed to external light. do.

The planarization layer 52 made of an organic insulator is formed on the color filters R, G, and B and the black matrix 30. In the planarization layer 52, a contact hole 24 is formed through the planarization layer 52 and the passivation layer 50 to expose the storage upper electrode 22. The planarization layer 52 compensates for the step difference between the color filters R, G and B and the black matrix 30 to provide a flat surface, and from the color filters R, G and B and the black matrix 30 To prevent impurities from flowing into the liquid crystal.

The pixel electrode 18 is formed in each pixel area to overlap the color filters R, G, and B on the planarization layer 52, and is connected to the storage upper electrode 22 exposed through the contact hole 24. do.

As such, in the conventional COT array substrate, the color filters R, G, and B are formed in a dot shape as the space where the contact hole 24 is to be formed is needed. This is because the photoresist in which the pigment used as the material of the color filters R, G, and B is dispersed has a negative characteristic in which the exposed portion remains in a pattern, thereby making contact in the color filters R, G, and B. This is because it is difficult to form the hole 24. In addition, even when the dot-type color filters R, G, and B are formed, at least 40 µm or more, as shown in FIG. 4, between the color filters R, G, or B of the same color patterned in the same process for the reasons described above. Space A to have is necessary. If such a space A is not secured, a poor pattern of the color filter R or G or B occurs. Therefore, in order to form a dot pattern, the gap between color filters R, G, or B of the same color separated from the gate line 2, that is, the space A, must be increased, resulting in a decrease in aperture ratio. Furthermore, when the liquid crystal panel is made high in resolution and the pixel area is reduced, the problem of the decrease in aperture ratio due to the dot-type color filters R, G, and B becomes more serious.

On the other hand, the black matrix 30 overlapping the data line 4 forms a parasitic capacitor to delay the pixel signal supplied through the data line 4. The delay amount of the pixel signal increases as the data line 4 moves away from the driving circuit, resulting in deterioration in image quality due to insufficient charge amount of the pixel signal at the end of the data line 4. In addition, even in the case of using a resin instead of a metal (Cr or the like) as the material of the black matrix 30, the data line 4 and the parasitic capacitor are still formed, resulting in the above-described deterioration in image quality.

Accordingly, it is an object of the present invention to provide a COT array substrate and a method of manufacturing the same, which can prevent a pattern defect and a decrease in the aperture ratio of a color filter by horizontally forming the color filter.

Another object of the present invention is to provide a COT array substrate and a method of manufacturing the same, which can minimize the parasitic capacitance caused by the black matrix by removing the vertical black matrix by a horizontal stripe type color filter.

In order to achieve the above object, a COT array substrate according to an embodiment of the present invention includes a thin film transistor array including a thin film transistor connected between a gate line and a data line defining a pixel region, and a protective film for protecting them; Color filters formed in a horizontal stripe shape on the protective layer such that colors are distinguished based on the gate line; A black matrix formed on the passivation layer along the gate line; Each pixel region includes a pixel electrode formed on a color filter and connected to the thin film transistor.

The black matrix is formed over an adjacent color filter covering the thin film transistor.

The present invention further includes a storage upper electrode overlapping the gate line and the gate insulating layer therebetween to form a storage capacitor.

The drain electrode of the thin film transistor extends in the vertical direction of the pixel region, and the storage upper electrode is integrated with the extended drain electrode.

Further, the present invention further includes a planarization layer that compensates for the step difference between the color filter and the black matrix to provide a flat surface on which the pixel electrode is to be formed.

In addition, the present invention further includes a contact hole penetrating the planarization layer and the passivation layer to expose the upper storage electrode, and the pixel electrode is connected to the upper storage electrode through the contact hole.

The color filter is disposed with a space between the adjacent color filter, the gate line, and the contact hole formed therebetween, and the black matrix is formed to expose the space where the contact hole is to be formed.

A method of manufacturing a thin film transistor array substrate having a color filter according to the present invention includes the steps of forming a thin film transistor array including a thin film transistor connected between a gate line and a data line defining a pixel region, and a protective film protecting them; Forming color filters on the passivation layer in a horizontal stripe type so that colors are distinguished based on the gate line; Forming a black matrix on the passivation layer along the gate line; And forming a pixel electrode on the color filter for each pixel region so as to be connected to the thin film transistor.

The color filter is formed by repeating the pigment layer printing, exposure and development processes for each color.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 8.

5 is a plan view of a portion of a COT array substrate according to an embodiment of the present invention, Figures 6 and 7 are cut along the line II-II ', III-III' of the COT array substrate shown in Figure 5 It is sectional drawing.

5 to 7 includes a thin film transistor array including a gate line 102, a data line 104, a thin film transistor 106, and the like, and a horizontal stripe type on the thin film transistor array. And a pixel electrode 118 overlapping the color filters R, G, and B with the color filters R, G, and B formed thereon and the black matrix 130 and the planarization layer 152 therebetween.

The gate line 102 and the data line 104 are formed on the substrate 142 to intersect with the gate insulating layer 144 therebetween to define a pixel area.

The thin film transistor 106 includes a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, and a drain electrode 12 facing the source electrode 110. . The thin film transistor 106 includes an active layer 146 overlapping with the gate electrode 108 and the gate insulating layer 144 therebetween to form a channel between the source electrode 110 and the drain electrode 112, and an active layer thereof. 146 and an ohmic contact layer 148 to reduce contact resistance between the source and drain electrodes 110 and 112.

The storage upper electrode 122 overlaps the front gate line 102 and the gate insulating layer 144 to form a storage capacitor. The storage upper electrode 122 is formed in an integrated structure with the drain electrode 112 extended along the pixel area.

The passivation layer 150 is formed on the gate insulating layer 144 to cover the thin film transistor 106, the data line 104, and the storage upper electrode 122.

The color filters R, G, and B are formed on the passivation layer 50 so as to distinguish colors in units of horizontal lines. In detail, the color filters R, G, and B are formed in a horizontal stripe type so that colors are distinguished based on the gate line 102. These color filters R, G, and B are sequentially formed for each color with the space B to be exposed of the storage upper electrode 122 interposed therebetween as shown in FIG. 8. Accordingly, the same color filters R or G or B can structurally secure at least two dots or more in the vertical direction. Therefore, in the patterning process, pattern defects due to lack of process margins between the same color filters R, G, or B may be prevented, and reduction of aperture ratio for process margins may be prevented.

The black matrix 130 is formed to extend to the adjacent color filters R, G, and B along the gate line 102 on the passivation layer 150 where the color filters R, G, and B are formed, and the thin film transistor 106. It is formed to overlap with). However, the black matrix 130 is formed so as not to overlap the region where the storage upper electrode 122 is exposed by the contact hole. The black matrix 130 prevents light leakage through the space between the color filters R, G, and B, external light reflection, and light leakage current due to the channel portion of the thin film transistor 106 being exposed to external light. do. In particular, the black matrix 130 does not need a vertical portion overlapping the data line 104 as the color filters R, G, and B are formed in a horizontal stripe shape. Accordingly, parasitic capacitance between the black matrix 130 and the data line 104 can be minimized.

On the color filters R, G, and B and the black matrix 130, a planarization layer 152 made of an organic insulator (photo acryl, etc.) is formed. A contact hole 124 is formed in the planarization layer 152 to expose the storage upper electrode 122 through the planarization layer 152 and the passivation layer 150. The planarization layer 152 compensates for the step difference between the color filters R, G and B and the black matrix 130 to provide a flat surface, and from the color filters R, G and B and the black matrix 130. To prevent impurities from flowing into the liquid crystal.

The pixel electrode 118 is independently formed to overlap the color filters R, G, and B in each pixel area on the planarization layer 152, and the storage upper electrode 122 exposed through the contact hole 124. Connected.

A method of manufacturing a COT array substrate according to an embodiment of the present invention having such a structure will be described below with reference to FIGS. 9A to 9E.

9A is a cross-sectional view illustrating a thin film transistor array in a COT array substrate according to an embodiment of the present invention.

In the first mask process, a gate metal pattern including the gate line 102 and the gate electrode 108 is formed on the substrate 142. Specifically, the gate metal layer is formed on the lower substrate 142 through a deposition method such as a sputtering method. Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd) are used as the gate metal layer. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a gate metal pattern including the gate line 102 and the gate electrode 108 protruding from the gate line 102. .

Subsequently, a gate insulating layer 144 is formed on the substrate 142 on which the gate lines and the electrodes 102 and 108 are formed through a deposition method such as PECVD or sputtering. As the material of the gate insulating film 144, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

In the second mask process, a semiconductor pattern including an active layer 146 and an ohmic contact layer 148 is formed on the gate insulating layer 144. In detail, a semiconductor layer, that is, an amorphous silicon layer and an n + amorphous silicon layer, is deposited on the gate insulating layer 144 through a deposition method such as PECVD or sputtering. Subsequently, the semiconductor layer is etched by the photolithography process and the etching process using the second mask to form a semiconductor pattern including the active layer 146 and the ohmic contact layer 148.

A source / drain metal pattern including the data line 102, the source and drain electrodes 110 and 112, and the storage upper electrode 122 is formed on the gate insulating layer 144 on which the semiconductor pattern is formed. In detail, the source / drain metal layer is deposited on the gate insulating layer 152 on which the semiconductor pattern is formed through a deposition method such as PECVD or sputtering. As the source / drain metal layer, Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd) and the like are used. Subsequently, the source / drain metal layer is etched by the photolithography process and the etching process using the third mask to face the source electrode 110 and the source electrode 112 protruding from the data line 102 and the data line 102. A source / drain metal pattern is formed that includes the drain electrode 114 and the storage upper electrode 122 that is integrated with the extended drain electrode 114 and overlaps a portion of the front gate line 102. Next, the active layer 146 is exposed by removing the ohmic contact layer 148 exposed between the source electrode 112 and the drain electrode 114 as a mask.

Meanwhile, the above-described semiconductor pattern and the source / drain metal pattern may be formed using one mask when using a partially transmissive (diffractive exposure or semitransmissive) mask.

Next, the passivation layer 150 is formed on the gate insulating layer 144 on which the source / drain metal pattern is formed. As the material of the protective film 150, an inorganic insulating material such as the gate insulating film 144 or an organic insulating material is used.

9B is a cross-sectional view illustrating color filters R, G, and B formed on the thin film transistor array.

Color filters R, G, and B are sequentially formed on the passivation layer 150 by the fourth to sixth mask processes. Specifically, a horizontal stripe-type red color filter R is formed by applying a photoresist in which red pigment is dispersed on the passivation layer 150, and then exposing and developing the photoresist using a fourth mask. In this case, the horizontal stripe type red color filter R has an interval of at least two dots in the vertical direction. Accordingly, the process margin between the red color filters R for forming the pattern is sufficiently secured structurally. Subsequently, the fifth to sixth mask processes are repeated as described above to form horizontal striped green and blue color filters G and B separated based on the gate line 102.

FIG. 9C is a cross-sectional view of the black matrix 30 formed on the thin film transistor array on which the color filters R, G, and B are formed.

The black matrix is formed on the passivation layer 150 in which the color filters R, G, and B are formed by the seventh mask process. Specifically, an adjacent color is formed along the gate line 102 by forming a black resin layer covering the color filters R, G, and B on the passivation layer 152 and then patterning the photoresist and etching processes using a seventh mask. The horizontal striped black matrix 130 is formed to span the filters R, G, and B.

9D is a cross-sectional view illustrating the planarization layer 152 formed on the color filters R, G, and B and the black matrix 30.

In the eighth mask process, the planarization layer 152 having the contact holes 24 is formed on the color filters R, G, and B and the black matrix 130. Specifically, the planarization layer 152 is formed on the color filters R, G, and B and the black matrix 130 through a spin coating method. As the material of the planarization layer 152, an organic insulating material having a high degree of planarization, such as photoacryl, is used. Subsequently, the planarization layer 152 and the lower protective layer 150 are patterned by a photolithography process and an etching process using an eighth mask to form a contact hole 124 exposing the storage upper electrode 122.

9E is a cross-sectional view illustrating the pixel electrode 118 formed on the planarization layer 152.

The pixel electrode 118 is independently formed in each pixel area on the planarization layer 152 by the ninth mask process. Specifically, the transparent conductive film is formed on the planarization layer 152 through a deposition method such as sputtering. ITO, TO, IZO, etc. are used as a transparent conductive film. Subsequently, the pixel electrode 118 is formed by patterning the transparent conductive film through a photolithography process and an etching process using a ninth mask. The pixel electrode 118 is connected to the storage upper electrode 122 through the contact hole 124.

As described above, in the COT array substrate and the method of manufacturing the same according to the present invention, as the color filters are formed in the horizontal stripe shape, a space of at least 2 dots between the color filters of the same color can be secured structurally. Accordingly, in the patterning process of the color filter, pattern defects due to lack of process margins between the same color filters R, G, or B may be prevented, and reduction of the aperture ratio for securing process margins may be prevented.

In addition, in the COT array substrate and the manufacturing method thereof according to the present invention, since the color filter is formed in a horizontal stripe shape, the vertical portion of the black matrix overlapping with the data line is unnecessary. Accordingly, the parasitic capacitance between the black matrix and the data line can be minimized to reduce the signal delay amount, thereby preventing deterioration in image quality.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view partially showing a conventional COT array substrate.

FIG. 2 is a cross-sectional view of the COT array substrate shown in FIG. 2 taken along the line II ′. FIG.

3 is a plan view showing a structure in which a color filter is formed in the COT array substrate shown in FIG.

4 is a plan view briefly showing the color filter arrangement structure in the COT array substrate shown in FIG.

5 is a plan view partially showing a COT array substrate according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view of the COT array substrate shown in FIG. 5 taken along a line II-II '.

FIG. 7 is a cross-sectional view of the COT array substrate of FIG. 5 taken along line III-III ′. FIG.

FIG. 8 is a plan view briefly showing the color filter arrangement structure in the COT array substrate shown in FIG. 5; FIG.

9A to 9E are cross-sectional views for explaining a method of manufacturing a COT array substrate in accordance with an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

2, 102: gate line 4, 104: data line

6, 106 thin film transistor 8, 108 gate electrode

10, 110: source electrode 12, 112: drain electrode

24 and 124: contact holes 18 and 118: pixel electrodes

22, 122: storage upper electrode 30, 130: black matrix

42, 142: substrate 44, 144: gate insulating film

46, 146: active layer 48, 148: ohmic contact layer

50, 150: first protective film 52, 152: second protective film

R, G, B: Color filter A, B: Color filter removal area

Claims (15)

A thin film transistor array including a thin film transistor connected between a gate line and a data line defining a pixel region, and a protective film protecting them; Color filters formed in a horizontal stripe shape on the protective layer such that colors are distinguished based on the gate line; A black matrix formed on the passivation layer along the gate line; And a pixel electrode formed on each color region on the color filter and connected to the thin film transistor. The method of claim 1, The black matrix is And a color filter formed over an adjacent color filter while covering the thin film transistor. The method of claim 1, And a storage upper electrode overlapping with the gate line and the gate insulating layer therebetween to form a storage capacitor. The method of claim 3, wherein The thin film transistor array substrate having a color filter, wherein the drain electrode of the thin film transistor extends in a vertical direction of the pixel region, and the storage upper electrode is integrated with the extended drain electrode. The method according to any one of claims 1 and 4, And a planarization layer for compensating for the step difference between the color filter and the black matrix to provide a flat surface on which the pixel electrode is to be formed. The method of claim 5, A contact hole penetrating the planarization layer and the passivation layer to expose the storage upper electrode; And the pixel electrode is connected to the storage upper electrode through the contact hole. The method of claim 6, The color filter is a thin film formed with a color filter, wherein the color filter is disposed between the gate line and the space where the contact hole is to be formed, and the black matrix is formed to expose the space where the contact hole is to be formed. Transistor array substrate. Forming a thin film transistor array including a thin film transistor connected between a gate line and a data line defining a pixel region, and a protective film protecting them; Forming color filters on the passivation layer in a horizontal stripe type so that colors are distinguished based on the gate line; Forming a black matrix on the passivation layer along the gate line; And forming a pixel electrode on the color filter for each pixel region so as to be connected to the thin film transistor. The method of claim 8, The black matrix is And a color filter formed over an adjacent color filter while covering the thin film transistor. The method of claim 8, And forming a storage upper electrode overlapping the gate line with the gate insulating layer therebetween to form a storage capacitor. The method of claim 10, The drain electrode of the thin film transistor extends in the vertical direction of the pixel region, and the storage upper electrode is integrated with the extended drain electrode. The method according to any one of claims 8 and 11, And forming a planarization layer that compensates for the step difference between the color filter and the black matrix to provide a flat surface on which the pixel electrode is to be formed. The method of claim 12, Forming a contact hole through the planarization layer and the passivation layer to expose the storage upper electrode; And the pixel electrode is connected to the storage upper electrode through the contact hole. The method of claim 13, The color filter is disposed with an adjacent color filter interposed between the gate line and the space where the contact hole is to be formed, and the black matrix is formed such that the space where the contact hole is to be formed is exposed. Method of manufacturing a thin film transistor array substrate. The method of claim 8, The color filter is a method of manufacturing a thin film transistor array substrate having a color filter, characterized in that formed by repeating the pigment layer printing, exposure, development process for each color.