KR20050052730A - Thin film transistor for lcd and method for fabrication the same - Google Patents

Abstract

The present invention relates to a thin film transistor of a liquid crystal display device using polysilicon and a method of manufacturing the same.

In the liquid crystal display integrated with a driving circuit, when the N-type and P-type thin film transistors, which are the driving element CMOS element and the switching element of the display unit, are formed on the substrate at the same time, the gate insulating film formed thereon by the gate electrode has a step difference, and therefore Therefore, the amorphous silicon layer formed on the gate insulating film also has a step. When the step of crystallizing the amorphous silicon layer having the step into the polysilicon layer, the crystallization characteristic is lowered by the stepped portion, there is a problem that the disconnection of the polysilicon layer occurs.

The present invention provides a method of manufacturing a thin film transistor of a liquid crystal display device having excellent crystallization characteristics and formation of a polysilicon layer having no step by performing a CMP process after forming a gate insulating film.

Description

Thin film transistor for liquid crystal display device and manufacturing method therefor {Thin film transistor for LCD and method for fabrication the same}

The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor having a bottom gate structure using a chemical mechanical polishing (CMP) process.

Recently, with the rapid development of the information society, there is a need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption. displays are actively being developed.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which two electrodes are formed face each other, inserting a liquid crystal material between the two substrates, and then applying voltage to the two electrodes. It is a device that expresses an image by the transmittance of light that varies depending on the movement of liquid crystal molecules by moving the liquid crystal molecules by an electric field.

The lower substrate of the liquid crystal display includes a thin film transistor that is a switching element. In the active layer, one of the components of the thin film transistor, amorphous silicon (a-Si: H) is mainly used. This is because amorphous silicon can be formed on a large substrate such as a low cost glass substrate at low temperature.

However, a driving circuit is required to drive the thin film transistor using such amorphous silicon. The driving circuit includes a plurality of complementary metal oxide semiconductor (CMOS) devices, and single crystal silicon is used to form such a CMOS device.

Accordingly, the liquid crystal display device is driven by connecting a large scale integration made of single crystal silicon to a thin film transistor array substrate made of amorphous silicon by a method such as tape automated bonding (TAB). However, since the price of the driving circuit is very high, such a liquid crystal display has a disadvantage of high price.

Recently, a liquid crystal display device employing a thin film transistor using polysilicon (poly-Si) has been widely researched and developed. In the liquid crystal display device using polysilicon, the switching element of the display unit and the CMOS element of the driving unit can be formed on the same substrate, and the process is simplified since the process of connecting the switching element and the driving circuit is unnecessary. In addition, polysilicon has a field response mobility of about 100 to 200 times greater than that of amorphous silicon, so it has a fast response speed and excellent stability to temperature and light.

Such polysilicon may be formed by depositing amorphous silicon by as-deposition, plasma enhanced chemical vapor deposition, or low pressure chemical vapor deposition, and then crystallizing it. .

Polysilicon formation using amorphous silicon includes solid phase crystallization (SPC), metal induced crystallization (MIC), laser annealing, and sequential side solidification ( sequential lateral solidification (hereinafter referred to as SLS method).

The above-described silicon crystallization method can be applied to manufacturing a driving device or a switching device. In general, the higher the resolution of the liquid crystal display device, the shorter the pad pitch of the signal line and the scan line, and thus, the TCP (Tape Carrier Package), which is a general driving circuit mounting method, becomes difficult to bond itself. However, fabricating a drive circuit directly on the substrate with polysilicon reduces drive IC costs and simplifies mounting.

1 is a schematic diagram of an array substrate on which a driving circuit is formed using polysilicon.

As shown, the driving circuit portion 5 and the pixel portion 2 are formed on the substrate 1 together. The pixel portion 2 is positioned at the center of the substrate 1, and gate and data driving circuit portions 5a and 5b are positioned at one side of the pixel portion 2 and the other side not parallel thereto. In the pixel portion 2, a plurality of gate wires 7 connected to the gate driving circuit part 5a and a plurality of data wires 49 connected to the data driving circuit part 5b cross each other. The pixel electrode 66 is formed in the pixel region P defined by the intersecting lines 49, and the thin film transistor Tr connected to the pixel electrode 10 is positioned at the intersection of the two wires 7 and 49. do.

In addition, the gate and data driving circuit unit are connected to an external signal input terminal 11.

The gate and data driving circuit units 5a and 5b control an internal signal input through the external signal input terminal 11 to control the display to the pixel unit 2 through the gate and data lines 7 and 49, respectively. Apparatus for supplying signals and data signals.

Accordingly, in the gate and data driving circuit portions 5a and 5b, a complementary metal-oxide semiconductor (CMOS) element, which is an inverter, is formed inside the driving circuit portion to properly output an input signal.

As shown in the figure, the CMOS device is a complementary MOS device combining an N-type transistor and a P-type transistor, and is a circuit that operates as an inverter, and has an advantage of consuming very little power. .

Since the CMOS device requires fast operating characteristics, the polysilicon layer as described above is used as the semiconductor layer, and when the semiconductor layer, in particular, the active layer is used as polysilicon, a high mobility can be obtained. There is an advantage that the quality of the picture is improved.

Hereinafter, a structure and a manufacturing method of a thin film transistor formed on an array substrate of a liquid crystal display device using polysilicon to form a driving device or a switching device will be described with reference to the accompanying drawings.

2 and 3 are cross-sectional views illustrating cross sections of the switching device and the CMOS device, respectively, in which FIG. 2 illustrates the switching device of the display unit, and FIG. 3 illustrates the CMOS device of the driving unit.

As illustrated, a silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is deposited on the transparent insulating substrate 1 on which the switching element region and the CMOS element region are defined to form a buffer layer 3.

Next, a metal material is deposited and patterned on the buffer layer 3 to form gate electrodes 6, 9, and 12 in the display unit and the driver unit. Thereafter, silicon oxide (SiO ₂ ), which is an inorganic insulating material, is deposited on the gate electrodes 6, 9, and 12 to form a gate insulating layer 16.

Next, amorphous silicon (a-Si) is deposited on the gate insulating layer 16 to form an amorphous silicon layer. Next, the amorphous silicon layer is crystallized to form a polysilicon layer, and then a photoresist is applied to a specific region to form a blocking mask (not shown), p + doping, n + doping, and n−. By sequentially doping, polysilicon semiconductor layers 35 and 38 including n + and n− doped regions are formed in the thin film transistor, which is the switching element of the display unit, and the N-type thin film transistor forming units T and C1 of the driver unit. In the P-type thin film transistor forming unit C2 of the driving unit, a polysilicon semiconductor layer 28 including a p + doped region is formed. At this time, in each of the regions T, C1, and C2, the semiconductor layers 28b, 35c, and 38c corresponding to the gate electrodes 6, 9, and 12 are active layers 28b of the pure polysilicon layer which are not doped. , 35c, 38c).

Next, a metal material is deposited and patterned on the n +, p + and n− doped semiconductor layers 28, 35, and 38 to form source and drain electrodes (50a, 53a, 56a, 50b, 53b, 56b). To form. In this case, exposed semiconductor layers other than the source and drain electrodes 50a, 53a, 56a, and 50b, 53b, and 56b may be removed by etching the regions T, C1, and C2.

Next, an inorganic insulating material is deposited on the source and drain electrodes 50a, 53a, 56a, 50b, 53b, and 56b and the exposed gate insulating layer to form a protective layer 60, and to form a thin film transistor in the display unit. In the part T, the protective layer 60 is patterned to form a drain contact hole 63 exposing the drain electrode 50b. Next, a transparent conductive material is deposited and patterned on the passivation layer 60 where the drain contact hole 63 is formed to form the pixel electrode 66. The pixel electrode 66 is in contact with the exposed drain electrode 50b and is formed for each pixel.

In the thin film transistor of the display unit and the driver unit of the bottom gate structure, which is a component of the liquid crystal display device using the polysilicon described above, the gate insulating layer 16 formed on the gate electrodes 6, 9, and 12 is formed on the lower gate electrode ( 6, 9, and 12 are formed with a step, and the step coverage is poor due to the step, and the problem of disconnection of the semiconductor layers 28, 35, and 38 formed on the gate insulating layer 16 occurs. In addition, in the crystallization process that proceeds when the semiconductor layers 28, 35, 38 of polysilicon are formed, the lowering of the crystallization characteristic of the crystallized semiconductor layers 28, 35, 38 after the crystallization process is caused by the step difference. There is a problem that occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to manufacture a thin film transistor having a bottom gate structure, and after forming a gate insulating film, a step of forming a gate insulating film by introducing a CMP process, which is a chemical mechanical polishing process, is formed. The present invention provides a method of manufacturing a thin film transistor of a liquid crystal display device capable of preventing disconnection of the semiconductor layer due to the step and improving crystallization characteristics when forming a semiconductor layer of polysilicon using a crystallization process.

In order to achieve the above object, a method of manufacturing a thin film transistor for a liquid crystal display device using polysilicon according to the present invention includes forming a gate electrode on a substrate; Forming a first gate insulating film over the gate electrode; Performing a chemical mechanical polishing (CMP) process on the surface of the first gate insulating layer to planarize the step of the first insulating layer on the substrate on which the first gate insulating layer is formed; Forming a second gate insulating film on the first gate insulating film planarized by the CMP process; Forming a polysilicon layer over the second gate insulating film; The polysilicon layer is defined as a first region of the central portion and a second region located on both sides of the first region, and an active layer comprising a polysilicon layer of the first region by doping the second region of the polysilicon layer. Forming a semiconductor layer comprising a layer and an ohmic contact layer comprising the second region; Forming source and drain electrodes spaced apart from each other with the active layer interposed therebetween on the semiconductor layer; Forming a protective layer on the source and drain electrodes.

In this case, the minimum thickness of the first gate insulating film before the CMP process is preferably at least 90% of the thickness of the gate electrode.

In addition, forming the polysilicon may include forming an amorphous silicon layer; And crystallizing the amorphous silicon layer.

In addition, an n-doped LDD layer may be further formed between the ohmic contact layer and the active layer, wherein the ohmic contact layer is an n + doped ohmic contact layer.

The method may further include forming a buffer layer on the substrate before forming the gate electrode.

The thin film transistor according to the present invention comprises a gate electrode; A gate insulating film having a flat surface on the gate electrode by a chemical mechanical polishing CMP process; A semiconductor layer formed on the gate insulating layer without a step, the active layer having a portion corresponding to the gate electrode, and an ohmic contact layer having a predetermined interval extending from both ends of the active layer; Source and drain electrodes contacting the ohmic contact layer on the semiconductor layer and spaced apart from each other by a predetermined distance; And a protective layer formed on the source and drain electrodes.

In this case, the gate insulating film having the flat surface may include a first gate insulating film and a second gate insulating film. In this case, the first gate insulating film may be polished by a CMP process to have a flat surface.

In addition, the method of manufacturing an array substrate having a thin film transistor according to the present invention includes a display portion including an n-type thin film transistor, which is a switching element, on the substrate, and comprising a plurality of pixels defined by intersections of gate wirings and data wirings, n-type and A liquid crystal display device having a driving circuit including a driving unit including a plurality of CMOS elements including p-type thin film transistors, wherein the I region where the n-type thin film transistor of the display unit is formed and the n-type and p-type thin film transistors of the driving unit are respectively formed. Forming a gate electrode in said regions I to III on the substrate defined by region II and III; Forming a first gate insulating film over the gate electrode; Performing a chemical mechanical polishing (CMP) process on the surface of the first gate insulating layer to planarize the step of the first insulating layer on the substrate on which the first gate insulating layer is formed; Forming a second gate insulating film on the first gate insulating film planarized by the CMP process; Forming a polysilicon layer over the second gate insulating film; Performing n + and n− doping to the I and II regions of the polysilicon layer and p + doping to the III region at the same time; Forming source and drain electrodes spaced apart from each other by a predetermined distance on the doped polysilicon layer; Forming a protective layer on a front surface of the source and drain electrodes; Patterning a passivation layer formed in region I to form a drain contact hole exposing a lower drain electrode; Forming a pixel electrode in contact with the exposed drain electrode over the passivation layer of the region I in which the drain contact hole is formed.

Hereinafter, a method of manufacturing a thin film transistor of a liquid crystal display using polysilicon according to the present invention will be described in detail with reference to the accompanying drawings.

The driving circuit-integrated liquid crystal display device using polysilicon has already been described in the related art, and thus description thereof is omitted in the present invention. In addition, the present invention provides a liquid crystal display device having a silicon-based semiconductor layer, wherein the thin film transistor having a bottom gate structure constituting a CMOS element of a driver and a switching element of a display is formed on a substrate. A method of manufacturing a transistor.

4A to 4M are process cross-sectional views of a display unit switching element of a liquid crystal display device with integrated drive circuit according to the present invention, and FIGS. 5A to 5M are process cross-sectional views of a CMOS element of a drive unit of a liquid crystal display device integrated with a drive circuit according to the present invention, respectively. It is sectional drawing of a manufacturing process of a type | mold and a P type thin film transistor. At this time, the switching element forming portion I of the display portion, the N-type thin film transistor forming portion II of the driving portion, and the P-type thin film transistor forming portion of the driving portion III are respectively shown on the drawing.

First, as illustrated in FIGS. 4A and 5A, silicon oxide (SiO ₂ ) is entirely deposited on the transparent insulating substrate 100 to form a buffer layer 103 having a predetermined thickness. When the amorphous silicon layer is crystallized into a polysilicon layer, the buffer layer 103 may generate alkali ions, such as potassium ions (K +), sodium ions (Na +), and the like that exist inside the substrate by heat. This is to prevent the film quality of the polysilicon layer from deteriorating by ions.

Subsequently, a metal material such as chromium (Cr), aluminum (Al), or molybdenum (Mo) is deposited on the entire surface of the substrate 100 on the buffer layer 103, and a first mask process is performed to perform a gate electrode. (105, 109, 112) are formed in regions I, II, and III, respectively.

Next, as shown in FIGS. 4B and 5B, one selected from silicon oxide (SiO ₂ ) or silicon nitride (SiNx), which is an inorganic insulating material, is formed on the substrate 100 on which the gate electrodes 106, 109, and 112 are formed. The first gate insulating layer 115 is formed by increasing the substrate 100 over the entire surface of the substrate 100. In this case, the first gate insulating layer 115 may have a thickness similar to that of the gate electrodes 105, 109, and 112, and is formed thicker than 90% of the thickness of the gate electrode. A portion of the first gate insulating layer 115 formed on the buffer layer 103 and a portion of the first gate insulating layer 115 formed on the buffer layer 103 and the gate electrode 105, 109, 112 are formed with a step difference. .

Next, as shown in FIGS. 4C and 5C and 4D and 5D, a chemical mechanical polishing (CMP) process, which is chemical mechanical polishing, is performed on the first gate insulating layer 115 having the step, thereby forming a part having the step. Make it flat. The CMP process is a process for removing a protruding portion of the surface of a wafer or a substrate to pattern or pattern a material that is difficult to form a pattern by conventional dry etching. It combines and etches chemical reaction effects. A liquid slurry (not shown) containing an abrasive in an acid or base solution is injected into the CMP apparatus 120 to smooth out the stepped portions on the substrate by mechanical polishing by the abrasive and chemical action by the slurry. It is.

At this time, as shown in the drawing, when the first gate insulating film 115 is formed to be thinner than the gate electrode, the surface of the gate electrodes 105, 109 and 112 including the first gate insulating film 115 to form a step may be included. Some are also polished. Alternatively, when the first gate insulating layer 115 is formed thicker than the thickness of the gate electrodes 105, 109 and 112, only the stepped first gate insulating layer 115 on the gate electrodes 105, 109 and 112 is polished. And the lower gate electrodes 105, 109, 112 may not be polished.

Next, as illustrated in FIGS. 4E and 5E, a gate electrode exposed by depositing the same inorganic insulating material as the first gate insulating film 115 on the first gate insulating film 115 polished and flattened by the CMP process ( A second gate insulating layer 116 having a predetermined thickness is formed on the entire surface of the substrate 100 including 105, 109, and 112. In this case, since the lower portion of the second gate insulating layer 116 is flat, a naturally flat layer is formed.

Next, the amorphous silicon layer is deposited on the planarly formed second gate insulating layer 116 to form an amorphous silicon layer having a predetermined thickness, and the amorphous silicon layer is crystallized by performing a crystallization process using a laser or the like on the amorphous silicon layer. Thus, the polysilicon layer 125 is formed. In the crystallization process using the laser or the like, since the amorphous silicon layer is formed flat without having a step, the laser beam to be irradiated with an appropriate energy density can be performed without adjusting its position according to the step. Therefore, the change in the energy density of the laser beam irradiated to the amorphous silicon layer is less than the case of irradiating to the amorphous silicon layer having a step, that is, the error range of the laser beam energy density is reduced, the polysilicon with good crystallization characteristics Layer 125 may be formed.

Next, as shown in 4f and 5f, a photoresist is applied onto the flatly formed polysilicon layer 125, and a second mask process is performed to form a photoresist on the entire polysilicon layer 125 in regions I and II. The pattern 130 is formed, and the photoresist pattern 130 is formed to cover only the polysilicon layer 128b corresponding to the gate electrode 112 in the region III.

Subsequently, p + doping by ion implantation of a first dose is performed to the polysilicon layer 128a exposed to the outside of the photoresist pattern 130 using the photoresist pattern 130 as a blocking mask. At this time, the polysilicon layer 125 in the I and II regions is not doped because the photoresist pattern 130 acts as a blocking mask, and in the region III, the portion corresponding to the gate electrode 112 in the polysilicon layer 128 is not doped. Only the polysilicon layer 128b is not doped by the photoresist pattern 130 formed thereon, and the other portions are p + doped to form a p-type ohmic contact layer 128a, and the p + undoped polysilicon layer ( 128b forms an active layer 128b.

Next, as shown in FIGS. 4G and 5G, the photoresist pattern (130 of FIGS. 4F and 5F) used as the blocking mask during the p + doping is removed by an ashing or stripping process. Then, a new photoresist is again applied on the polysilicon layers 128, 135, and 138 in the I, II, and III regions, and a third mask process is performed to form the photoresist pattern 132 for n + doping. At this time, in the I and II regions forming the N-type thin film transistor, the photoresist pattern 132 is formed to cover the gate electrodes 105 and 109 and the polysilicon layers 135c and 138c, and in the III region, The photoresist pattern 132 is formed to completely cover the entire polysilicon layer 128.

Next, n + doping is performed by implanting a second dose into the exposed polysilicon layers 135a and 138a using the photoresist pattern 132 as a blocking mask. At this time, the polysilicon layers 135c and 138c on the gate electrodes 105 and 109 of which the ion implantation is blocked by the photoresist pattern 132 among the polysilicon layers 135 and 138 in the I and II regions are not doped. And other portions are n + doped to form n-type ohmic contact layers 135a and 138a. In addition, the entire polysilicon layer 128 in the III region is not doped because ion implantation is blocked by the photoresist pattern 132.

Next, as shown in FIGS. 4H and 5H, partial etching is performed by using a dry etching apparatus to remove a predetermined interval at both ends of the photoresist pattern 132 used as a blocking mask during n + doping in regions I and II. The lower portions of the polysilicon layers 135b and 138b which are not doped are exposed. At this time, the photoresist pattern 143c in the region III is also simultaneously etched by the dry etching to expose a portion of the p + doped polysilicon layer 128 below.

Subsequently, n-doping is performed on the partially exposed polysilicon layers 135a, 135b, 138a, and 138b of each region by ion implantation of a third dose. At this time, the n + undoped polysilicon layers 135b and 138b below the portion where the photoresist pattern 132 is partially etched and removed in the I and II regions are n− doped to form the LDD layers 135b and 138b. To form.

Other exposed p + or n + doped polysilicon layers 135a, 138a, 128a are also n-doped but are not affected by n- doping since they are already doped with n + or p + at higher doses.

Next, as shown in 4i and 5i and 4j and 5j, chromium (Cr) and molybdenum in front of the substrate 100 over the n +, n- and p + doped polysilicon layers 135, 138 and 128 for each domain. A metal layer 140 having a predetermined thickness is formed by depositing a metal material such as (Mo). Thereafter, a photoresist is applied onto the metal layer 140, and a fourth mask process is performed to form photoresist patterns 143a and 143b. In this case, the photoresist patterns 143a and 143b are formed by varying the thickness by applying a diffraction exposure technique, and the photoresist is developed at a predetermined interval of the portion CR that is the boundary so that one independent device can be formed. To expose the metal layer 140 and form a thin photoresist pattern 143b at a portion corresponding to the gate electrodes 105, 109, 112 in the I, II, and III regions, and form the thin photoresist. Each end of the pattern 143b is extended to form a thick photoresist pattern 143a having a predetermined interval.

Next, a portion of the metal layer 140 exposed to the outside and the polysilicon layers 135a, 138a, and 128a below the metal layer 140 are disposed on the boundary portion CR where the photoresist patterns 143a and 143b are not formed. By simultaneously or successively etching, the polysilicon layers 135, 138, and 128 and the metal layer 140 are formed independently.

Next, as shown in FIGS. 4K and 5K, dry etching is performed on the photoresist patterns (143a and 143b of FIGS. 4J and 5J) formed on the metal layer 140 independently formed in I, II, and III regions. The photoresist pattern 143b is etched to expose metal layers (not shown) at predetermined intervals thereunder. At this time, the thickness of the thick photoresist pattern 143a becomes thinner, but the metal layers 150a, 150b, 153a, 153b, 156a, and 156b below it are not exposed.

Subsequently, the exposed metal layer (not shown) between the remaining photoresist patterns 143a that are not etched is etched to etch the lower polysilicon layer to more accurately prevent the doping of the active layers 135c, 138c, and 128b. Expose At this time, the metal layers 150a, 150b, 153a, 153b, 156a, and 156b that are not etched on the left and right sides of the exposed active layers 135c, 138c, and 128b are respectively source and drain electrodes 150a, 153a, 156a, and 150b. , 153b, 156b).

Next, as shown in FIGS. 4L and 5L, the photoresist pattern remaining on the source and drain electrodes 150a, 153a and 156a, and 150b, 153b and 156b (143a in FIGS. 4k and 5k). Strip and remove the protective layer by depositing or applying an inorganic insulating material or an organic insulating material on the entire surface of the substrate 100 including the source and drain electrodes 150a, 153a, 156a, and 150b, 153b, and 156b. To form 160.

Since the process is applied only to the manufacturing process of the thin film transistor, which is a switching element of the region I, which is the display unit, it is strictly referred to as a manufacturing process of the array substrate, but will be described together since the process is continuous to the above-described thin film transistor process.

4M and 5M, a mask process is performed on the passivation layer 160 to form a drain contact hole 163 exposing the drain electrode 150b in the I region.

 A transparent conductive material is deposited on the entire surface of the substrate 100 on the passivation layer 160 including the drain contact hole 163 exposing the drain electrode 150b of the region I in succession and performing a mask process. In contact with the drain electrode 150b through 163, an independent pixel electrode 166 is formed for each pixel of the I region.

In the array substrate of the drive circuit-integrated liquid crystal display device finally completed by the present invention, the structure of the driving unit and the thin film transistor formed in the display unit will be described with reference to FIGS. 4M and 5M.

The thin film transistor according to the embodiment of the present invention has a bottom gate structure in which a buffer layer 103 is formed on the substrate 100, and gate electrodes 105, 109, 112, and the buffer layer 103 are formed on the buffer layer 103. The gate insulating films 115 and 116 having a flat structure are formed on the gate electrodes 105, 109 and 112. More specifically, the gate insulating layers 115 and 116 are divided into a first gate insulating layer 115 and a second gate insulating layer 116, and are formed with a step difference between the gate electrodes 105, 109 and 112. CMP process is performed on 115 to polish and level the stepped portion on the first gate insulating film 115 by the gate electrodes 105, 109 and 112, and then the upper portion of the first gate insulating film 115. The second gate insulating layer 116 is formed again. Doped polysilicon semiconductor layers 135, 138, and 128 are formed on the second gate insulating layer 116. The semiconductor layers 135, 138, and 128 are n + and n− doped n-type ohmic contact layers 135a and 138a and LDD layers 135b and 138b in the case of n-type thin film transistors (I and II regions) of the display unit and the driver unit. ) And the undoped active layers 135c and 138c, and in the case of the p-type thin film transistor (III region) of the driver, the p-doped p-type ohmic contact layer 128b and the undoped active layer 128a. Formed. At this time, the active layers 135c, 138c, and 128b of the semiconductor layers 135, 138, and 128 are formed at positions corresponding to the lower gate electrodes 105, 109, and 112, and the active layers 135c, 138c and 128b extend from both ends and have a constant width, and are ohmic contact layers 135a, 138a and 128b, and LDD layers 135b and 138b are formed of the active layers 135c, 138c and 128b and the ohmic contact layer 135a. , 138a and 128a.

Next, the semiconductor layers 135, 138, and 128 are in contact with the ohmic contact layers 135a, 138a, and 128a including the LDD layers 135b and 138b, respectively, and the widths of the active layers 135c, 138c, and 128b are different from each other. Source and drain electrodes 150a, 153a, 156a, and 150b, 153b, and 156b are spaced apart from each other, and the source and drain electrodes 150a, 153a, 156a, 150b, 153b, and 156b. The protective layer 160 is formed on the entire surface of the substrate 100 including.

In the thin film transistor (I region) of the display unit, a portion of the passivation layer 160 is patterned to expose the drain electrode 150b, and is in contact with the exposed drain electrode 150b and over the passivation layer 160. The pixel electrode 166 is formed.

The present invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

The present invention applies a CMP process to a gate insulating film formed with a conventional step in manufacturing a bottom gate structure thin film transistor using polysilicon used as a display element and a switching element of a driving circuit integrated liquid crystal display device and a CMOS element. After the planarization process, an amorphous silicon layer is formed and crystallized to form a polysilicon layer, thereby improving crystallization characteristics.

In addition, by eliminating the step, there is an effect of preventing disconnection defects when the polysilicon layer is formed by improving step curvy.

1 is a schematic diagram of an array substrate on which drive circuits are formed using polysilicon;

2 and 3 are cross-sectional views showing cross-sections of a switching element and a CMOS element of the conventional liquid crystal display integrated with a driving circuit, respectively.

4A to 4M and FIGS. 5A to 5M are cross-sectional views illustrating manufacturing steps of a switching element of a display unit and a CMOS element of a driving unit of the liquid crystal display integrated with a driving circuit according to the present invention;

<Description of Symbols for Main Parts of Drawings>

100 substrate 103 buffer layer

109 and 112: active layer 115: first gate insulating film

120: CMP device

Claims (10)

Forming a gate electrode on the substrate; Forming a first gate insulating film over the gate electrode; Performing a chemical mechanical polishing (CMP) process on the surface of the first gate insulating layer to planarize the step of the first insulating layer on the substrate on which the first gate insulating layer is formed; Forming a second gate insulating film on the first gate insulating film planarized by the CMP process; Forming a polysilicon layer over the second gate insulating film; The polysilicon layer is defined as a first region of the central portion and a second region located on both sides of the first region, and an active layer comprising a polysilicon layer of the first region by doping the second region of the polysilicon layer. Forming a semiconductor layer comprising a layer and an ohmic contact layer comprising the second region; Forming source and drain electrodes spaced apart from each other with the active layer interposed therebetween on the semiconductor layer; Forming a protective layer on the source and drain electrodes Thin film transistor manufacturing method of the liquid crystal display device comprising a. The method of claim 1, And the minimum thickness of the first gate insulating film before the CMP process is at least 90% of the thickness of the gate electrode. The method of claim 1, The forming of the polysilicon may include forming an amorphous silicon layer; Crystallizing the amorphous silicon layer The thin film transistor manufacturing method of the liquid crystal display device further comprising. The method of claim 1, And n-doped LDD (Lightly Dopped Drain) layers are further formed between the ohmic contact layer and the active layer. The method of claim 1, And the ohmic contact layer is an n + doped ohmic contact layer. The method of claim 1, And forming a buffer layer on the substrate before the forming of the gate electrode. A gate electrode; A gate insulating film having a flat surface on the gate electrode by a chemical mechanical polishing CMP process; A semiconductor layer formed on the gate insulating layer without a step, the active layer having a portion corresponding to the gate electrode, and an ohmic contact layer having a predetermined interval extending from both ends of the active layer; Source and drain electrodes contacting the ohmic contact layer on the semiconductor layer and spaced apart from each other by a predetermined distance; A protective layer formed on the source and drain electrodes Thin film transistor of the liquid crystal display device comprising a. The method of claim 7, wherein The thin film transistor of the liquid crystal display device, wherein the gate insulating film having the flat surface includes a first gate insulating film and a second gate insulating film. The method of claim 7, wherein And the first gate insulating layer has a flat surface by grinding a step by a CMP process. A driving circuit including an n-type thin film transistor as a switching element on a substrate and having a display portion composed of a plurality of pixels defined by the intersection of a gate wiring and a data wiring, and a driving portion configured with a plurality of CMOS elements composed of n-type and p-type thin film transistors. In an integrated liquid crystal display device, Forming gate electrodes in regions I to III on a substrate defined by region I and region II and III in which the n-type thin film transistor of the display portion is formed and the n-type and p-type thin film transistor of the driving portion, respectively; Forming a first gate insulating film over the gate electrode; Performing a chemical mechanical polishing (CMP) process on the surface of the first gate insulating layer to planarize the step of the first insulating layer on the substrate on which the first gate insulating layer is formed; Forming a second gate insulating film on the first gate insulating film planarized by the CMP process; Forming a polysilicon layer over the second gate insulating film; Performing n + and n− doping to the I and II regions of the polysilicon layer and p + doping to the III region at the same time; Forming source and drain electrodes spaced apart from each other by a predetermined distance on the doped polysilicon layer; Forming a protective layer on a front surface of the source and drain electrodes; Patterning a passivation layer formed in the region to form a drain contact hole exposing a lower drain electrode; Forming a pixel electrode in contact with the exposed drain electrode over the passivation layer of the region I in which the drain contact hole is formed; Method of manufacturing an array substrate for a liquid crystal display device comprising a.