KR20050052577A - Manufacturing method for semicondutor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a gate electrode overlapped with a hard mask layer is formed to have a stepped step shape to facilitate gap fill of a subsequent interlayer insulating film, thereby preventing void formation between the gate electrodes. Process yield and device reliability can be improved by preventing short circuits between adjacent transistors and bridges between bit lines and charge storage electrodes.

Description

Manufacturing method for semiconductor device {Manufacturing method for semicondutor device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a gate electrode is formed in a structure capable of effectively filling a gap insulation layer between the gate electrodes after forming a high aspect ratio gate electrode, thereby preventing voids between gate electrodes. It relates to a method for manufacturing a semiconductor device that can improve the yield and reliability of the device.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced, and the contact hole diameter and The aspect ratio, which is the ratio of depths, increases. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, accurate and strict alignment between the masks in the contact forming process is required, so that the process margin is reduced or the process must be performed without any margin.

These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.

In the semiconductor device according to the related art, after forming a gate electrode overlapping with a hard mask layer, an interlayer insulating layer is coated with BPSG or the like, and then heat-treated to reflow to fill the space between the gate electrodes.

Here, the gate line width and spacing are reduced according to the high integration tendency of the device, and an egg etching material such as silicide or tungsten is used as the gate electrode in order to reduce the resistance of the gate electrode material. Increased.

1A to 1C illustrate a manufacturing process of a semiconductor device according to the present invention.

First, an element isolation oxide film (not shown) is formed on the semiconductor substrate 10, a gate insulating film 12 is formed on the surface of the semiconductor substrate 10, and a polysilicon layer 14 and a tungsten silicide layer are formed thereon. (16), a hard mask layer 18 of nitride material and an antireflection film 20 of oxynitride film are sequentially formed, and a photoresist pattern 22 for gate patterning is formed on the antireflection film 20. . (See FIG. 1A).

Next, the anti-reflection film 20 and the hard mask layer 18 having the photoresist pattern 22 exposed as a mask are sequentially etched to form a pattern, and the photoresist pattern 22 is removed. (See FIG. 1B).

Thereafter, the tungsten silicide layer 16, the polysilicon layer 14, and the gate insulating layer 12, which expose the anti-reflection film 20 and the hard mask layer 18 pattern as a mask, are sequentially etched to form a gate electrode. In addition, an oxide film 24 having a thickness of about 50-100 kV is formed on the entire surface of the structure, and an interlayer insulating film 26 for flattening the structure is applied to a gap fill. (See FIG. 1C).

In the method of manufacturing a semiconductor device according to the related art as described above, voids are easily formed in the spaces between the gate electrodes during a gap fill process of a subsequent interlayer insulating layer due to the high aspect ratio gate electrode, which is formed during the subsequent self-aligned contact forming process. Adjacent transistors to be electrically insulated by the polysilicon layer filling this portion are connected to each other and fail to operate normally, or a bit line bridge or a charge storage electrode bridge may be generated to reduce process yield and device reliability.

The present invention is to solve the above problems, an object of the present invention is to form a pattern in the shape of a match head by applying a silicon nitride film during spacer formation, and sequentially etched to form an inclined gate electrode to form an interlayer insulating film It provides a method of manufacturing a semiconductor device that can improve the process yield and device reliability by preventing gaps between gate electrodes and preventing short circuits between adjacent transistors or bridges between bit lines or charge storage electrodes by facilitating gap fill of the electrodes. Is in.

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

Forming a gate insulating film on the semiconductor substrate;

Sequentially applying a polysilicon layer, an upper conductive layer, and a hard mask layer made of a nitride film on the gate insulating film;

Forming a hard mask layer pattern and an upper conductive layer pattern exposing the polysilicon layer by selectively etching the hard mask layer and the upper conductive layer using a gate electrode patterning mask;

Forming a silicon silicon film on the entire surface of the structure, but thinly formed on the polycrystalline silicon layer, and thickly formed on the top and sidewalls of the hard mask layer pattern so as to be applied to form a match head;

Forming a polysilicon layer pattern by sequentially etching the polysilicon nitride layer and the polysilicon layer on the polysilicon layer, and removing a substantial portion of the matched silicon-like persilicon layer,

The remaining silicon silicon film is removed, but the hard mask layer and the upper conductive layer are also partially removed to provide a step of having a stepped slope.

In another aspect of the present invention, the gate insulating film, the polysilicon layer, the upper conductive layer, and the hard mask layer are formed to have thicknesses of 40-100 kPa, 500-2000 kPa, 500-2000 kPa, and 2000-3000 kPa, respectively. Silver is deposited by single-layer chemical vapor deposition method, 100-500Å thick, 600-800Å, 0.1-500torr, and the deposition gas is SiH4 5-60sccm and NH3 5-100sccm, but the gas ratio is SiH4: NH3 = 1: 1- It is characterized by forming on a condition of 1: 5.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are manufacturing process diagrams of a semiconductor device according to the present invention.

First, an element isolation oxide film (not shown) is formed on the semiconductor substrate 30 to define an active region, and an oxide film, a nitride film, or a gate insulating film 32 having a thickness of about 40-100 micrometers is formed on the structure; Polycrystalline silicon layer 34 of about 500-2000 mm thick, tungsten silicide layer 36 of about 500-2000 mm thick, hard mask layer 38 of about 2000-3000 mm thick and 500-1500 mm thick of nitride film material After the anti-reflection film 40 made of an oxynitride film is sequentially formed, the photoresist pattern 42, which is a mask for gate patterning, is formed on the anti-reflection film 40. In the above, instead of tungsten silicide, it may be replaced by another conductive layer such as metal silicide or metal layer. (See FIG. 2A).

Next, the anti-reflection film 40 and the hard mask layer 38 having the photoresist pattern 42 exposed as a mask are sequentially etched to expose the tungsten silicide layer 36, and the photoresist pattern 42 is removed. (See FIG. 2B).

Thereafter, the tungsten silicide layer 36, in which the anti-reflection film 40 and the hard mask layer 38 pattern are exposed as a mask, is etched to expose the polysilicon layer 34, and the step coverage is provided on the entire surface of the structure. This poor silicon silicon nitride film 44 is deposited by a single-layer chemical vapor deposition method and applied to the antireflection film 40, the hard mask layer 38, and the tungsten silicide layer 36 in a matched head shape. Wherein the silicon silicon film 44 is formed to a thickness of about 100-500Å on the entire surface, the deposition temperature is 600-800Å, 0.1-500torr, the deposition gas using SiH4 5-60sccm and NH3 5-100sccm, but the gas ratio In the process conditions of about SiH 4: NH 3 = 1: 1-1: 5, a thin layer is applied to the exposed sidewalls of the polysilicon layer 34 and the tungsten silicide layer 36, and the hard mask layer 38 It is thickly formed on the anti-reflection film 40 to have a match head shape. (See FIG. 2C).

Thereafter, the oversilicon nitride film 44 and the polysilicon layer 34 on the polysilicon layer 34 are sequentially etched to complete the gate electrode. At this time, a substantial portion of the match head of the silicon nitride film 44 is etched to remain thin on the top of the anti-reflection film 40 and on the sidewalls of the hard mask layer 38 and the tungsten silicide layer 36 pattern. (See FIG. 2D).

Subsequently, when the oversilicon nitride film 44 is removed, the anti-reflection film 40 and the hard mask layer 38 of similar material are etched together, and the tungsten silicide layer 36 is partially etched, but the extent thereof is a hard mask. Compared with the layer 38, the steps have a stepped shape, which in turn is stepped. (See FIG. 2E).

Although not shown in the drawing, when the interlayer insulating film is applied to the entire surface of the structure, the gap fill is easily performed by the stepped gate electrode and the hard mask layer pattern.

As described above, in the method of fabricating the semiconductor device according to the present invention, since the gate electrode overlapped with the hard mask layer is formed to have a stepped step, the gap fill of the subsequent interlayer insulating film is facilitated, thus forming voids between the gate electrodes. This prevents short circuits between adjacent transistors and bridges between bit lines and charge storage electrodes, thereby improving process yield and device reliability.

1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art.

2a to 2e is a manufacturing process diagram of a semiconductor device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10, 30: semiconductor substrate 12, 32: gate insulating film

14, 34 polysilicon layer 16, 36 tungsten silicide layer

18, 38: hard mask layer 20, 40: antireflection film

22, 42: photosensitive film pattern 24: oxide film

26 interlayer insulating film 44 silicon nitride film

Claims (4)

Forming a gate insulating film on the semiconductor substrate; Sequentially applying a polysilicon layer, an upper conductive layer, and a hard mask layer made of a nitride film on the gate insulating film; Forming a hard mask layer pattern and an upper conductive layer pattern exposing the polysilicon layer by selectively etching the hard mask layer and the upper conductive layer using a gate electrode patterning mask; Forming a silicon silicon film on the entire surface of the structure, but forming a thin silicon on the sidewalls of the polysilicon layer and the upper conductive layer, and thickly forming the upper and sidewalls of the hard mask layer pattern so as to be applied to form a match head; and, Forming a polysilicon layer pattern by sequentially etching the polysilicon nitride layer and the polysilicon layer on the polysilicon layer, wherein the sidewalls of the match-shaped persilicon nitride layer are also etched and removed by a predetermined thickness; Removing the remaining silicon silicon film, and simultaneously removing predetermined thicknesses of the sidewalls of the hard mask layer and the upper conductive layer to form a stepped gate electrode. The method of claim 1, And forming the gate insulating film, the polysilicon layer, the upper conductive layer, and the hard mask layer to a thickness of 40-100 kV, 500-2000 kV, 500-2000 kV, and 2000-3000 kV, respectively. The method of claim 1, The method of manufacturing a semiconductor device, characterized in that the silicon nitride film is deposited by a single-layer chemical vapor deposition method. The method of claim 3, wherein The silicon silicon film is 100-500Å thickness, 600-800Å, 0.1-500torr, the deposition gas is SiH4 5-60sccm and NH3 5-100sccm, but the gas ratio of SiH4: NH3 = 1: 1-1: 5 Forming a semiconductor device, characterized in that formed.