KR20050044247A - 피시아이 익스프레스 링크의 동적 재구성 방법 및 장치 - Google Patents
피시아이 익스프레스 링크의 동적 재구성 방법 및 장치 Download PDFInfo
- Publication number
- KR20050044247A KR20050044247A KR1020040085758A KR20040085758A KR20050044247A KR 20050044247 A KR20050044247 A KR 20050044247A KR 1020040085758 A KR1020040085758 A KR 1020040085758A KR 20040085758 A KR20040085758 A KR 20040085758A KR 20050044247 A KR20050044247 A KR 20050044247A
- Authority
- KR
- South Korea
- Prior art keywords
- link
- endpoint
- switching
- controller
- information processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Bus Control (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| USUSSN10/702,832 | 2003-11-06 | ||
| US10/702,832 US7099969B2 (en) | 2003-11-06 | 2003-11-06 | Dynamic reconfiguration of PCI Express links |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20050044247A true KR20050044247A (ko) | 2005-05-12 |
Family
ID=33541626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020040085758A Ceased KR20050044247A (ko) | 2003-11-06 | 2004-10-26 | 피시아이 익스프레스 링크의 동적 재구성 방법 및 장치 |
Country Status (9)
| Country | Link |
|---|---|
| US (2) | US7099969B2 (https=) |
| JP (1) | JP2005141739A (https=) |
| KR (1) | KR20050044247A (https=) |
| CN (2) | CN101303681B (https=) |
| DE (1) | DE102004053801B4 (https=) |
| FR (1) | FR2862147B1 (https=) |
| GB (1) | GB2407890B (https=) |
| SG (1) | SG112061A1 (https=) |
| TW (1) | TWI328168B (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100708565B1 (ko) * | 2005-01-28 | 2007-04-19 | 후지쯔 가부시끼가이샤 | 복수의 처리 노드를 시리얼 버스에 의해 상호 접속하는장치 |
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- 2003-11-06 US US10/702,832 patent/US7099969B2/en not_active Expired - Lifetime
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2004
- 2004-10-26 KR KR1020040085758A patent/KR20050044247A/ko not_active Ceased
- 2004-10-26 TW TW093132374A patent/TWI328168B/zh not_active IP Right Cessation
- 2004-10-26 JP JP2004311154A patent/JP2005141739A/ja active Pending
- 2004-10-26 SG SG200406877A patent/SG112061A1/en unknown
- 2004-11-04 GB GB0424436A patent/GB2407890B/en not_active Expired - Lifetime
- 2004-11-05 FR FR0411796A patent/FR2862147B1/fr not_active Expired - Lifetime
- 2004-11-08 DE DE102004053801.8A patent/DE102004053801B4/de not_active Expired - Lifetime
- 2004-11-08 CN CN2008100984109A patent/CN101303681B/zh not_active Expired - Lifetime
- 2004-11-08 CN CNB2004100907157A patent/CN100444145C/zh not_active Expired - Lifetime
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2006
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100708565B1 (ko) * | 2005-01-28 | 2007-04-19 | 후지쯔 가부시끼가이샤 | 복수의 처리 노드를 시리얼 버스에 의해 상호 접속하는장치 |
| US7461194B2 (en) | 2005-01-28 | 2008-12-02 | Fujitsu Limited | Apparatus for interconnecting a plurality of process nodes by serial bus |
Also Published As
| Publication number | Publication date |
|---|---|
| US20050102454A1 (en) | 2005-05-12 |
| US7293125B2 (en) | 2007-11-06 |
| FR2862147A1 (fr) | 2005-05-13 |
| CN101303681A (zh) | 2008-11-12 |
| GB0424436D0 (en) | 2004-12-08 |
| JP2005141739A (ja) | 2005-06-02 |
| US20070073959A1 (en) | 2007-03-29 |
| SG112061A1 (en) | 2005-06-29 |
| CN101303681B (zh) | 2012-06-27 |
| CN1624674A (zh) | 2005-06-08 |
| GB2407890A (en) | 2005-05-11 |
| GB2407890B (en) | 2006-07-12 |
| US7099969B2 (en) | 2006-08-29 |
| FR2862147B1 (fr) | 2007-04-06 |
| DE102004053801B4 (de) | 2015-07-30 |
| TWI328168B (en) | 2010-08-01 |
| DE102004053801A1 (de) | 2005-06-16 |
| CN100444145C (zh) | 2008-12-17 |
| TW200519613A (en) | 2005-06-16 |
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